URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/xulalx25soc/trunk/bench/cpp/sdramsim.cpp
8,10 → 8,10
int bs, unsigned addr, int driv, short data) { |
short result = 0; |
|
if (driv) |
result = data; |
else if (!clk) |
return m_last_value; |
if (driv) // If the bus is going out, reads don't make sense ... but |
result = data; // read what we output anyway |
else if (!clk) // If the clock is zero, return our last value |
return m_last_value; // Always called w/clk=1, thus never here |
if (!cke) { |
fprintf(stderr, "This simulation only supports CKE high!\n"); |
fprintf(stderr, "\tCKE = %d\n", cke); |
29,13 → 29,13
assert((ras_n)&&(cas_n)&&(we_n)); |
if (m_clocks_till_idle == 0) { |
m_pwrup++; |
printf("Successful power up wait, moving to state #1\n"); |
// printf("Successful power up wait, moving to state #1\n"); |
} |
} else if (m_pwrup == 1) { |
if ((!cs_n)&&(!ras_n)&&(cas_n)&&(!we_n)&&(addr&0x0400)) { |
// Wait until a precharge all banks command |
m_pwrup++; |
printf("Successful precharge command, moving to state #2\n"); |
// printf("Successful precharge command, moving to state #2\n"); |
m_clocks_till_idle = 8; |
} |
} else if (m_pwrup == 2) { |
43,7 → 43,7
// set command. We'll insist they be before. |
if (m_clocks_till_idle == 0) { |
m_pwrup++; |
printf("Successful initial auto-refresh, waiting for mode-set\n"); |
// printf("Successful initial auto-refresh, waiting for mode-set\n"); |
for(int i=0; i<m_nrefresh; i++) |
m_refresh_time[i] = MAX_REFRESH_TIME; |
} else |
52,10 → 52,10
const int tRSC = 2; |
if ((!cs_n)&&(!ras_n)&&(!cas_n)&&(!we_n)){ |
// mode set |
printf("Mode set: %08x\n", addr); |
// printf("Mode set: %08x\n", addr); |
assert(addr == 0x021); |
m_pwrup++; |
printf("Successful mode set, moving to state #3, tRSC = %d\n", tRSC); |
// printf("Successful mode set, moving to state #3, tRSC = %d\n", tRSC); |
m_clocks_till_idle=tRSC; |
} |
} else if (m_pwrup == 4) { |
63,7 → 63,7
if (m_clocks_till_idle == 0) { |
m_pwrup = POWERED_UP_STATE; |
m_clocks_till_idle = 0; |
printf("Successful settup! SDRAM switching to operational\n"); |
// printf("Successful settup! SDRAM switching to operational\n"); |
} else if (m_clocks_till_idle == 1) { |
; |
} else assert(0 && "Should never get here!"); |
110,15 → 110,18
} |
|
if ((m_clocks_till_idle > 0)&&(m_next_wr)) { |
printf("SDRAM[%08x] <= %04x\n", m_wr_addr, data & 0x0ffff); |
// printf("SDRAM[%08x] <= %04x\n", m_wr_addr, data & 0x0ffff); |
m_mem[m_wr_addr++] = data; |
result = data; |
m_next_wr = false; |
} else { |
result = (driv)?data:m_qdata[m_qloc]; |
} |
m_qloc = (m_qloc + 1)&m_qmask; |
result = (driv)?data:m_qdata[(m_qloc)&m_qmask]; |
m_qdata[(m_qloc)&m_qmask] = 0; |
|
// if (result != 0) |
// printf("%d RESULT[%3d] = %04x\n", clk, m_qloc, result&0x0ffff); |
|
if ((!cs_n)&&(!ras_n)&&(!cas_n)&&(we_n)) { |
// Auto-refresh command |
m_refresh_time[m_refresh_loc] = MAX_REFRESH_TIME; |
139,10 → 142,10
assert(0 == (bs & (~3))); // Assert w/in bounds |
m_bank_status[bs] &= 0x03; // Close the bank |
|
printf("Precharging bank %d\n", bs); |
// printf("Precharging bank %d\n", bs); |
} |
} else if ((!cs_n)&&(!ras_n)&&(cas_n)&&(we_n)) { |
printf("Activating bank %d\n", bs); |
// printf("Activating bank %d\n", bs); |
// Activate a bank! |
if (0 != (bs & (~3))) { |
m_fail = 2; |
158,7 → 161,7
m_bank_open_time[bs] = MAX_BANKOPEN_TIME; |
m_bank_row[bs] = addr; |
} else if ((!cs_n)&&(ras_n)&&(!cas_n)) { |
printf("R/W Op\n"); |
// printf("R/W Op\n"); |
if (!we_n) { |
// Initiate a write |
assert(0 == (bs & (~3))); // Assert w/in bounds |
171,7 → 174,7
m_wr_addr |= (addr & 0x01ff); |
|
assert(driv); |
printf("SDRAM[%08x] <= %04x\n", m_wr_addr, data & 0x0ffff); |
// printf("SDRAM[%08x] <= %04x\n", m_wr_addr, data & 0x0ffff); |
m_mem[m_wr_addr++] = data; |
m_clocks_till_idle = 2; |
m_next_wr = true; |
193,12 → 196,14
rd_addr |= (addr & 0x01ff); |
|
assert(!driv); |
printf("SDRAM.Q %04x <= SDRAM[%08x]\n", |
m_mem[rd_addr] & 0x0ffff, rd_addr); |
m_qdata[(m_qloc+1)&m_qmask] = m_mem[rd_addr++]; |
printf("SDRAM.Q %04x <= SDRAM[%08x]\n", |
m_mem[rd_addr] & 0x0ffff, rd_addr); |
m_qdata[(m_qloc+2)&m_qmask] = m_mem[rd_addr++]; |
// printf("SDRAM.Q[%2d] %04x <= SDRAM[%08x]\n", |
// (m_qloc+3)&m_qmask, |
// m_mem[rd_addr] & 0x0ffff, rd_addr); |
m_qdata[(m_qloc+3)&m_qmask] = m_mem[rd_addr++]; |
// printf("SDRAM.Q[%2d] %04x <= SDRAM[%08x]\n", |
// (m_qloc+4)&m_qmask, |
// m_mem[rd_addr] & 0x0ffff, rd_addr); |
m_qdata[(m_qloc+4)&m_qmask] = m_mem[rd_addr++]; |
m_clocks_till_idle = 2; |
|
if (addr & 0x0400) { // Auto precharge |
/xulalx25soc/trunk/bench/cpp/sdramsim.h
6,6 → 6,7
#define PWRUP_WAIT_CKS ((int)(.000200 * CLK_RATE_HZ)) |
#define MAX_BANKOPEN_TIME ((int)(.000100 * CLK_RATE_HZ)) |
#define MAX_REFRESH_TIME ((int)(.064 * CLK_RATE_HZ)) |
#define SDRAM_QSZ 16 |
|
class SDRAMSIM { |
int m_pwrup; |
16,7 → 17,7
int m_bank_open_time[NBANKS]; |
unsigned *m_refresh_time; |
int m_refresh_loc, m_nrefresh; |
int m_qloc, m_qdata[8], m_qmask, m_wr_addr; |
int m_qloc, m_qdata[SDRAM_QSZ], m_qmask, m_wr_addr; |
int m_clocks_till_idle; |
bool m_next_wr; |
unsigned m_fail; |
37,7 → 38,7
m_wr_addr = 0; |
|
m_qloc = 0; |
m_qmask = 7; |
m_qmask = SDRAM_QSZ-1; |
|
m_next_wr = true; |
m_fail = 0; |
/xulalx25soc/trunk/bench/cpp/pipecmdr.h
147,8 → 147,12
m_started_flag = true; |
} else if (m_ilen < 0) { |
// An error occurred, close the connection |
perror("Read error: "); |
fprintf(stderr, "Closing connection\n"); |
// This could also be the |
// indication of a simple |
// connection close, so we deal |
// with this quietly. |
// perror("Read error: "); |
// fprintf(stderr, "Closing connection\n"); |
close(m_con); |
m_con = -1; |
} else { // the connection closed on us |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
79,39 → 79,17
|
bool writeout = false; |
/* |
if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__rx_stb) |
if (m_core->v__DOT__sdram__DOT__r_pending) |
writeout = true; |
else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2iface__DOT__state != m_last_ps2_state) |
else if (m_core->v__DOT__sdram__DOT__bank_active[0]) |
writeout = true; |
else if (m_core->v__DOT__runio__DOT__themouse__DOT__m_state != m_last_mouse_state) |
else if (m_core->v__DOT__sdram__DOT__bank_active[1]) |
writeout = true; |
else if (m_core->i_ps2 != m_last_ps2) |
else if (m_core->v__DOT__sdram__DOT__bank_active[2]) |
writeout = true; |
else if (m_core->o_ps2 != m_last_ops2) |
else if (m_core->v__DOT__sdram__DOT__bank_active[3]) |
writeout = true; |
else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2_perr) |
writeout = true; |
else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2_ferr) |
writeout = true; |
*/ |
// if ((m_core->v__DOT__genbus__DOT__runwb__DOT__o_wb_cyc)||(m_core->v__DOT__bus_cyc)) |
// writeout = true; |
// else if (m_last_cyc) |
// writeout = true; |
if ((m_tickcount > 0x5010)&&(m_core->v__DOT__sdram__DOT__r_state != 0)) |
writeout = true; |
else if ((m_core->v__DOT__dwb_cyc)&&((m_core->v__DOT__wb_stb) |
||(m_core->v__DOT__dwb_stall) |
||(m_core->v__DOT__dwb_ack))) |
writeout = true; |
else if (m_core->v__DOT__dwb_cyc) |
writeout = true; |
else if (m_core->v__DOT__sdram__DOT__need_refresh) |
writeout = true; |
else if ((m_core->v__DOT__wbu_cyc)&&((m_core->v__DOT__wbu_addr == 0x106)||(m_core->v__DOT__wbu_addr == 0x0107))) |
writeout = true; |
if (m_tickcount < 0x05010) |
writeout = false; |
if (writeout) { |
printf("%08lx:", m_tickcount); |
|
166,13 → 144,15
(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ", |
(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ", |
(m_core->v__DOT__sdram__DOT__r_we)?'W':'R', |
(m_core->v__DOT__sdram__DOT__r_data), |
(m_core->v__DOT__sdram__DOT__r_we) |
?(m_core->v__DOT__sdram__DOT__r_data) |
:(m_core->v__DOT__sdram_data), |
(m_core->v__DOT__sdram__DOT__r_addr)); |
|
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x", |
(m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-", |
(m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-", |
(m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-", |
printf("%s%s%s%s%s%s%s%s%s%s%s%2x", |
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-", |
// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-", |
// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-", |
(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-", |
(m_core->v__DOT__zippy__DOT__cpu_dbg_stall)?"Z":"-", |
(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-", |
/xulalx25soc/trunk/rtl/wbsdram.v
458,10 → 458,24
r_barrell_ack[(RDLY-1):0] <= 0; |
end |
|
|
`ifdef VERILATOR |
// While I hate to build something that works one way under Verilator |
// and another way in practice, this really isn't that. The problem |
// Verilator is having is resolved in toplevel.v--one file that |
// Verilator doesn't implement. In toplevel.v, there's not only a |
// single clocked latch but two taking place. Here, we replicate one |
// of those. The second takes place (somehow) within the sdramsim.cpp |
// file. |
reg [15:0] ram_data, last_ram_data; |
always @(posedge i_clk) |
ram_data <= i_ram_data; |
always @(posedge i_clk) |
last_ram_data <= ram_data; |
`else |
reg [15:0] last_ram_data; |
always @(posedge i_clk) |
last_ram_data <= i_ram_data; |
`endif |
assign o_wb_ack = r_barrell_ack[0]; |
assign o_wb_data = { last_ram_data, i_ram_data }; |
|