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/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v File deleted \ No newline at end of file
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc-testbench-defines.v
0,0 → 1,2
 
 
/openrisc/trunk/orpsocv2/bench/verilog/uart_stim.v
0,0 → 1,108
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench UART Stimulus ////
//// ////
//// Description ////
//// ORPSoC Testbench UART input generator ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - jb, jb@orsoc.se ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// Encodes 8-bit, 1 stop bit, no parity UART signals at 115200 buad
`timescale 1ns/1ns
module uart_stim(clk, uart_rx);
 
input clk;
output reg uart_rx;
 
 
// Default baud of 115200, period (ns)
parameter uart_baudrate_period_ns = 8680;
 
// Uart Stim file - we include it
parameter stim_file = "uart0_stim.v";
// Something to trigger the task
reg [7:0] next_byte;
parameter len = 11; // Number of chars in string
reg [(len*8)-1:0] uart_string;
integer i;
 
/*
initial
begin
uart_rx = 1;
uart_string = "dhry 100\n!\n";
#12_000_000;
for(i=0;i<len;i=i+1)
begin
uart_tx_byte(uart_string[(len*8)-1:(len*8)-8]);
#20_000_000;
// Shift along string
uart_string = {uart_string[(len*8)-9:0],8'h00};
end
end
*/
// Task to drive UART RX line (transmit a char) - 1 stop bit, no parity
task uart_tx_byte;
input [7:0] tx_byte;
begin
// Start bit
uart_rx = 1'b0;
#uart_baudrate_period_ns;
uart_rx = tx_byte[0];
#uart_baudrate_period_ns;
uart_rx = tx_byte[1];
#uart_baudrate_period_ns;
uart_rx = tx_byte[2];
#uart_baudrate_period_ns;
uart_rx = tx_byte[3];
#uart_baudrate_period_ns;
uart_rx = tx_byte[4];
#uart_baudrate_period_ns;
uart_rx = tx_byte[5];
#uart_baudrate_period_ns;
uart_rx = tx_byte[6];
#uart_baudrate_period_ns;
uart_rx = tx_byte[7];
#uart_baudrate_period_ns;
// Stop bit
uart_rx = 1'b1;
#uart_baudrate_period_ns;
end
endtask // uart_tx_byte
 
endmodule // uart_decoder
/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc-defines ////
//// ////
//// Top level ORPSoC defines file ////
//// ////
//// Included in toplevel and testbench ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// Define board clock - main system clock period
// 20ns period = 50MHz freq.
`define BOARD_CLOCK_PERIOD_NS 20
 
// Included modules: define to include
`define JTAG_DEBUG
`define UART0
 
// end of included module defines - keep this comment line here
 
//
// Arbiter defines
//
 
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
 
// Data bus arbiter
 
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
 
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
 
/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-params.v
0,0 → 1,121
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc-params ////
//// ////
//// Top level ORPSoC parameters file ////
//// ////
//// Included in toplevel and testbench ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
///////////////////////////
// //
// Peripheral parameters //
// //
///////////////////////////
 
// UART 0 params
parameter wbs_d_uart0_data_width = 8;
parameter uart0_wb_adr = 8'h90;
parameter uart0_data_width = 8;
parameter uart0_addr_width = 3;
 
// ROM
parameter wbs_i_rom0_data_width = 32;
parameter wbs_i_rom0_addr_width = 6;
parameter rom0_wb_adr = 4'hf;
 
//////////////////////////////////////////////////////
// //
// Wishbone bus parameters //
// //
//////////////////////////////////////////////////////
 
////////////////////////
// //
// Arbiter parameters //
// //
////////////////////////
 
parameter wb_dw = 32; // Default Wishbone full word width
parameter wb_aw = 32; // Default Wishbone full address width
 
///////////////////////////
// //
// Instruction bus //
// //
///////////////////////////
parameter ibus_arb_addr_match_width = 4;
// Slave addresses
parameter ibus_arb_slave0_adr = rom0_wb_adr; // ROM
parameter ibus_arb_slave1_adr = 4'h0; // Main memory
 
///////////////////////////
// //
// Data bus //
// //
///////////////////////////
// Has auto foward to last slave when no address hits
parameter dbus_arb_wb_addr_match_width = 8;
parameter dbus_arb_wb_num_slaves = 2;
// Slave addresses
parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
parameter dbus_arb_slave1_adr = 8'hxx; // Default slave - address don't care (X)
 
///////////////////////////////
// //
// Byte-wide peripheral bus //
// //
///////////////////////////////
parameter bbus_arb_wb_addr_match_width = 8;
parameter bbus_arb_wb_num_slaves = 1; // Update this when changing slaves!
// Slave addresses
parameter bbus_arb_slave0_adr = uart0_wb_adr;
parameter bbus_arb_slave1_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave2_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave3_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave4_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave5_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave6_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave7_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave8_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave9_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave10_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave11_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave12_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave13_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave14_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave15_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave16_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave17_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave18_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave19_adr = 0 /* UNASSIGNED */;
 
 
 
 
/openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v
0,0 → 1,1192
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, byte-wide data path, no bursting ////
/// ////
/// Simple arbiter, single master, multiple slave, for byte-wide ////
/// peripherals ////
/// ////
/// Julius Baxter, julius@opencores.org ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//
// Things to update when changing slave config:
//
// 1. Port list
// 2. Port specification
// 3. Slave addr select parameter
// 4. Slave addr selects
// 5. Slave input mux logic
// 6. The four different master out mux logics (dat_o mux, and ack, rty & err)
//
`include "orpsoc-defines.v"
module arbiter_bytebus
(
 
// Master in
wbm0_adr_o,
wbm0_dat_o,
wbm0_sel_o,
wbm0_we_o,
wbm0_cyc_o,
wbm0_stb_o,
wbm0_cti_o,
wbm0_bte_o,
wbm0_dat_i,
wbm0_ack_i,
wbm0_err_i,
wbm0_rty_i,
 
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
/*
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
 
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
wbs2_dat_i,
wbs2_we_i,
wbs2_cyc_i,
wbs2_stb_i,
wbs2_cti_i,
wbs2_bte_i,
wbs2_dat_o,
wbs2_ack_o,
wbs2_err_o,
wbs2_rty_o,
 
// Slave four
// Wishbone Slave interface
wbs3_adr_i,
wbs3_dat_i,
wbs3_we_i,
wbs3_cyc_i,
wbs3_stb_i,
wbs3_cti_i,
wbs3_bte_i,
wbs3_dat_o,
wbs3_ack_o,
wbs3_err_o,
wbs3_rty_o,
 
// Slave five
// Wishbone Slave interface
wbs4_adr_i,
wbs4_dat_i,
wbs4_we_i,
wbs4_cyc_i,
wbs4_stb_i,
wbs4_cti_i,
wbs4_bte_i,
wbs4_dat_o,
wbs4_ack_o,
wbs4_err_o,
wbs4_rty_o,
 
// Slave six
// Wishbone Slave interface
wbs5_adr_i,
wbs5_dat_i,
wbs5_we_i,
wbs5_cyc_i,
wbs5_stb_i,
wbs5_cti_i,
wbs5_bte_i,
wbs5_dat_o,
wbs5_ack_o,
wbs5_err_o,
wbs5_rty_o,
 
// Slave seven
// Wishbone Slave interface
wbs6_adr_i,
wbs6_dat_i,
wbs6_we_i,
wbs6_cyc_i,
wbs6_stb_i,
wbs6_cti_i,
wbs6_bte_i,
wbs6_dat_o,
wbs6_ack_o,
wbs6_err_o,
wbs6_rty_o,
 
// Slave eight
// Wishbone Slave interface
wbs7_adr_i,
wbs7_dat_i,
wbs7_we_i,
wbs7_cyc_i,
wbs7_stb_i,
wbs7_cti_i,
wbs7_bte_i,
wbs7_dat_o,
wbs7_ack_o,
wbs7_err_o,
wbs7_rty_o,
 
// Slave nine
// Wishbone Slave interface
wbs8_adr_i,
wbs8_dat_i,
wbs8_we_i,
wbs8_cyc_i,
wbs8_stb_i,
wbs8_cti_i,
wbs8_bte_i,
wbs8_dat_o,
wbs8_ack_o,
wbs8_err_o,
wbs8_rty_o,
 
// Slave ten
// Wishbone Slave interface
wbs9_adr_i,
wbs9_dat_i,
wbs9_we_i,
wbs9_cyc_i,
wbs9_stb_i,
wbs9_cti_i,
wbs9_bte_i,
wbs9_dat_o,
wbs9_ack_o,
wbs9_err_o,
wbs9_rty_o,
 
// Slave eleven
// Wishbone Slave interface
wbs10_adr_i,
wbs10_dat_i,
wbs10_we_i,
wbs10_cyc_i,
wbs10_stb_i,
wbs10_cti_i,
wbs10_bte_i,
wbs10_dat_o,
wbs10_ack_o,
wbs10_err_o,
wbs10_rty_o,
 
// Slave twelve
// Wishbone Slave interface
wbs11_adr_i,
wbs11_dat_i,
wbs11_we_i,
wbs11_cyc_i,
wbs11_stb_i,
wbs11_cti_i,
wbs11_bte_i,
wbs11_dat_o,
wbs11_ack_o,
wbs11_err_o,
wbs11_rty_o,
 
// Slave thirteen
// Wishbone Slave interface
wbs12_adr_i,
wbs12_dat_i,
wbs12_we_i,
wbs12_cyc_i,
wbs12_stb_i,
wbs12_cti_i,
wbs12_bte_i,
wbs12_dat_o,
wbs12_ack_o,
wbs12_err_o,
wbs12_rty_o,
 
// Slave fourteen
// Wishbone Slave interface
wbs13_adr_i,
wbs13_dat_i,
wbs13_we_i,
wbs13_cyc_i,
wbs13_stb_i,
wbs13_cti_i,
wbs13_bte_i,
wbs13_dat_o,
wbs13_ack_o,
wbs13_err_o,
wbs13_rty_o,
 
// Slave fifteen
// Wishbone Slave interface
wbs14_adr_i,
wbs14_dat_i,
wbs14_we_i,
wbs14_cyc_i,
wbs14_stb_i,
wbs14_cti_i,
wbs14_bte_i,
wbs14_dat_o,
wbs14_ack_o,
wbs14_err_o,
wbs14_rty_o,
 
// Slave sixteen
// Wishbone Slave interface
wbs15_adr_i,
wbs15_dat_i,
wbs15_we_i,
wbs15_cyc_i,
wbs15_stb_i,
wbs15_cti_i,
wbs15_bte_i,
wbs15_dat_o,
wbs15_ack_o,
wbs15_err_o,
wbs15_rty_o,
 
// Slave seventeen
// Wishbone Slave interface
wbs16_adr_i,
wbs16_dat_i,
wbs16_we_i,
wbs16_cyc_i,
wbs16_stb_i,
wbs16_cti_i,
wbs16_bte_i,
wbs16_dat_o,
wbs16_ack_o,
wbs16_err_o,
wbs16_rty_o,
 
 
// Slave eighteen
// Wishbone Slave interface
wbs17_adr_i,
wbs17_dat_i,
wbs17_we_i,
wbs17_cyc_i,
wbs17_stb_i,
wbs17_cti_i,
wbs17_bte_i,
wbs17_dat_o,
wbs17_ack_o,
wbs17_err_o,
wbs17_rty_o,
// Slave nineteen
// Wishbone Slave interface
wbs18_adr_i,
wbs18_dat_i,
wbs18_we_i,
wbs18_cyc_i,
wbs18_stb_i,
wbs18_cti_i,
wbs18_bte_i,
wbs18_dat_o,
wbs18_ack_o,
wbs18_err_o,
wbs18_rty_o,
// Slave twenty
// Wishbone Slave interface
wbs19_adr_i,
wbs19_dat_i,
wbs19_we_i,
wbs19_cyc_i,
wbs19_stb_i,
wbs19_cti_i,
wbs19_bte_i,
wbs19_dat_o,
wbs19_ack_o,
wbs19_err_o,
wbs19_rty_o,
*/
wb_clk, wb_rst
);
 
parameter wb_dat_width = 32;
parameter wbs_dat_width = 8;
parameter wb_adr_width = 32;
 
parameter wb_addr_match_width = 8;
 
parameter wb_num_slaves = 20; // Currently can handle up to 20
 
// Slave addresses
parameter slave0_adr = 8'h00;
parameter slave1_adr = 8'h00;
parameter slave2_adr = 8'h00;
parameter slave3_adr = 8'h00;
parameter slave4_adr = 8'h00;
parameter slave5_adr = 8'h00;
parameter slave6_adr = 8'h00;
parameter slave7_adr = 8'h00;
parameter slave8_adr = 8'h00;
parameter slave9_adr = 8'h00;
parameter slave10_adr = 8'h00;
parameter slave11_adr = 8'h00;
parameter slave12_adr = 8'h00;
parameter slave13_adr = 8'h00;
parameter slave14_adr = 8'h00;
parameter slave15_adr = 8'h00;
parameter slave16_adr = 8'h00;
parameter slave17_adr = 8'h00;
parameter slave18_adr = 8'h00;
parameter slave19_adr = 8'h00;
 
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
input wb_clk;
input wb_rst;
// WB Master one
input [wb_adr_width-1:0] wbm0_adr_o;
input [wb_dat_width-1:0] wbm0_dat_o;
input [3:0] wbm0_sel_o;
input wbm0_we_o;
input wbm0_cyc_o;
input wbm0_stb_o;
input [2:0] wbm0_cti_o;
input [1:0] wbm0_bte_o;
output [wb_dat_width-1:0] wbm0_dat_i;
output wbm0_ack_i;
output wbm0_err_i;
output wbm0_rty_i;
// Slave one
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs0_adr_i;
output [wbs_dat_width-1:0] wbs0_dat_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wbs_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs1_adr_i;
output [wbs_dat_width-1:0] wbs1_dat_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wbs_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs2_adr_i;
output [wbs_dat_width-1:0] wbs2_dat_i;
output wbs2_we_i;
output wbs2_cyc_i;
output wbs2_stb_i;
output [2:0] wbs2_cti_i;
output [1:0] wbs2_bte_i;
input [wbs_dat_width-1:0] wbs2_dat_o;
input wbs2_ack_o;
input wbs2_err_o;
input wbs2_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs3_adr_i;
output [wbs_dat_width-1:0] wbs3_dat_i;
output wbs3_we_i;
output wbs3_cyc_i;
output wbs3_stb_i;
output [2:0] wbs3_cti_i;
output [1:0] wbs3_bte_i;
input [wbs_dat_width-1:0] wbs3_dat_o;
input wbs3_ack_o;
input wbs3_err_o;
input wbs3_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs4_adr_i;
output [wbs_dat_width-1:0] wbs4_dat_i;
output wbs4_we_i;
output wbs4_cyc_i;
output wbs4_stb_i;
output [2:0] wbs4_cti_i;
output [1:0] wbs4_bte_i;
input [wbs_dat_width-1:0] wbs4_dat_o;
input wbs4_ack_o;
input wbs4_err_o;
input wbs4_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs5_adr_i;
output [wbs_dat_width-1:0] wbs5_dat_i;
output wbs5_we_i;
output wbs5_cyc_i;
output wbs5_stb_i;
output [2:0] wbs5_cti_i;
output [1:0] wbs5_bte_i;
input [wbs_dat_width-1:0] wbs5_dat_o;
input wbs5_ack_o;
input wbs5_err_o;
input wbs5_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs6_adr_i;
output [wbs_dat_width-1:0] wbs6_dat_i;
output wbs6_we_i;
output wbs6_cyc_i;
output wbs6_stb_i;
output [2:0] wbs6_cti_i;
output [1:0] wbs6_bte_i;
input [wbs_dat_width-1:0] wbs6_dat_o;
input wbs6_ack_o;
input wbs6_err_o;
input wbs6_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs7_adr_i;
output [wbs_dat_width-1:0] wbs7_dat_i;
output wbs7_we_i;
output wbs7_cyc_i;
output wbs7_stb_i;
output [2:0] wbs7_cti_i;
output [1:0] wbs7_bte_i;
input [wbs_dat_width-1:0] wbs7_dat_o;
input wbs7_ack_o;
input wbs7_err_o;
input wbs7_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs8_adr_i;
output [wbs_dat_width-1:0] wbs8_dat_i;
output wbs8_we_i;
output wbs8_cyc_i;
output wbs8_stb_i;
output [2:0] wbs8_cti_i;
output [1:0] wbs8_bte_i;
input [wbs_dat_width-1:0] wbs8_dat_o;
input wbs8_ack_o;
input wbs8_err_o;
input wbs8_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs9_adr_i;
output [wbs_dat_width-1:0] wbs9_dat_i;
output wbs9_we_i;
output wbs9_cyc_i;
output wbs9_stb_i;
output [2:0] wbs9_cti_i;
output [1:0] wbs9_bte_i;
input [wbs_dat_width-1:0] wbs9_dat_o;
input wbs9_ack_o;
input wbs9_err_o;
input wbs9_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs10_adr_i;
output [wbs_dat_width-1:0] wbs10_dat_i;
output wbs10_we_i;
output wbs10_cyc_i;
output wbs10_stb_i;
output [2:0] wbs10_cti_i;
output [1:0] wbs10_bte_i;
input [wbs_dat_width-1:0] wbs10_dat_o;
input wbs10_ack_o;
input wbs10_err_o;
input wbs10_rty_o;
 
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs11_adr_i;
output [wbs_dat_width-1:0] wbs11_dat_i;
output wbs11_we_i;
output wbs11_cyc_i;
output wbs11_stb_i;
output [2:0] wbs11_cti_i;
output [1:0] wbs11_bte_i;
input [wbs_dat_width-1:0] wbs11_dat_o;
input wbs11_ack_o;
input wbs11_err_o;
input wbs11_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs12_adr_i;
output [wbs_dat_width-1:0] wbs12_dat_i;
output wbs12_we_i;
output wbs12_cyc_i;
output wbs12_stb_i;
output [2:0] wbs12_cti_i;
output [1:0] wbs12_bte_i;
input [wbs_dat_width-1:0] wbs12_dat_o;
input wbs12_ack_o;
input wbs12_err_o;
input wbs12_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs13_adr_i;
output [wbs_dat_width-1:0] wbs13_dat_i;
output wbs13_we_i;
output wbs13_cyc_i;
output wbs13_stb_i;
output [2:0] wbs13_cti_i;
output [1:0] wbs13_bte_i;
input [wbs_dat_width-1:0] wbs13_dat_o;
input wbs13_ack_o;
input wbs13_err_o;
input wbs13_rty_o;
 
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs14_adr_i;
output [wbs_dat_width-1:0] wbs14_dat_i;
output wbs14_we_i;
output wbs14_cyc_i;
output wbs14_stb_i;
output [2:0] wbs14_cti_i;
output [1:0] wbs14_bte_i;
input [wbs_dat_width-1:0] wbs14_dat_o;
input wbs14_ack_o;
input wbs14_err_o;
input wbs14_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs15_adr_i;
output [wbs_dat_width-1:0] wbs15_dat_i;
output wbs15_we_i;
output wbs15_cyc_i;
output wbs15_stb_i;
output [2:0] wbs15_cti_i;
output [1:0] wbs15_bte_i;
input [wbs_dat_width-1:0] wbs15_dat_o;
input wbs15_ack_o;
input wbs15_err_o;
input wbs15_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs16_adr_i;
output [wbs_dat_width-1:0] wbs16_dat_i;
output wbs16_we_i;
output wbs16_cyc_i;
output wbs16_stb_i;
output [2:0] wbs16_cti_i;
output [1:0] wbs16_bte_i;
input [wbs_dat_width-1:0] wbs16_dat_o;
input wbs16_ack_o;
input wbs16_err_o;
input wbs16_rty_o;
 
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs17_adr_i;
output [wbs_dat_width-1:0] wbs17_dat_i;
output wbs17_we_i;
output wbs17_cyc_i;
output wbs17_stb_i;
output [2:0] wbs17_cti_i;
output [1:0] wbs17_bte_i;
input [wbs_dat_width-1:0] wbs17_dat_o;
input wbs17_ack_o;
input wbs17_err_o;
input wbs17_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs18_adr_i;
output [wbs_dat_width-1:0] wbs18_dat_i;
output wbs18_we_i;
output wbs18_cyc_i;
output wbs18_stb_i;
output [2:0] wbs18_cti_i;
output [1:0] wbs18_bte_i;
input [wbs_dat_width-1:0] wbs18_dat_o;
input wbs18_ack_o;
input wbs18_err_o;
input wbs18_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs19_adr_i;
output [wbs_dat_width-1:0] wbs19_dat_i;
output wbs19_we_i;
output wbs19_cyc_i;
output wbs19_stb_i;
output [2:0] wbs19_cti_i;
output [1:0] wbs19_bte_i;
input [wbs_dat_width-1:0] wbs19_dat_o;
input wbs19_ack_o;
input wbs19_err_o;
input wbs19_rty_o;
*/
 
reg watchdog_err;
// Master input mux output wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wbs_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
wire [wbs_dat_width-1:0] wbm_dat_byte_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
 
// Master input mux (not really used, only one master on this bus)
assign wbm_adr_o = wbm0_adr_o;
 
// Select the right byte and put it on the data out line
// !BIG ENDIAN!
assign wbm_dat_o = wbm0_sel_o[3] ? wbm0_dat_o[31:24] :
wbm0_sel_o[2] ? wbm0_dat_o[23:16] :
wbm0_sel_o[1] ? wbm0_dat_o[15:8] :
wbm0_dat_o[7:0];
assign wbm_we_o = wbm0_we_o;
assign wbm_cyc_o = wbm0_stb_o;
assign wbm_stb_o = wbm0_stb_o;
 
// Will we really need these for byte-peripherals
assign wbm_cti_o = wbm0_cti_o;
assign wbm_bte_o = wbm0_bte_o;
 
// Signals back to the master
assign wbm0_dat_i = (wbm0_sel_o[3]) ? {wbm_dat_byte_i, 24'd0} :
(wbm0_sel_o[2]) ? {8'd0, wbm_dat_byte_i, 16'd0} :
(wbm0_sel_o[1]) ? {16'd0, wbm_dat_byte_i, 8'd0} :
{24'd0, wbm_dat_byte_i};
 
assign wbm0_ack_i = wbm_ack_i;
assign wbm0_err_i = wbm_err_i;
assign wbm0_rty_i = wbm_rty_i;
 
`ifdef ARBITER_BYTEBUS_WATCHDOG
reg [`ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
 
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
 
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
 
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
`else // !`ifdef ARBITER_BYTEBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
`endif // !`ifdef ARBITER_BYTEBUS_WATCHDOG
 
// Wishbone slave mux out wires
wire [wb_adr_width-1:0] wbs_adr_i;
wire [wbs_dat_width-1:0] wbs_dat_i;
wire wbs_we_i;
wire wbs_cyc_i;
wire wbs_stb_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [wbs_dat_width-1:0] wbs_dat_o;
wire wbs_ack_o;
wire wbs_err_o;
wire wbs_rty_o;
 
// Slave select wire
wire [wb_num_slaves-1:0] wb_slave_sel;
// Slave out mux in wires
wire [wbs_dat_width-1:0] wbs_dat_o_mux_i [0:wb_num_slaves-1];
wire wbs_ack_o_mux_i [0:wb_num_slaves-1];
wire wbs_err_o_mux_i [0:wb_num_slaves-1];
wire wbs_rty_o_mux_i [0:wb_num_slaves-1];
 
// Slave selects
assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
/*
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr;
assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr;
assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr;
assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr;
assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr;
assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr;
assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr;
assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave17_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave18_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave19_adr;
*/
 
 
// Assign master inputs to slaves and slave inputs for MUXing back to master
 
// Slave 0 inputs
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel[0];
assign wbs0_stb_i = wbm_stb_o & wb_slave_sel[0];
assign wbs0_we_i = wbm_we_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
 
/*
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
assign wbs1_we_i = wbm_we_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
 
 
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
assign wbs2_we_i = wbm_we_o;
assign wbs2_cti_i = wbm_cti_o;
assign wbs2_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel[2];
assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel[2];
assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel[2];
 
 
// Slave 3 inputs
assign wbs3_adr_i = wbm_adr_o;
assign wbs3_dat_i = wbm_dat_o;
assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel[3];
assign wbs3_stb_i = wbm_stb_o & wb_slave_sel[3];
assign wbs3_we_i = wbm_we_o;
assign wbs3_cti_i = wbm_cti_o;
assign wbs3_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel[3];
assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel[3];
assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel[3];
 
 
// Slave 4 inputs
assign wbs4_adr_i = wbm_adr_o;
assign wbs4_dat_i = wbm_dat_o;
assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel[4];
assign wbs4_stb_i = wbm_stb_o & wb_slave_sel[4];
assign wbs4_we_i = wbm_we_o;
assign wbs4_cti_i = wbm_cti_o;
assign wbs4_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel[4];
assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel[4];
assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel[4];
 
 
// Slave 5 inputs
assign wbs5_adr_i = wbm_adr_o;
assign wbs5_dat_i = wbm_dat_o;
assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel[5];
assign wbs5_stb_i = wbm_stb_o & wb_slave_sel[5];
assign wbs5_we_i = wbm_we_o;
assign wbs5_cti_i = wbm_cti_o;
assign wbs5_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[5] = wbs5_dat_o;
assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel[5];
assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel[5];
assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel[5];
 
 
// Slave 6 inputs
assign wbs6_adr_i = wbm_adr_o;
assign wbs6_dat_i = wbm_dat_o;
assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel[6];
assign wbs6_stb_i = wbm_stb_o & wb_slave_sel[6];
assign wbs6_we_i = wbm_we_o;
assign wbs6_cti_i = wbm_cti_o;
assign wbs6_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[6] = wbs6_dat_o;
assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel[6];
assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel[6];
assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel[6];
 
 
// Slave 7 inputs
assign wbs7_adr_i = wbm_adr_o;
assign wbs7_dat_i = wbm_dat_o;
assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel[7];
assign wbs7_stb_i = wbm_stb_o & wb_slave_sel[7];
assign wbs7_we_i = wbm_we_o;
assign wbs7_cti_i = wbm_cti_o;
assign wbs7_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[7] = wbs7_dat_o;
assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel[7];
assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel[7];
assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel[7];
 
 
// Slave 8 inputs
assign wbs8_adr_i = wbm_adr_o;
assign wbs8_dat_i = wbm_dat_o;
assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel[8];
assign wbs8_stb_i = wbm_stb_o & wb_slave_sel[8];
assign wbs8_we_i = wbm_we_o;
assign wbs8_cti_i = wbm_cti_o;
assign wbs8_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[8] = wbs8_dat_o;
assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel[8];
assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel[8];
assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel[8];
 
 
// Slave 9 inputs
assign wbs9_adr_i = wbm_adr_o;
assign wbs9_dat_i = wbm_dat_o;
assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel[9];
assign wbs9_stb_i = wbm_stb_o & wb_slave_sel[9];
assign wbs9_we_i = wbm_we_o;
assign wbs9_cti_i = wbm_cti_o;
assign wbs9_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[9] = wbs9_dat_o;
assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel[9];
assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel[9];
assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel[9];
 
 
// Slave 10 inputs
assign wbs10_adr_i = wbm_adr_o;
assign wbs10_dat_i = wbm_dat_o;
assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel[10];
assign wbs10_stb_i = wbm_stb_o & wb_slave_sel[10];
assign wbs10_we_i = wbm_we_o;
assign wbs10_cti_i = wbm_cti_o;
assign wbs10_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[10] = wbs10_dat_o;
assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel[10];
assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel[10];
assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel[10];
 
// Slave 11 inputs
assign wbs11_adr_i = wbm_adr_o;
assign wbs11_dat_i = wbm_dat_o;
assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel[11];
assign wbs11_stb_i = wbm_stb_o & wb_slave_sel[11];
assign wbs11_we_i = wbm_we_o;
assign wbs11_cti_i = wbm_cti_o;
assign wbs11_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[11] = wbs11_dat_o;
assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel[11];
assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel[11];
assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel[11];
 
// Slave 12 inputs
assign wbs12_adr_i = wbm_adr_o;
assign wbs12_dat_i = wbm_dat_o;
assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel[12];
assign wbs12_stb_i = wbm_stb_o & wb_slave_sel[12];
assign wbs12_we_i = wbm_we_o;
assign wbs12_cti_i = wbm_cti_o;
assign wbs12_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[12] = wbs12_dat_o;
assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel[12];
assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel[12];
assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel[12];
 
 
// Slave 13 inputs
assign wbs13_adr_i = wbm_adr_o;
assign wbs13_dat_i = wbm_dat_o;
assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel[13];
assign wbs13_stb_i = wbm_stb_o & wb_slave_sel[13];
assign wbs13_we_i = wbm_we_o;
assign wbs13_cti_i = wbm_cti_o;
assign wbs13_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[13] = wbs13_dat_o;
assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel[13];
assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel[13];
assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel[13];
 
 
// Slave 14 inputs
assign wbs14_adr_i = wbm_adr_o;
assign wbs14_dat_i = wbm_dat_o;
assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel[14];
assign wbs14_stb_i = wbm_stb_o & wb_slave_sel[14];
assign wbs14_we_i = wbm_we_o;
assign wbs14_cti_i = wbm_cti_o;
assign wbs14_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[14] = wbs14_dat_o;
assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel[14];
assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel[14];
assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel[14];
 
 
// Slave 15 inputs
assign wbs15_adr_i = wbm_adr_o;
assign wbs15_dat_i = wbm_dat_o;
assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel[15];
assign wbs15_stb_i = wbm_stb_o & wb_slave_sel[15];
assign wbs15_we_i = wbm_we_o;
assign wbs15_cti_i = wbm_cti_o;
assign wbs15_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[15] = wbs15_dat_o;
assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel[15];
assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel[15];
assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel[15];
 
 
// Slave 16 inputs
assign wbs16_adr_i = wbm_adr_o;
assign wbs16_dat_i = wbm_dat_o;
assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel[16];
assign wbs16_stb_i = wbm_stb_o & wb_slave_sel[16];
assign wbs16_we_i = wbm_we_o;
assign wbs16_cti_i = wbm_cti_o;
assign wbs16_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[16] = wbs16_dat_o;
assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel[16];
assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel[16];
assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel[16];
 
 
// Slave 17 inputs
assign wbs17_adr_i = wbm_adr_o;
assign wbs17_dat_i = wbm_dat_o;
assign wbs17_cyc_i = wbm_cyc_o & wb_slave_sel[17];
assign wbs17_stb_i = wbm_stb_o & wb_slave_sel[17];
assign wbs17_we_i = wbm_we_o;
assign wbs17_cti_i = wbm_cti_o;
assign wbs17_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[17] = wbs17_dat_o;
assign wbs_ack_o_mux_i[17] = wbs17_ack_o & wb_slave_sel[17];
assign wbs_err_o_mux_i[17] = wbs17_err_o & wb_slave_sel[17];
assign wbs_rty_o_mux_i[17] = wbs17_rty_o & wb_slave_sel[17];
// Slave 18 inputs
assign wbs18_adr_i = wbm_adr_o;
assign wbs18_dat_i = wbm_dat_o;
assign wbs18_cyc_i = wbm_cyc_o & wb_slave_sel[18];
assign wbs18_stb_i = wbm_stb_o & wb_slave_sel[18];
assign wbs18_we_i = wbm_we_o;
assign wbs18_cti_i = wbm_cti_o;
assign wbs18_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[18] = wbs18_dat_o;
assign wbs_ack_o_mux_i[18] = wbs18_ack_o & wb_slave_sel[18];
assign wbs_err_o_mux_i[18] = wbs18_err_o & wb_slave_sel[18];
assign wbs_rty_o_mux_i[18] = wbs18_rty_o & wb_slave_sel[18];
// Slave 19 inputs
assign wbs19_adr_i = wbm_adr_o;
assign wbs19_dat_i = wbm_dat_o;
assign wbs19_cyc_i = wbm_cyc_o & wb_slave_sel[19];
assign wbs19_stb_i = wbm_stb_o & wb_slave_sel[19];
assign wbs19_we_i = wbm_we_o;
assign wbs19_cti_i = wbm_cti_o;
assign wbs19_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[19] = wbs19_dat_o;
assign wbs_ack_o_mux_i[19] = wbs19_ack_o & wb_slave_sel[19];
assign wbs_err_o_mux_i[19] = wbs19_err_o & wb_slave_sel[19];
assign wbs_rty_o_mux_i[19] = wbs19_rty_o & wb_slave_sel[19];
 
*/
 
 
 
// Master out mux from slave in data
assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
/*
wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
wb_slave_sel[8] ? wbs_dat_o_mux_i[8] :
wb_slave_sel[9] ? wbs_dat_o_mux_i[9] :
wb_slave_sel[10] ? wbs_dat_o_mux_i[10] :
wb_slave_sel[11] ? wbs_dat_o_mux_i[11] :
wb_slave_sel[12] ? wbs_dat_o_mux_i[12] :
wb_slave_sel[13] ? wbs_dat_o_mux_i[13] :
wb_slave_sel[14] ? wbs_dat_o_mux_i[14] :
wb_slave_sel[15] ? wbs_dat_o_mux_i[15] :
wb_slave_sel[16] ? wbs_dat_o_mux_i[16] :
wb_slave_sel[17] ? wbs_dat_o_mux_i[17] :
wb_slave_sel[18] ? wbs_dat_o_mux_i[18] :
wb_slave_sel[19] ? wbs_dat_o_mux_i[19] :
*/
wbs_dat_o_mux_i[0];
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] /* |
wbs_ack_o_mux_i[1] |
wbs_ack_o_mux_i[2] |
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[4] |
wbs_ack_o_mux_i[5] |
wbs_ack_o_mux_i[6] |
wbs_ack_o_mux_i[7] |
wbs_ack_o_mux_i[8] |
wbs_ack_o_mux_i[9] |
wbs_ack_o_mux_i[10] |
wbs_ack_o_mux_i[11] |
wbs_ack_o_mux_i[12] |
wbs_ack_o_mux_i[13] |
wbs_ack_o_mux_i[14] |
wbs_ack_o_mux_i[15] |
wbs_ack_o_mux_i[16] |
wbs_ack_o_mux_i[17] |
wbs_ack_o_mux_i[18] |
wbs_ack_o_mux_i[19]
*/
;
 
assign wbm_err_i = wbs_err_o_mux_i[0] |/*
wbs_err_o_mux_i[1] |
wbs_err_o_mux_i[2] |
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[4] |
wbs_err_o_mux_i[5] |
wbs_err_o_mux_i[6] |
wbs_err_o_mux_i[7] |
wbs_err_o_mux_i[8] |
wbs_err_o_mux_i[9] |
wbs_err_o_mux_i[10] |
wbs_err_o_mux_i[11] |
wbs_err_o_mux_i[12] |
wbs_err_o_mux_i[13] |
wbs_err_o_mux_i[14] |
wbs_err_o_mux_i[15] |
wbs_err_o_mux_i[16] |
wbs_err_o_mux_i[17] |
wbs_err_o_mux_i[18] |
wbs_err_o_mux_i[19] |
*/
watchdog_err ;
 
assign wbm_rty_i = wbs_rty_o_mux_i[0] /*|
wbs_rty_o_mux_i[1] |
wbs_rty_o_mux_i[2] |
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[4] |
wbs_rty_o_mux_i[5] |
wbs_rty_o_mux_i[6] |
wbs_rty_o_mux_i[7] |
wbs_rty_o_mux_i[8] |
wbs_rty_o_mux_i[9] |
wbs_rty_o_mux_i[10] |
wbs_rty_o_mux_i[11] |
wbs_rty_o_mux_i[12] |
wbs_rty_o_mux_i[13] |
wbs_rty_o_mux_i[14] |
wbs_rty_o_mux_i[15] |
wbs_rty_o_mux_i[16] |
wbs_rty_o_mux_i[17] |
wbs_rty_o_mux_i[18] |
wbs_rty_o_mux_i[19]
*/
;
 
endmodule // arbiter_bytebus
/openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v
0,0 → 1,1261
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, burst-compatible ////
/// ////
/// Simple arbiter, multi-master, multi-slave with default slave ////
/// for chaining with peripheral arbiter ////
/// ////
/// Julius Baxter, julius@opencores.org ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
// 2 Masters, a few slaves
module arbiter_dbus
(
// or1200 data master
// Wishbone Master interface
wbm0_adr_o,
wbm0_dat_o,
wbm0_sel_o,
wbm0_we_o,
wbm0_cyc_o,
wbm0_stb_o,
wbm0_cti_o,
wbm0_bte_o,
wbm0_dat_i,
wbm0_ack_i,
wbm0_err_i,
wbm0_rty_i,
 
// or1200 debug master
// Wishbone Master interface
wbm1_adr_o,
wbm1_dat_o,
wbm1_sel_o,
wbm1_we_o,
wbm1_cyc_o,
wbm1_stb_o,
wbm1_cti_o,
wbm1_bte_o,
wbm1_dat_i,
wbm1_ack_i,
wbm1_err_i,
wbm1_rty_i,
 
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_sel_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
 
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_sel_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
 
/*
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
wbs2_dat_i,
wbs2_sel_i,
wbs2_we_i,
wbs2_cyc_i,
wbs2_stb_i,
wbs2_cti_i,
wbs2_bte_i,
wbs2_dat_o,
wbs2_ack_o,
wbs2_err_o,
wbs2_rty_o,
 
// Slave four
// Wishbone Slave interface
wbs3_adr_i,
wbs3_dat_i,
wbs3_sel_i,
wbs3_we_i,
wbs3_cyc_i,
wbs3_stb_i,
wbs3_cti_i,
wbs3_bte_i,
wbs3_dat_o,
wbs3_ack_o,
wbs3_err_o,
wbs3_rty_o,
 
// Slave five
// Wishbone Slave interface
wbs4_adr_i,
wbs4_dat_i,
wbs4_sel_i,
wbs4_we_i,
wbs4_cyc_i,
wbs4_stb_i,
wbs4_cti_i,
wbs4_bte_i,
wbs4_dat_o,
wbs4_ack_o,
wbs4_err_o,
wbs4_rty_o,
 
// Slave six
// Wishbone Slave interface
wbs5_adr_i,
wbs5_dat_i,
wbs5_sel_i,
wbs5_we_i,
wbs5_cyc_i,
wbs5_stb_i,
wbs5_cti_i,
wbs5_bte_i,
wbs5_dat_o,
wbs5_ack_o,
wbs5_err_o,
wbs5_rty_o,
 
// Slave seven
// Wishbone Slave interface
wbs6_adr_i,
wbs6_dat_i,
wbs6_sel_i,
wbs6_we_i,
wbs6_cyc_i,
wbs6_stb_i,
wbs6_cti_i,
wbs6_bte_i,
wbs6_dat_o,
wbs6_ack_o,
wbs6_err_o,
wbs6_rty_o,
 
// Slave eight
// Wishbone Slave interface
wbs7_adr_i,
wbs7_dat_i,
wbs7_sel_i,
wbs7_we_i,
wbs7_cyc_i,
wbs7_stb_i,
wbs7_cti_i,
wbs7_bte_i,
wbs7_dat_o,
wbs7_ack_o,
wbs7_err_o,
wbs7_rty_o,
 
// Slave nine
// Wishbone Slave interface
wbs8_adr_i,
wbs8_dat_i,
wbs8_sel_i,
wbs8_we_i,
wbs8_cyc_i,
wbs8_stb_i,
wbs8_cti_i,
wbs8_bte_i,
wbs8_dat_o,
wbs8_ack_o,
wbs8_err_o,
wbs8_rty_o,
 
// Slave ten
// Wishbone Slave interface
wbs9_adr_i,
wbs9_dat_i,
wbs9_sel_i,
wbs9_we_i,
wbs9_cyc_i,
wbs9_stb_i,
wbs9_cti_i,
wbs9_bte_i,
wbs9_dat_o,
wbs9_ack_o,
wbs9_err_o,
wbs9_rty_o,
 
// Slave eleven
// Wishbone Slave interface
wbs10_adr_i,
wbs10_dat_i,
wbs10_sel_i,
wbs10_we_i,
wbs10_cyc_i,
wbs10_stb_i,
wbs10_cti_i,
wbs10_bte_i,
wbs10_dat_o,
wbs10_ack_o,
wbs10_err_o,
wbs10_rty_o,
 
// Slave twelve
// Wishbone Slave interface
wbs11_adr_i,
wbs11_dat_i,
wbs11_sel_i,
wbs11_we_i,
wbs11_cyc_i,
wbs11_stb_i,
wbs11_cti_i,
wbs11_bte_i,
wbs11_dat_o,
wbs11_ack_o,
wbs11_err_o,
wbs11_rty_o,
 
// Slave thirteen
// Wishbone Slave interface
wbs12_adr_i,
wbs12_dat_i,
wbs12_sel_i,
wbs12_we_i,
wbs12_cyc_i,
wbs12_stb_i,
wbs12_cti_i,
wbs12_bte_i,
wbs12_dat_o,
wbs12_ack_o,
wbs12_err_o,
wbs12_rty_o,
 
// Slave fourteen
// Wishbone Slave interface
wbs13_adr_i,
wbs13_dat_i,
wbs13_sel_i,
wbs13_we_i,
wbs13_cyc_i,
wbs13_stb_i,
wbs13_cti_i,
wbs13_bte_i,
wbs13_dat_o,
wbs13_ack_o,
wbs13_err_o,
wbs13_rty_o,
 
// Slave fifteen
// Wishbone Slave interface
wbs14_adr_i,
wbs14_dat_i,
wbs14_sel_i,
wbs14_we_i,
wbs14_cyc_i,
wbs14_stb_i,
wbs14_cti_i,
wbs14_bte_i,
wbs14_dat_o,
wbs14_ack_o,
wbs14_err_o,
wbs14_rty_o,
 
// Slave sixteen
// Wishbone Slave interface
wbs15_adr_i,
wbs15_dat_i,
wbs15_sel_i,
wbs15_we_i,
wbs15_cyc_i,
wbs15_stb_i,
wbs15_cti_i,
wbs15_bte_i,
wbs15_dat_o,
wbs15_ack_o,
wbs15_err_o,
wbs15_rty_o,
 
// Slave seventeen
// Wishbone Slave interface
wbs16_adr_i,
wbs16_dat_i,
wbs16_sel_i,
wbs16_we_i,
wbs16_cyc_i,
wbs16_stb_i,
wbs16_cti_i,
wbs16_bte_i,
wbs16_dat_o,
wbs16_ack_o,
wbs16_err_o,
wbs16_rty_o,
*/
wb_clk,
wb_rst
);
 
parameter wb_dat_width = 32;
parameter wb_adr_width = 32;
 
parameter wb_addr_match_width = 8;
 
parameter wb_num_slaves = 2; // must also (un)comment things if changing
 
// Slave addresses - these should be defparam'd from top level
// Declare them as you need them
parameter slave0_adr = 0;
parameter slave1_adr = 0;
parameter slave2_adr = 0;
parameter slave3_adr = 0;
parameter slave4_adr = 0;
parameter slave5_adr = 0;
parameter slave6_adr = 0;
parameter slave7_adr = 0;
parameter slave8_adr = 0;
parameter slave9_adr = 0;
parameter slave10_adr = 0;
parameter slave11_adr = 0;
parameter slave12_adr = 0;
 
// Select for slave 0
`define WB_ARB_ADDR_MATCH_SEL_SLAVE0 wb_adr_width-1:wb_adr_width-4
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
 
input wb_clk;
input wb_rst;
// WB Master one
input [wb_adr_width-1:0] wbm0_adr_o;
input [wb_dat_width-1:0] wbm0_dat_o;
input [3:0] wbm0_sel_o;
input wbm0_we_o;
input wbm0_cyc_o;
input wbm0_stb_o;
input [2:0] wbm0_cti_o;
input [1:0] wbm0_bte_o;
output [wb_dat_width-1:0] wbm0_dat_i;
output wbm0_ack_i;
output wbm0_err_i;
output wbm0_rty_i;
input [wb_adr_width-1:0] wbm1_adr_o;
input [wb_dat_width-1:0] wbm1_dat_o;
input [3:0] wbm1_sel_o;
input wbm1_we_o;
input wbm1_cyc_o;
input wbm1_stb_o;
input [2:0] wbm1_cti_o;
input [1:0] wbm1_bte_o;
output [wb_dat_width-1:0] wbm1_dat_i;
output wbm1_ack_i;
output wbm1_err_i;
output wbm1_rty_i;
 
// Slave one
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs0_adr_i;
output [wb_dat_width-1:0] wbs0_dat_i;
output [3:0] wbs0_sel_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wb_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs1_adr_i;
output [wb_dat_width-1:0] wbs1_dat_i;
output [3:0] wbs1_sel_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wb_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs2_adr_i;
output [wb_dat_width-1:0] wbs2_dat_i;
output [3:0] wbs2_sel_i;
output wbs2_we_i;
output wbs2_cyc_i;
output wbs2_stb_i;
output [2:0] wbs2_cti_i;
output [1:0] wbs2_bte_i;
input [wb_dat_width-1:0] wbs2_dat_o;
input wbs2_ack_o;
input wbs2_err_o;
input wbs2_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs3_adr_i;
output [wb_dat_width-1:0] wbs3_dat_i;
output [3:0] wbs3_sel_i;
output wbs3_we_i;
output wbs3_cyc_i;
output wbs3_stb_i;
output [2:0] wbs3_cti_i;
output [1:0] wbs3_bte_i;
input [wb_dat_width-1:0] wbs3_dat_o;
input wbs3_ack_o;
input wbs3_err_o;
input wbs3_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs4_adr_i;
output [wb_dat_width-1:0] wbs4_dat_i;
output [3:0] wbs4_sel_i;
output wbs4_we_i;
output wbs4_cyc_i;
output wbs4_stb_i;
output [2:0] wbs4_cti_i;
output [1:0] wbs4_bte_i;
input [wb_dat_width-1:0] wbs4_dat_o;
input wbs4_ack_o;
input wbs4_err_o;
input wbs4_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs5_adr_i;
output [wb_dat_width-1:0] wbs5_dat_i;
output [3:0] wbs5_sel_i;
output wbs5_we_i;
output wbs5_cyc_i;
output wbs5_stb_i;
output [2:0] wbs5_cti_i;
output [1:0] wbs5_bte_i;
input [wb_dat_width-1:0] wbs5_dat_o;
input wbs5_ack_o;
input wbs5_err_o;
input wbs5_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs6_adr_i;
output [wb_dat_width-1:0] wbs6_dat_i;
output [3:0] wbs6_sel_i;
output wbs6_we_i;
output wbs6_cyc_i;
output wbs6_stb_i;
output [2:0] wbs6_cti_i;
output [1:0] wbs6_bte_i;
input [wb_dat_width-1:0] wbs6_dat_o;
input wbs6_ack_o;
input wbs6_err_o;
input wbs6_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs7_adr_i;
output [wb_dat_width-1:0] wbs7_dat_i;
output [3:0] wbs7_sel_i;
output wbs7_we_i;
output wbs7_cyc_i;
output wbs7_stb_i;
output [2:0] wbs7_cti_i;
output [1:0] wbs7_bte_i;
input [wb_dat_width-1:0] wbs7_dat_o;
input wbs7_ack_o;
input wbs7_err_o;
input wbs7_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs8_adr_i;
output [wb_dat_width-1:0] wbs8_dat_i;
output [3:0] wbs8_sel_i;
output wbs8_we_i;
output wbs8_cyc_i;
output wbs8_stb_i;
output [2:0] wbs8_cti_i;
output [1:0] wbs8_bte_i;
input [wb_dat_width-1:0] wbs8_dat_o;
input wbs8_ack_o;
input wbs8_err_o;
input wbs8_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs9_adr_i;
output [wb_dat_width-1:0] wbs9_dat_i;
output [3:0] wbs9_sel_i;
output wbs9_we_i;
output wbs9_cyc_i;
output wbs9_stb_i;
output [2:0] wbs9_cti_i;
output [1:0] wbs9_bte_i;
input [wb_dat_width-1:0] wbs9_dat_o;
input wbs9_ack_o;
input wbs9_err_o;
input wbs9_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs10_adr_i;
output [wb_dat_width-1:0] wbs10_dat_i;
output [3:0] wbs10_sel_i;
output wbs10_we_i;
output wbs10_cyc_i;
output wbs10_stb_i;
output [2:0] wbs10_cti_i;
output [1:0] wbs10_bte_i;
input [wb_dat_width-1:0] wbs10_dat_o;
input wbs10_ack_o;
input wbs10_err_o;
input wbs10_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs11_adr_i;
output [wb_dat_width-1:0] wbs11_dat_i;
output [3:0] wbs11_sel_i;
output wbs11_we_i;
output wbs11_cyc_i;
output wbs11_stb_i;
output [2:0] wbs11_cti_i;
output [1:0] wbs11_bte_i;
input [wb_dat_width-1:0] wbs11_dat_o;
input wbs11_ack_o;
input wbs11_err_o;
input wbs11_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs12_adr_i;
output [wb_dat_width-1:0] wbs12_dat_i;
output [3:0] wbs12_sel_i;
output wbs12_we_i;
output wbs12_cyc_i;
output wbs12_stb_i;
output [2:0] wbs12_cti_i;
output [1:0] wbs12_bte_i;
input [wb_dat_width-1:0] wbs12_dat_o;
input wbs12_ack_o;
input wbs12_err_o;
input wbs12_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs13_adr_i;
output [wb_dat_width-1:0] wbs13_dat_i;
output [3:0] wbs13_sel_i;
output wbs13_we_i;
output wbs13_cyc_i;
output wbs13_stb_i;
output [2:0] wbs13_cti_i;
output [1:0] wbs13_bte_i;
input [wb_dat_width-1:0] wbs13_dat_o;
input wbs13_ack_o;
input wbs13_err_o;
input wbs13_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs14_adr_i;
output [wb_dat_width-1:0] wbs14_dat_i;
output [3:0] wbs14_sel_i;
output wbs14_we_i;
output wbs14_cyc_i;
output wbs14_stb_i;
output [2:0] wbs14_cti_i;
output [1:0] wbs14_bte_i;
input [wb_dat_width-1:0] wbs14_dat_o;
input wbs14_ack_o;
input wbs14_err_o;
input wbs14_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs15_adr_i;
output [wb_dat_width-1:0] wbs15_dat_i;
output [3:0] wbs15_sel_i;
output wbs15_we_i;
output wbs15_cyc_i;
output wbs15_stb_i;
output [2:0] wbs15_cti_i;
output [1:0] wbs15_bte_i;
input [wb_dat_width-1:0] wbs15_dat_o;
input wbs15_ack_o;
input wbs15_err_o;
input wbs15_rty_o;
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs16_adr_i;
output [wb_dat_width-1:0] wbs16_dat_i;
output [3:0] wbs16_sel_i;
output wbs16_we_i;
output wbs16_cyc_i;
output wbs16_stb_i;
output [2:0] wbs16_cti_i;
output [1:0] wbs16_bte_i;
input [wb_dat_width-1:0] wbs16_dat_o;
input wbs16_ack_o;
input wbs16_err_o;
input wbs16_rty_o;
*/
 
reg watchdog_err;
`ifdef ARBITER_DBUS_REGISTERING
 
// Registering setup:
// Masters typically register their outputs, so do the master selection and
// muxing before registering in the arbiter. Keep the common parts outside
// for code brevity.
// Master ins -> |MUX> -> these wires
wire [wb_adr_width-1:0] wbm_adr_o_w;
wire [wb_dat_width-1:0] wbm_dat_o_w;
wire [3:0] wbm_sel_o_w;
wire wbm_we_o_w;
wire wbm_cyc_o_w;
wire wbm_stb_o_w;
wire [2:0] wbm_cti_o_w;
wire [1:0] wbm_bte_o_w;
// Slave ins -> |MUX> -> these wires
wire [wb_dat_width-1:0] wbm_dat_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
 
// Registers after masters input mux
reg [wb_adr_width-1:0] wbm_adr_o_r;
reg [wb_dat_width-1:0] wbm_dat_o_r;
reg [3:0] wbm_sel_o_r;
reg wbm_we_o_r;
reg wbm_cyc_o_r;
reg wbm_stb_o_r;
reg [2:0] wbm_cti_o_r;
reg [1:0] wbm_bte_o_r;
 
// Master input mux register wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wb_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
 
// Registers after slaves input mux
reg [wb_dat_width-1:0] wbm_dat_i_r;
reg wbm_ack_i_r;
reg wbm_err_i_r;
reg wbm_rty_i_r;
 
// Master select (MUX controls)
wire [1:0] master_sel;
// priority to wbm1, the debug master
assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o;
assign master_sel[1] = wbm1_cyc_o;
 
 
// Master input mux, priority to debug master
assign wbm_adr_o_w = master_sel[1] ? wbm1_adr_o :
wbm0_adr_o;
assign wbm_dat_o_w = master_sel[1] ? wbm1_dat_o :
wbm0_dat_o;
assign wbm_sel_o_w = master_sel[1] ? wbm1_sel_o :
wbm0_sel_o;
 
assign wbm_we_o_w = master_sel[1] ? wbm1_we_o :
wbm0_we_o;
assign wbm_cyc_o_w = master_sel[1] ? wbm1_cyc_o :
wbm0_cyc_o;
 
assign wbm_stb_o_w = master_sel[1] ? wbm1_stb_o :
wbm0_stb_o;
 
assign wbm_cti_o_w = master_sel[1] ? wbm1_cti_o :
wbm0_cti_o;
 
assign wbm_bte_o_w = master_sel[1] ? wbm1_bte_o :
wbm0_bte_o;
 
// Register muxed master signals
always @(posedge wb_clk)
begin
wbm_adr_o_r <= wbm_adr_o_w;
wbm_dat_o_r <= wbm_dat_o_w;
wbm_sel_o_r <= wbm_sel_o_w;
wbm_we_o_r <= wbm_we_o_w;
wbm_cyc_o_r <= wbm_cyc_o_w;
wbm_stb_o_r <= wbm_stb_o_w & !wbm_ack_i & !wbm_ack_i_r;
wbm_cti_o_r <= wbm_cti_o_w;
wbm_bte_o_r <= wbm_bte_o_w;
wbm_dat_i_r <= wbm_dat_i;
wbm_ack_i_r <= wbm_ack_i;
wbm_err_i_r <= wbm_err_i;
wbm_rty_i_r <= wbm_rty_i;
end // always @ (posedge wb_clk)
 
assign wbm_adr_o = wbm_adr_o_r;
assign wbm_dat_o = wbm_dat_o_r;
assign wbm_sel_o = wbm_sel_o_r;
assign wbm_we_o = wbm_we_o_r;
assign wbm_cyc_o = wbm_cyc_o_r;
assign wbm_stb_o = wbm_stb_o_r;
assign wbm_cti_o = wbm_cti_o_r;
assign wbm_bte_o = wbm_bte_o_r;
 
// Master input mux, priority to debug master
assign wbm0_dat_i = wbm_dat_i_r;
assign wbm0_ack_i = wbm_ack_i_r & master_sel[0];
assign wbm0_err_i = wbm_err_i_r & master_sel[0];
assign wbm0_rty_i = wbm_rty_i_r & master_sel[0];
assign wbm1_dat_i = wbm_dat_i_r;
assign wbm1_ack_i = wbm_ack_i_r & master_sel[1];
assign wbm1_err_i = wbm_err_i_r & master_sel[1];
assign wbm1_rty_i = wbm_rty_i_r & master_sel[1];
`else // !`ifdef ARBITER_DBUS_REGISTERING
 
// Master input mux output wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wb_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
// Master select
wire [1:0] master_sel;
// priority to wbm1, the debug master
assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o;
assign master_sel[1] = wbm1_cyc_o;
 
 
// Master input mux, priority to debug master
assign wbm_adr_o = master_sel[1] ? wbm1_adr_o :
wbm0_adr_o;
assign wbm_dat_o = master_sel[1] ? wbm1_dat_o :
wbm0_dat_o;
assign wbm_sel_o = master_sel[1] ? wbm1_sel_o :
wbm0_sel_o;
 
assign wbm_we_o = master_sel[1] ? wbm1_we_o :
wbm0_we_o;
assign wbm_cyc_o = master_sel[1] ? wbm1_cyc_o :
wbm0_cyc_o;
 
assign wbm_stb_o = master_sel[1] ? wbm1_stb_o :
wbm0_stb_o;
 
assign wbm_cti_o = master_sel[1] ? wbm1_cti_o :
wbm0_cti_o;
 
assign wbm_bte_o = master_sel[1] ? wbm1_bte_o :
wbm0_bte_o;
 
 
wire [wb_dat_width-1:0] wbm_dat_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
 
 
assign wbm0_dat_i = wbm_dat_i;
assign wbm0_ack_i = wbm_ack_i & master_sel[0];
assign wbm0_err_i = wbm_err_i & master_sel[0];
assign wbm0_rty_i = wbm_rty_i & master_sel[0];
assign wbm1_dat_i = wbm_dat_i;
assign wbm1_ack_i = wbm_ack_i & master_sel[1];
assign wbm1_err_i = wbm_err_i & master_sel[1];
assign wbm1_rty_i = wbm_rty_i & master_sel[1];
 
 
`endif // !`ifdef ARBITER_DBUS_REGISTERING
 
// Slave select wire
wire [wb_num_slaves-1:0] wb_slave_sel;
// Slave out mux in wires
wire [wb_dat_width-1:0] wbs_dat_o_mux_i [0:wb_num_slaves-1];
wire wbs_ack_o_mux_i [0:wb_num_slaves-1];
wire wbs_err_o_mux_i [0:wb_num_slaves-1];
wire wbs_rty_o_mux_i [0:wb_num_slaves-1];
 
//
// Slave selects
//
assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr | wbm_adr_o[31:28] == 4'hf; // Special case, point all reads to ROM address to here
// Auto select last slave when others are not selected
assign wb_slave_sel[1] = !(wb_slave_sel[0]);
 
/*
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr;
assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr;
assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr;
assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr;
assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr;
assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr;
assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr;
assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr;
*/
 
`ifdef ARBITER_DBUS_WATCHDOG
reg [`ARBITER_DBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
 
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
 
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
 
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
 
`else // !`ifdef ARBITER_DBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
`endif // !`ifdef ARBITER_DBUS_WATCHDOG
 
// Slave 0 inputs
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel[0];
assign wbs0_stb_i = wbm_stb_o & wb_slave_sel[0];
assign wbs0_we_i = wbm_we_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
 
 
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
assign wbs1_we_i = wbm_we_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
 
/*
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
assign wbs2_sel_i = wbm_sel_o;
assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
assign wbs2_we_i = wbm_we_o;
assign wbs2_cti_i = wbm_cti_o;
assign wbs2_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel[2];
assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel[2];
assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel[2];
 
 
// Slave 3 inputs
assign wbs3_adr_i = wbm_adr_o;
assign wbs3_dat_i = wbm_dat_o;
assign wbs3_sel_i = wbm_sel_o;
assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel[3];
assign wbs3_stb_i = wbm_stb_o & wb_slave_sel[3];
assign wbs3_we_i = wbm_we_o;
assign wbs3_cti_i = wbm_cti_o;
assign wbs3_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel[3];
assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel[3];
assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel[3];
 
// Slave 4 inputs
assign wbs4_adr_i = wbm_adr_o;
assign wbs4_dat_i = wbm_dat_o;
assign wbs4_sel_i = wbm_sel_o;
assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel[4];
assign wbs4_stb_i = wbm_stb_o & wb_slave_sel[4];
assign wbs4_we_i = wbm_we_o;
assign wbs4_cti_i = wbm_cti_o;
assign wbs4_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel[4];
assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel[4];
assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel[4];
 
 
// Slave 5 inputs
assign wbs5_adr_i = wbm_adr_o;
assign wbs5_dat_i = wbm_dat_o;
assign wbs5_sel_i = wbm_sel_o;
assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel[5];
assign wbs5_stb_i = wbm_stb_o & wb_slave_sel[5];
assign wbs5_we_i = wbm_we_o;
assign wbs5_cti_i = wbm_cti_o;
assign wbs5_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[5] = wbs5_dat_o;
assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel[5];
assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel[5];
assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel[5];
 
 
// Slave 6 inputs
assign wbs6_adr_i = wbm_adr_o;
assign wbs6_dat_i = wbm_dat_o;
assign wbs6_sel_i = wbm_sel_o;
assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel[6];
assign wbs6_stb_i = wbm_stb_o & wb_slave_sel[6];
assign wbs6_we_i = wbm_we_o;
assign wbs6_cti_i = wbm_cti_o;
assign wbs6_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[6] = wbs6_dat_o;
assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel[6];
assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel[6];
assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel[6];
 
 
// Slave 7 inputs
assign wbs7_adr_i = wbm_adr_o;
assign wbs7_dat_i = wbm_dat_o;
assign wbs7_sel_i = wbm_sel_o;
assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel[7];
assign wbs7_stb_i = wbm_stb_o & wb_slave_sel[7];
assign wbs7_we_i = wbm_we_o;
assign wbs7_cti_i = wbm_cti_o;
assign wbs7_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[7] = wbs7_dat_o;
assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel[7];
assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel[7];
assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel[7];
 
 
// Slave 8 inputs
assign wbs8_adr_i = wbm_adr_o;
assign wbs8_dat_i = wbm_dat_o;
assign wbs8_sel_i = wbm_sel_o;
assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel[8];
assign wbs8_stb_i = wbm_stb_o & wb_slave_sel[8];
assign wbs8_we_i = wbm_we_o;
assign wbs8_cti_i = wbm_cti_o;
assign wbs8_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[8] = wbs8_dat_o;
assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel[8];
assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel[8];
assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel[8];
 
 
// Slave 9 inputs
assign wbs9_adr_i = wbm_adr_o;
assign wbs9_dat_i = wbm_dat_o;
assign wbs9_sel_i = wbm_sel_o;
assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel[9];
assign wbs9_stb_i = wbm_stb_o & wb_slave_sel[9];
assign wbs9_we_i = wbm_we_o;
assign wbs9_cti_i = wbm_cti_o;
assign wbs9_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[9] = wbs9_dat_o;
assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel[9];
assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel[9];
assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel[9];
 
 
// Slave 10 inputs
assign wbs10_adr_i = wbm_adr_o;
assign wbs10_dat_i = wbm_dat_o;
assign wbs10_sel_i = wbm_sel_o;
assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel[10];
assign wbs10_stb_i = wbm_stb_o & wb_slave_sel[10];
assign wbs10_we_i = wbm_we_o;
assign wbs10_cti_i = wbm_cti_o;
assign wbs10_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[10] = wbs10_dat_o;
assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel[10];
assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel[10];
assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel[10];
 
// Slave 11 inputs
assign wbs11_adr_i = wbm_adr_o;
assign wbs11_dat_i = wbm_dat_o;
assign wbs11_sel_i = wbm_sel_o;
assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel[11];
assign wbs11_stb_i = wbm_stb_o & wb_slave_sel[11];
assign wbs11_we_i = wbm_we_o;
assign wbs11_cti_i = wbm_cti_o;
assign wbs11_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[11] = wbs11_dat_o;
assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel[11];
assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel[11];
assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel[11];
 
 
// Slave 12 inputs
assign wbs12_adr_i = wbm_adr_o;
assign wbs12_dat_i = wbm_dat_o;
assign wbs12_sel_i = wbm_sel_o;
assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel[12];
assign wbs12_stb_i = wbm_stb_o & wb_slave_sel[12];
assign wbs12_we_i = wbm_we_o;
assign wbs12_cti_i = wbm_cti_o;
assign wbs12_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[12] = wbs12_dat_o;
assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel[12];
assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel[12];
assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel[12];
 
 
// Slave 13 inputs
assign wbs13_adr_i = wbm_adr_o;
assign wbs13_dat_i = wbm_dat_o;
assign wbs13_sel_i = wbm_sel_o;
assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel[13];
assign wbs13_stb_i = wbm_stb_o & wb_slave_sel[13];
assign wbs13_we_i = wbm_we_o;
assign wbs13_cti_i = wbm_cti_o;
assign wbs13_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[13] = wbs13_dat_o;
assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel[13];
assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel[13];
assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel[13];
 
 
// Slave 14 inputs
assign wbs14_adr_i = wbm_adr_o;
assign wbs14_dat_i = wbm_dat_o;
assign wbs14_sel_i = wbm_sel_o;
assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel[14];
assign wbs14_stb_i = wbm_stb_o & wb_slave_sel[14];
assign wbs14_we_i = wbm_we_o;
assign wbs14_cti_i = wbm_cti_o;
assign wbs14_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[14] = wbs14_dat_o;
assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel[14];
assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel[14];
assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel[14];
 
 
// Slave 15 inputs
assign wbs15_adr_i = wbm_adr_o;
assign wbs15_dat_i = wbm_dat_o;
assign wbs15_sel_i = wbm_sel_o;
assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel[15];
assign wbs15_stb_i = wbm_stb_o & wb_slave_sel[15];
assign wbs15_we_i = wbm_we_o;
assign wbs15_cti_i = wbm_cti_o;
assign wbs15_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[15] = wbs15_dat_o;
assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel[15];
assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel[15];
assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel[15];
 
 
// Slave 16 inputs
assign wbs16_adr_i = wbm_adr_o;
assign wbs16_dat_i = wbm_dat_o;
assign wbs16_sel_i = wbm_sel_o;
assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel[16];
assign wbs16_stb_i = wbm_stb_o & wb_slave_sel[16];
assign wbs16_we_i = wbm_we_o;
assign wbs16_cti_i = wbm_cti_o;
assign wbs16_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[16] = wbs16_dat_o;
assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel[16];
assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel[16];
assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel[16];
 
*/
 
 
 
// Master out mux from slave in data
assign wbm_dat_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
/* wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
wb_slave_sel[8] ? wbs_dat_o_mux_i[8] :
wb_slave_sel[9] ? wbs_dat_o_mux_i[9] :
wb_slave_sel[10] ? wbs_dat_o_mux_i[10] :
wb_slave_sel[11] ? wbs_dat_o_mux_i[11] :
wb_slave_sel[12] ? wbs_dat_o_mux_i[12] :
wb_slave_sel[13] ? wbs_dat_o_mux_i[13] :
wb_slave_sel[14] ? wbs_dat_o_mux_i[14] :
wb_slave_sel[15] ? wbs_dat_o_mux_i[15] :
wb_slave_sel[16] ? wbs_dat_o_mux_i[16] :
*/
wbs_dat_o_mux_i[0];
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] |
wbs_ack_o_mux_i[1] /*|
wbs_ack_o_mux_i[2] |
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[4] |
wbs_ack_o_mux_i[5] |
wbs_ack_o_mux_i[6] |
wbs_ack_o_mux_i[7] |
wbs_ack_o_mux_i[8] |
wbs_ack_o_mux_i[9] |
wbs_ack_o_mux_i[10] |
wbs_ack_o_mux_i[11] |
wbs_ack_o_mux_i[12] |
wbs_ack_o_mux_i[13] |
wbs_ack_o_mux_i[14] |
wbs_ack_o_mux_i[15] |
wbs_ack_o_mux_i[16] */
;
 
assign wbm_err_i = wbs_err_o_mux_i[0] |
wbs_err_o_mux_i[1] |/*
wbs_err_o_mux_i[2] |
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[4] |
wbs_err_o_mux_i[5] |
wbs_err_o_mux_i[6] |
wbs_err_o_mux_i[7] |
wbs_err_o_mux_i[8] |
wbs_err_o_mux_i[9] |
wbs_err_o_mux_i[10] |
wbs_err_o_mux_i[11] |
wbs_err_o_mux_i[12] |
wbs_err_o_mux_i[13] |
wbs_err_o_mux_i[14] |
wbs_err_o_mux_i[15] |
wbs_err_o_mux_i[16] |*/
watchdog_err ;
 
 
assign wbm_rty_i = wbs_rty_o_mux_i[0] |
wbs_rty_o_mux_i[1]/*|
wbs_rty_o_mux_i[2] |
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[4] |
wbs_rty_o_mux_i[5] |
wbs_rty_o_mux_i[6] |
wbs_rty_o_mux_i[7] |
wbs_rty_o_mux_i[8] |
wbs_rty_o_mux_i[9] |
wbs_rty_o_mux_i[10] |
wbs_rty_o_mux_i[11] |
wbs_rty_o_mux_i[12] |
wbs_rty_o_mux_i[13] |
wbs_rty_o_mux_i[14] |
wbs_rty_o_mux_i[15] |
wbs_rty_o_mux_i[16]*/;
 
endmodule // arbiter_dbus
 
/openrisc/trunk/orpsocv2/rtl/verilog/arbiter/README
0,0 → 1,67
Wishbone arbiter RTL source
 
The current implementation of these arbiters for the design is a hard-coded
slightly configurable set up, rather than a configurable one-size-fits-all
approach. It is assumed a Harvard architecture is in use, and therefore there
are seperate busses for both instruction and data busses of the processor. The
data bus arbiter also has a peripheral, or byte (wide) bus, attached to it.
 
The busses have ports following the Wishbone B3 standard. They are a cross-bar
switch setup, ie only one master can be controlling the bus at a time. A simple
priority-based arbitration system is used, however this only really matters for
the data bus, which has multiple masters.
 
The addresses for each slave are configured through parameters. It is expected
the instantiation of the arbiter will define these parameters also.
 
The arbiters have the option of passing the signals through with or without any
sequential logic (registering) however they _DO NOT_ yet support registered
bursting (ie, where wb_cti indicates anything other than a Wishbone classic
cycle.) Do not enable registering, via the defines, and expect bursting to work!
 
There is an optional watchdog counter which will assert wb_err if a request is
not serviced within the counting period of the clock. The width of the timer
is defined.
 
The arbiters depend on the design's top level define file. The options for
registering and the watchdog timer should be set there.
 
arbiter_ibus.v:
This has only one master input and two slaves - a ROM and a main memory.
This is the simplest of the arbiters. It has 32-bit wide data ports.
 
 
arbiter_dbus.v:
This has two masters ports and several slave ports. It has 32-bit wide
data ports. It has a default slave it selects if none of the other
slaves are selected, allowing daisy-chaining of another arbiter onto it
(used for the peripheral byte-bus.)
 
Increasing or reducing the slaves here requires:
1. Altering the module() declaration, adding the required ports.
2. Altering the input/output declaration, adding the required ports.
3. Add/remove(comment-out) the appropriate line in the section under the
commend "Slave selects". Ensure to alter the final slave, or
"default" slave's select logic to include/exclude the slave being
added/removed.
4. Alter the inputs from the master going to the slave
5. Alter the inputs from the slave (wb_ack, wb_dat_i, etc.) going to the
master
6. When instantiating, be sure that the address for the new slave is
defined.
7. Be sure to update the appropriate parameters in design-params.v with
the correct total number of slaves, and the address of the new slave.
 
For most of this slave configuration change, it should be as easy as
following the example of the structure already in the file, and
potentially just moving the open block-comment marker "/*" past the
lines for the new slave.
 
arbiter_bytebus.v:
This is a single-master arbiter, connecting to multiple slaves. It has
single byte-wide data ports. The data port back to the master maps read
bytes to the correct position in a 32-bit wide word, consistent with a
big-endian representation of data. There is no default slave. The
procedure for adding new slaves is the same as for the main data-bus
arbiter, except for the default slave selection considerations.
/openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v
0,0 → 1,337
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, burst-compatible ////
/// ////
/// Simple arbiter, single master, dual slave, primarily for ////
/// processor instruction bus, providing access to one main ////
/// memory server and one ROM ////
/// ////
/// Julius Baxter, julius@opencores.org ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
// One master, 2 slaves.
module arbiter_ibus
(
// instruction bus in
// Wishbone Master interface
wbm_adr_o,
wbm_dat_o,
wbm_sel_o,
wbm_we_o,
wbm_cyc_o,
wbm_stb_o,
wbm_cti_o,
wbm_bte_o,
wbm_dat_i,
wbm_ack_i,
wbm_err_i,
wbm_rty_i,
 
 
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_sel_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
 
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_sel_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
 
wb_clk,
wb_rst
);
 
 
parameter wb_dat_width = 32;
parameter wb_adr_width = 32;
 
parameter wb_addr_match_width = 8;
 
parameter slave0_adr = 8'hf0; // FLASH ROM
parameter slave1_adr = 8'h00; // Main memory (SDRAM/FPGA SRAM)
 
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
input wb_clk;
input wb_rst;
 
// WB Master
input [wb_adr_width-1:0] wbm_adr_o;
input [wb_dat_width-1:0] wbm_dat_o;
input [3:0] wbm_sel_o;
input wbm_we_o;
input wbm_cyc_o;
input wbm_stb_o;
input [2:0] wbm_cti_o;
input [1:0] wbm_bte_o;
output [wb_dat_width-1:0] wbm_dat_i;
output wbm_ack_i;
output wbm_err_i;
output wbm_rty_i;
 
// WB Slave 0
output [wb_adr_width-1:0] wbs0_adr_i;
output [wb_dat_width-1:0] wbs0_dat_i;
output [3:0] wbs0_sel_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wb_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
 
// WB Slave 1
output [wb_adr_width-1:0] wbs1_adr_i;
output [wb_dat_width-1:0] wbs1_dat_i;
output [3:0] wbs1_sel_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wb_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
 
wire [1:0] slave_sel; // One bit per slave
 
reg watchdog_err;
`ifdef ARBITER_IBUS_WATCHDOG
reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
reg wbm_stb_edge_r, wbm_ack_i_r; // Reg these, better timing
 
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
 
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
 
always @(posedge wb_clk)
wbm_stb_edge_r <= wbm_stb_edge;
always @(posedge wb_clk)
wbm_ack_i_r <= wbm_ack_i;
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i_r) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge_r) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
 
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
`else // !`ifdef ARBITER_IBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
 
`endif // !`ifdef ARBITER_IBUS_WATCHDOG
 
`ifdef ARBITER_IBUS_REGISTERING
// Master input registers
reg [wb_adr_width-1:0] wbm_adr_o_r;
reg [wb_dat_width-1:0] wbm_dat_o_r;
reg [3:0] wbm_sel_o_r;
reg wbm_we_o_r;
reg wbm_cyc_o_r;
reg wbm_stb_o_r;
reg [2:0] wbm_cti_o_r;
reg [1:0] wbm_bte_o_r;
// Slave output registers
reg [wb_dat_width-1:0] wbs0_dat_o_r;
reg wbs0_ack_o_r;
reg wbs0_err_o_r;
reg wbs0_rty_o_r;
reg [wb_dat_width-1:0] wbs1_dat_o_r;
reg wbs1_ack_o_r;
reg wbs1_err_o_r;
reg wbs1_rty_o_r;
 
wire wbm_ack_i_pre_reg;
 
// Register master input signals
always @(posedge wb_clk)
begin
wbm_adr_o_r <= wbm_adr_o;
wbm_dat_o_r <= wbm_dat_o;
wbm_sel_o_r <= wbm_sel_o;
wbm_we_o_r <= wbm_we_o;
wbm_cyc_o_r <= wbm_cyc_o;
wbm_stb_o_r <= wbm_stb_o & !wbm_ack_i_pre_reg & !wbm_ack_i;//classic
wbm_cti_o_r <= wbm_cti_o;
wbm_bte_o_r <= wbm_bte_o;
 
// Slave signals
wbs0_dat_o_r <= wbs0_dat_o;
wbs0_ack_o_r <= wbs0_ack_o;
wbs0_err_o_r <= wbs0_err_o;
wbs0_rty_o_r <= wbs0_rty_o;
wbs1_dat_o_r <= wbs1_dat_o;
wbs1_ack_o_r <= wbs1_ack_o;
wbs1_err_o_r <= wbs1_err_o;
wbs1_rty_o_r <= wbs1_rty_o;
end // always @ (posedge wb_clk)
 
// Slave select
assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
slave0_adr;
 
assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
slave1_adr;
 
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o_r;
assign wbs0_dat_i = wbm_dat_o_r;
assign wbs0_we_i = wbm_dat_o_r;
assign wbs0_sel_i = wbm_sel_o_r;
assign wbs0_cti_i = wbm_cti_o_r;
assign wbs0_bte_i = wbm_bte_o_r;
assign wbs0_cyc_i = wbm_cyc_o_r & slave_sel[0];
assign wbs0_stb_i = wbm_stb_o_r & slave_sel[0];
 
assign wbs1_adr_i = wbm_adr_o_r;
assign wbs1_dat_i = wbm_dat_o_r;
assign wbs1_we_i = wbm_dat_o_r;
assign wbs1_sel_i = wbm_sel_o_r;
assign wbs1_cti_i = wbm_cti_o_r;
assign wbs1_bte_i = wbm_bte_o_r;
assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];
 
// Master out assigns
// Don't care about none selected...
assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r :
wbs0_dat_o_r ;
assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
(slave_sel[1] & wbs1_ack_o_r)
;
assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
(slave_sel[1] & wbs1_err_o_r) |
watchdog_err;
assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
(slave_sel[1] & wbs1_rty_o_r);
 
// Non-registered ack
assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
(slave_sel[1] & wbs1_ack_o);
`else // !`ifdef ARBITER_IBUS_REGISTERING
 
// Slave select
assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
slave0_adr;
 
assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
slave1_adr;
 
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_we_i = wbm_dat_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0];
assign wbs0_stb_i = wbm_stb_o & slave_sel[0];
 
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_we_i = wbm_dat_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
 
// Master out assigns
// Don't care about none selected...
assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
wbs0_dat_o ;
assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
(slave_sel[1] & wbs1_ack_o);
assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
(slave_sel[1] & wbs1_err_o) |
watchdog_err;
assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
(slave_sel[1] & wbs1_rty_o);
 
`endif
endmodule // arbiter_ibus
 
/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/README
0,0 → 1,5
JTAG TAP RTL
 
See the project's page on OpenCores for more information:
http://opencores.org/project,jtag
 
/openrisc/trunk/orpsocv2/rtl/verilog/rom/rom.v
0,0 → 1,145
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback (unneback@opencores.org) ////
//// - Julius Baxter (julius@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`define B3_BURST
`define NONBLOCK_ASSIGN <= #1
module rom
( wb_adr_i, wb_stb_i, wb_cyc_i, wb_cti_i, wb_bte_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter addr_width = 5;
input [(addr_width+2)-1:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
input wb_clk;
input wb_rst;
`ifdef B3_BURST
reg [addr_width-1:0] adr;
reg wb_stb_i_r;
wire new_access;
reg new_access_r;
wire burst;
reg burst_r;
wire new_burst;
`endif
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o `NONBLOCK_ASSIGN 32'h15000000;
else
`ifdef B3_BURST
case (adr)
`else
case (wb_adr_i)
`endif
`include "bootrom.v"
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat_o `NONBLOCK_ASSIGN 32'h00000000;
endcase // case (wb_adr_i)
`ifdef B3_BURST
always @(posedge wb_clk)
wb_stb_i_r `NONBLOCK_ASSIGN wb_stb_i;
 
assign new_access = (wb_stb_i & !wb_stb_i_r);
 
always @(posedge wb_clk)
new_access_r <= new_access;
always @(posedge wb_clk)
burst_r `NONBLOCK_ASSIGN burst;
assign new_burst = (burst & !burst_r);
always @(posedge wb_clk)
if (wb_rst)
adr `NONBLOCK_ASSIGN 0;
else if (new_access)
// New access, register address, ack a cycle later
adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
else if (burst)
begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr `NONBLOCK_ASSIGN adr + 1;
2'b01: adr[1:0] `NONBLOCK_ASSIGN adr[1:0] + 1;
2'b10: adr[2:0] `NONBLOCK_ASSIGN adr[2:0] + 1;
2'b11: adr[3:0] `NONBLOCK_ASSIGN adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o `NONBLOCK_ASSIGN 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o `NONBLOCK_ASSIGN 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
wb_ack_o `NONBLOCK_ASSIGN 1;
else
wb_ack_o `NONBLOCK_ASSIGN 0;
 
assign burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
`else // !`ifdef B3_BURST
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o `NONBLOCK_ASSIGN 1'b0;
else
wb_ack_o `NONBLOCK_ASSIGN wb_stb_i & wb_cyc_i & !wb_ack_o;
`endif // !`ifdef B3_BURST
endmodule
/openrisc/trunk/orpsocv2/rtl/verilog/rom/README
0,0 → 1,13
ROM module
 
This module will act as a read-only memory with a Wishbone interface. It relies
on a generated list of verilog assigns for each address requested. This included
verilog file is from the sw/bootrom path. Anything building the system should
also build this bootrom.v (requires compilation of assembly file with or32
toolchain and parsing with custom tool in sw/utils, all done automagically by
Makefile in sw/bootrom)
 
This ROM can support Wishbone B3 bursting, but obviously then requires more
logic. The `NONBLOCK_DEFINE is to accomodate those annoying coding
methodologies that do all sequential assigns with a #delay, like the or1200 was.
 
/openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v
0,0 → 1,116
//////////////////////////////////////////////////////////////////////
//
// clkgen
//
// Handles clock and reset generation for rest of design
//
//
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// A simple implementation for the main generic ORPSoC simulations
//
 
`include "timescale.v"
`include "orpsoc-defines.v"
 
module clkgen
(
// Main clocks in, depending on board
clk_pad_i,
// Wishbone clock and reset out
wb_clk_o,
wb_rst_o,
 
// JTAG clock
`ifdef JTAG_DEBUG
tck_pad_i,
dbg_tck_o,
`endif
 
// Asynchronous, active low reset in
rst_n_pad_i
);
 
input clk_pad_i;
output wb_rst_o;
output wb_clk_o;
 
`ifdef JTAG_DEBUG
input tck_pad_i;
output dbg_tck_o;
`endif
// Asynchronous, active low reset (pushbutton, typically)
input rst_n_pad_i;
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
 
// An input buffer is usually instantiated here
assign async_rst_n = rst_n_pad_i;
// Everyone likes active-high reset signals...
assign async_rst = ~async_rst_n;
`ifdef JTAG_DEBUG
assign dbg_tck_o = tck_pad_i;
`endif
 
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
 
// An active-low synchronous reset from ethernet PLL
wire sync_eth_rst_n;
 
// Here we just assign "board" clock (really test) to wishbone clock
assign wb_clk_o = clk_pad_i;
//
// Reset generation
//
//
 
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
endmodule // clkgen
/openrisc/trunk/orpsocv2/rtl/verilog/clkgen/README
0,0 → 1,20
Clock and reset generation module
 
This module should be used as the main reset and clock generation module. It
should have the asynchronous resets and unbuffered clock lines coming in, and
depending on defines in the main design file, generate the appropriate clocks
and clock-synchronous resets.
 
Currently Actel and Xilinx technlogies are supported. It is unclear if the way
it is handling clock-configurations depending on boards is ideal, potentially
it could become very cluttered if further board support is added and this would
need to be looked at.
 
The technology-dependent modules (PLLs, buffers) instantiated here should be
located under the backend/vendor/rtl paths.
 
As mentioned previously, it is unclear if this is the best way to manage the
task of clock and reset generation, particularly if further specialised clock
domains wish to be added, however there is some benefit in that it is all
managed in one place and with the strict rules that all clocks and resets come
to this module to be generated.
/openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/simple_spi.v
0,0 → 1,420
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores MC68HC11E based SPI interface ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: simple_spi_top.v,v 1.5 2004-02-28 15:59:50 rherveille Exp $
//
// $Date: 2004-02-28 15:59:50 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/08/01 11:41:54 rherveille
// Fixed some timing bugs.
//
// Revision 1.3 2003/01/09 16:47:59 rherveille
// Updated clkcnt size and decoding due to new SPR bit assignments.
//
// Revision 1.2 2003/01/07 13:29:52 rherveille
// Changed SPR bits coding.
//
// Revision 1.1.1.1 2002/12/22 16:07:15 rherveille
// Initial release
//
//
 
 
 
//
// Motorola MC68HC11E based SPI interface
//
// Currently only MASTER mode is supported
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`define SIMPLE_SPI_RST_SENS rst_i
 
//module simple_spi_top(
module simple_spi ( // renamed by Julius
// 8bit WISHBONE bus slave interface
clk_i, // clock
rst_i, // reset (asynchronous active low)
cyc_i, // cycle
stb_i, // strobe
adr_i, // address
we_i, // write enable
dat_i, // data input
dat_o, // data output
ack_o, // normal bus termination
inta_o, // interrupt output
sck_o, // serial clock output
ss_o, //slave select
mosi_o, // MasterOut SlaveIN
miso_i // MasterIn SlaveOut
);
parameter slave_select_width = 1;
input wire clk_i; // clock
input wire rst_i; // reset (asynchronous active low)
input wire cyc_i; // cycle
input wire stb_i; // strobe
input wire [2:0] adr_i; // address
input wire we_i; // write enable
input wire [7:0] dat_i; // data input
output reg [7:0] dat_o; // data output
output reg ack_o; // normal bus termination
output reg inta_o; // interrupt output
// SPI port
output reg sck_o; // serial clock output
output [slave_select_width-1:0] ss_o;
output wire mosi_o; // MasterOut SlaveIN
input wire miso_i; // MasterIn SlaveOut
 
reg [slave_select_width-1:0] ss_r;
//
// Module body
//
reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
reg [7:0] sper; // Serial Peripheral Extension register
reg [7:0] treg; // Transmit/Receive register
 
// fifo signals
wire [7:0] rfdout;
reg wfre, rfwe;
wire rfre, rffull, rfempty;
wire [7:0] wfdout;
wire wfwe, wffull, wfempty;
 
// misc signals
wire tirq; // transfer interrupt (selected number of transfers done)
wire wfov; // write fifo overrun (writing while fifo full)
reg [1:0] state; // statemachine state
reg [2:0] bcnt;
 
 
// Little startup init FSM and logic
// Does 4 accesses and waits to read out the data so the module is
// properly reset:
// Write 1: 0x3
// Write 2: 0x0
// Write 3: 0x0
// Write 4: 0x0
//
// This means anysoftware that wants to read can simply start pushing stuff
// into the fifo to kick it off
//
reg [3:0] startup_state = 0;
reg [3:0] startup_state_r = 0;
parameter startup_state_reset = 0; // Set to 0x10 to init to read on startup
parameter startup_spcr = 0;
parameter startup_slave_select = 0;
wire startup_rfre;
wire startup_busy;
assign startup_busy = |startup_state_r;
always @(posedge clk_i)
if (rst_i)
startup_state <= startup_state_reset;
else if ((startup_state == startup_state_r))// Whenever state is back to 0
startup_state <= {1'b0,startup_state[3:1]};
always @(posedge clk_i)
if (rst_i)
startup_state_r <= startup_state_reset;
else if (startup_rfre)
startup_state_r <= {1'b0,startup_state_r[3:1]};
wire [1:0] startup_state_wdf;
// This sets the 0x3 command, to read
assign startup_state_wdf = {startup_state[3], startup_state[3]};
 
wire startup_wfwe;
assign startup_wfwe = startup_busy & (startup_state == startup_state_r & !rst_i);
assign startup_rfre = (startup_busy) & !rfempty &
(startup_state != startup_state_r);
//
// Wishbone interface
wire wb_acc = cyc_i & stb_i & !startup_busy; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
 
// dat_i
always @(posedge clk_i)
if (`SIMPLE_SPI_RST_SENS)
begin
spcr <= 8'h10 | startup_spcr; // set master bit
sper <= 8'h00;
ss_r <= 0;
end
else if (wb_wr)
begin
if (adr_i == 3'b000)
spcr <= dat_i | 8'h10; // always set master bit
 
if (adr_i == 3'b011)
sper <= dat_i;
if (adr_i == 3'b100)
ss_r <= dat_i[slave_select_width-1:0];
end // if (wb_wr)
else if (startup_busy)
ss_r <= startup_slave_select;
// Slave select output
// SPI slave select is active low
assign ss_o = ~ss_r;
 
// write fifo
assign wfwe = wb_acc & (adr_i == 3'b010) & ack_o & we_i;
assign wfov = wfwe & wffull;
 
// dat_o
always @(posedge clk_i)
case(adr_i) // synopsys full_case parallel_case
3'b000: dat_o <= spcr;
3'b001: dat_o <= spsr;
3'b010: dat_o <= rfdout;
3'b011: dat_o <= sper;
3'b100: dat_o <= {{(8-slave_select_width){1'b0}},ss_r};
default:
dat_o <= 0;
endcase
 
// read fifo
assign rfre = wb_acc & (adr_i == 3'b010) & ack_o & ~we_i;
 
// ack_o
always @(posedge clk_i)
if (`SIMPLE_SPI_RST_SENS)
ack_o <= 1'b0;
else
ack_o <= wb_acc & !ack_o;
 
// decode Serial Peripheral Control Register
wire spie = spcr[7]; // Interrupt enable bit
wire spe = spcr[6]; // System Enable bit
wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
wire mstr = spcr[4]; // Master Mode Select Bit
wire cpol = spcr[3]; // Clock Polarity Bit
wire cpha = spcr[2]; // Clock Phase Bit
wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
 
// decode Serial Peripheral Extension Register
wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
wire [1:0] spre = sper[1:0]; // extended clock rate select
 
wire [3:0] espr = {spre, spr};
 
// generate status register
wire wr_spsr = wb_wr & (adr_i == 3'b001);
 
reg spif;
always @(posedge clk_i)
if (~spe | rst_i)
spif <= 1'b0;
else
spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]);
 
reg wcol;
always @(posedge clk_i)
if (~spe | rst_i)
wcol <= 1'b0;
else
wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]);
 
assign spsr[7] = spif;
assign spsr[6] = wcol;
assign spsr[5:4] = 2'b00;
assign spsr[3] = wffull;
assign spsr[2] = wfempty;
assign spsr[1] = rffull;
assign spsr[0] = rfempty;
 
// generate IRQ output (inta_o)
always @(posedge clk_i)
inta_o <= spif & spie;
 
 
wire [7:0] wfifo_dat_i;
assign wfifo_dat_i = startup_busy ? {6'd0, startup_state_wdf} : dat_i;
wire wfifo_wfwe;
assign wfifo_wfwe = wfwe | startup_wfwe;
 
wire rfifo_rfre = rfre | startup_rfre;
//
// hookup read/write buffer fifo
fifo4 #(8)
rfifo(
.clk ( clk_i ),
.rst ( ~rst_i ),
.clr ( ~spe ),
.din ( treg ),
.we ( rfwe ),
.dout ( rfdout ),
.re ( rfifo_rfre ),
.full ( rffull ),
.empty ( rfempty )
),
wfifo(
.clk ( clk_i ),
.rst ( ~rst_i ),
.clr ( ~spe ),
.din ( wfifo_dat_i ),
.we ( wfifo_wfwe ),
.dout ( wfdout ),
.re ( wfre ),
.full ( wffull ),
.empty ( wfempty )
);
 
//
// generate clk divider
reg [11:0] clkcnt;
always @(posedge clk_i)
if(spe & (|clkcnt & |state))
clkcnt <= clkcnt - 11'h1;
else
case (espr) // synopsys full_case parallel_case
4'b0000: clkcnt <= 12'h0; // 2 -- original M68HC11 coding
4'b0001: clkcnt <= 12'h1; // 4 -- original M68HC11 coding
4'b0010: clkcnt <= 12'h3; // 16 -- original M68HC11 coding
4'b0011: clkcnt <= 12'hf; // 32 -- original M68HC11 coding
4'b0100: clkcnt <= 12'h1f; // 8
4'b0101: clkcnt <= 12'h7; // 64
4'b0110: clkcnt <= 12'h3f; // 128
4'b0111: clkcnt <= 12'h7f; // 256
4'b1000: clkcnt <= 12'hff; // 512
4'b1001: clkcnt <= 12'h1ff; // 1024
4'b1010: clkcnt <= 12'h3ff; // 2048
4'b1011: clkcnt <= 12'h7ff; // 4096
endcase
 
// generate clock enable signal
wire ena = ~|clkcnt;
 
// transfer statemachine
always @(posedge clk_i)
if (~spe | rst_i)
begin
state <= 2'b00; // idle
bcnt <= 3'h0;
treg <= 8'h00;
wfre <= 1'b0;
rfwe <= 1'b0;
sck_o <= 1'b0;
end
else
begin
wfre <= 1'b0;
rfwe <= 1'b0;
 
case (state) //synopsys full_case parallel_case
2'b00: // idle state
begin
bcnt <= 3'h7; // set transfer counter
treg <= wfdout; // load transfer register
sck_o <= cpol; // set sck
 
if (~wfempty) begin
wfre <= 1'b1;
state <= 2'b01;
if (cpha) sck_o <= ~sck_o;
end
end
 
2'b01: // clock-phase2, next data
if (ena) begin
sck_o <= ~sck_o;
state <= 2'b11;
end
 
2'b11: // clock phase1
if (ena) begin
treg <= {treg[6:0], miso_i};
bcnt <= bcnt -3'h1;
 
if (~|bcnt) begin
state <= 2'b00;
sck_o <= cpol;
rfwe <= 1'b1;
end else begin
state <= 2'b01;
sck_o <= ~sck_o;
end
end
 
2'b10: state <= 2'b00;
endcase
end
 
assign mosi_o = treg[7];
 
 
// count number of transfers (for interrupt generation)
reg [1:0] tcnt; // transfer count
always @(posedge clk_i)
if (~spe)
tcnt <= icnt;
else if (rfwe) // rfwe gets asserted when all bits have been transfered
if (|tcnt)
tcnt <= tcnt - 2'h1;
else
tcnt <= icnt;
 
assign tirq = ~|tcnt & rfwe;
 
endmodule
 
/openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/fifo4.v
0,0 → 1,131
/////////////////////////////////////////////////////////////////////
//// ////
//// FIFO 4 entries deep ////
//// ////
//// Authors: Rudolf Usselmann, Richard Herveille ////
//// rudi@asics.ws richard@asics.ws ////
//// ////
//// ////
//// Download from: http://www.opencores.org/projects/sasc ////
//// http://www.opencores.org/projects/simple_spi ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
//// www.asics.ws ////
//// rudi@asics.ws, richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $
//
// $Date: 2002-12-22 16:07:14 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
// 4 entry deep fast fifo
module fifo4(clk, rst, clr, din, we, dout, re, full, empty);
 
parameter dw = 8;
 
input clk, rst;
input clr;
input [dw:1] din;
input we;
output [dw:1] dout;
input re;
output full, empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [dw:1] mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] wp_p2;
wire [1:0] rp_p1;
wire full, empty;
reg gb;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
if(!rst) wp <= 2'h0;
else
if(clr) wp <= 2'h0;
else
if(we) wp <= wp_p1;
 
assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;
 
always @(posedge clk or negedge rst)
if(!rst) rp <= 2'h0;
else
if(clr) rp <= 2'h0;
else
if(re) rp <= rp_p1;
 
assign rp_p1 = rp + 2'h1;
 
// Fifo Output
assign dout = mem[ rp ];
 
// Fifo Input
always @(posedge clk)
if(we) mem[ wp ] <= din;
 
// Status
assign empty = (wp == rp) & !gb;
assign full = (wp == rp) & gb;
 
// Guard Bit ...
always @(posedge clk)
if(!rst) gb <= 1'b0;
else
if(clr) gb <= 1'b0;
else
if((wp_p1 == rp) & we) gb <= 1'b1;
else
if(re) gb <= 1'b0;
 
endmodule
/openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/README
0,0 → 1,13
"Simple SPI" SPI controller RTL
 
http://opencores.org/project,simple_spi
 
The core has had a variable-width slave-select register and corresponding I/O
lines added.
 
There is also optional boot-up logic, that sends a series of bus-commands upon
reset, initialising, say a SPI flash chip, to read-state. This could potentially
save space in any bootloader code or FSM wishing to read from an SPI-bus chip
at boot time. Defparam the 'startup_state_reset' to 4'h10 to enable it, and
see the RTL for more details.
 
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/README
0,0 → 1,5
UART 16550 compatible (mostly) core RTL
 
http://opencores.org/project,uart16550
 
The core is configured to be in 8-bit mode in this project.
/openrisc/trunk/orpsocv2/sw/utils/bin2vlogarray.c
6,7 → 6,7
/******************************************************************************/
 
// Project Name : ORPSoC v2
// File Name : bin2c.c
// File Name : bin2vlogarray.c
// Prepared By :
// Project Start :
 
44,25 → 44,32
//
// Looks like this:
//
// 0 : wb_dat_o <= #1 32'h18000000;
// 1 : wb_dat_o <= #1 32'h18200000;
// 2 : wb_dat_o <= #1 32'h1880b000;
// 3 : wb_dat_o <= #1 32'ha8400051;
// 4 : wb_dat_o <= #1 32'hd8041000;
// 5 : wb_dat_o <= #1 32'h18c00000;
// 6 : wb_dat_o <= #1 32'h18e00000;
// 0 : wb_dat_o <= 32'h18000000;
// 1 : wb_dat_o <= 32'h18200000;
// 2 : wb_dat_o <= 32'h1880b000;
// 3 : wb_dat_o <= 32'ha8400051;
// 4 : wb_dat_o <= 32'hd8041000;
// 5 : wb_dat_o <= 32'h18c00000;
// 6 : wb_dat_o <= 32'h18e00000;
//
// etc...
//
//
// The generated file is pulled into the appropriate part of a verilog
// module and gets synthesized.
 
#include <stdio.h>
#include <stdint.h>
 
#define OUT_REG_STRING "wb_dat_o"
 
// OR1200 no longer has these #delays on synchronous assigns - so we don't need
// them here anymore either.
//#define ASSIGN_STRING "<= #1"
#define ASSIGN_STRING "<= "
 
#define SIZE_STRING "32'h"
 
// Concatenate the defines
#define BEFORE_STRING "%d : "OUT_REG_STRING" "ASSIGN_STRING" "SIZE_STRING
 
//#define BEFORE_STRING "%d : wb_dat_o <= 32'h"
/openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S
0,0 → 1,163
//////////////////////////////////////////////////////////////////////
/// ////
/// bootrom ////
/// ////
/// Assembly programs to be embedded inside system to aid boot ////
/// ////
/// Julius Baxter, julius@opencores.org ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// Defines for which bootrom app to use are in board.h - TODO: use the
// processed orspoc-defines.v file for this define. It makes more sense
// as this software ends up as gates.
#include "board.h"
 
#ifdef BOOTLOADER_SPI_FLASH
/* Assembly program to go into the boot ROM */
/* Currently just loads a program from SPI flash into RAM */
/* Assuming address at RAM_LOAD_BASE gets clobbered, we need
a byte writable address somewhere!*/
 
#define SPI_BASE SPI0_BASE
/* simple_spi driver */
#define SPI_SPCR 0x0
#define SPI_SPSR 0x1
#define SPI_SPDR 0x2
#define SPI_SPER 0x3
#define SPI_SPSS 0x4
 
#define SPI_SPCR_XFER_GO 0x51
#define SPI_SPSS_INIT 0x1
#define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/
#define RAM_LOAD_BASE SDRAM_BASE
#define RESET_ADDR 0x100
 
boot_init:
l.movhi r0, 0
l.movhi r1, RAM_LOAD_BASE
l.movhi r4, hi(SPI_BASE)
spi_init:
l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
l.sb SPI_SPCR(r4), r2
l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
l.ori r6, r0, SPI_SPSS_INIT
l.sb SPI_SPSS(r4), r6 /* Now put in appropriate slave select */
l.jal spi_xfer
l.ori r3, r0, 0x3 /* READ command opcode for SPI device */
l.jal spi_xfer
l.or r3, r0, r0
l.jal spi_xfer
l.or r3, r0, r0
l.jal spi_xfer
l.or r3, r0, r0
l.movhi r6, 0
l.movhi r7, 0xffff
 
copy:
l.jal spi_xfer /* Read a byte into r3 */
l.add r8, r1, r6 /* Calculate store address */
l.sb 0(r8), r3 /* Write byte to memory */
l.addi r6, r6, 1 /* Increment counter */
l.sfeqi r6, 0x4 /* Is this the first word */
l.bf store_sizeword /* put sizeword in the register */
l.sfeq r6, r7 /* Check if we've finished loading the words */
l.bnf copy /* Continue copying if not last word */
l.nop
 
goto_reset:
l.ori r1, r1, RESET_ADDR
l.jr r1
l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
store_sizeword:
l.j copy
l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
spi_xfer:
l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */
l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
spi_xfer_poll:
l.andi r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */
l.sfeqi r3, SPI_SPSR_RX_CHECK /* is bit set? ... */
l.bf spi_xfer_poll /* ... if so, rxfifo empty, keep polling */
l.lbz r3, SPI_SPSR(r4) /* Read SPSR */
l.jr r9
l.lbz r3, SPI_SPDR(r4) /* Get data byte */
 
 
#endif
 
#ifdef BOOTLOADER_GOTO_RESET
/* Jump to reset vector in the SDRAM */
l.movhi r0, 0
l.movhi r4, SDRAM_BASE
l.ori r4, r4, 0x100
l.jr r4
l.nop
#endif
 
#ifdef BOOTLOADER_LOOP_AT_ZERO
 
/* Don't load app via SPI, instead just put an infinite loop into bottom
of memory and jump there.
*/
l.movhi r0, 0
l.movhi r4, SDRAM_BASE
l.sw 0x0(r4), r0
l.movhi r5, hi(0x15000001) /* A l.nop 1 so sim exits if this enabled */
l.ori r5, r5, lo(0x15000001)
l.sw 0x4(r4), r5
l.sw 0x8(r4), r5
l.sw 0xc(r4), r5
l.jr r4
l.nop
 
 
#endif
 
#ifdef BOOTLOADER_LOOP_IN_ROM
 
/* Don't load app via SPI, instead just put an infinite loop into bottom
of memory and jump there.
*/
l.movhi r0, 0
l.nop 0x1
l.j 0
l.nop
l.nop
 
 
#endif
/openrisc/trunk/orpsocv2/sw/bootrom/Makefile
0,0 → 1,22
# Makefile for bootROM Verilog
 
include ../Makefile.inc
 
 
all: bootrom.v
 
%.v: %.bin ../utils/bin2vlogarray
$(Q)../utils/bin2vlogarray < $< > $@
 
%.dis: %.o
$(Q)$(OR32_OBJDUMP) -d $< > $@
 
%.bin: %.o
$(Q)$(OR32_OBJCOPY) -O binary $< $@
 
../utils/bin2vlogarray:
$(Q)$(MAKE) -C ../utils bin2vlogarray
 
clean:
$(Q)rm -f *.o *.bin *.hex *.in *.dis *.v
 
/openrisc/trunk/orpsocv2/sw/include/or1200-defines.h File deleted
/openrisc/trunk/orpsocv2/sw/include/simple-spi.h File deleted
/openrisc/trunk/orpsocv2/sw/include/eth-phy-mii.h File deleted
/openrisc/trunk/orpsocv2/sw/include/open-eth.h File deleted
/openrisc/trunk/orpsocv2/sw/include/sdram.h File deleted
/openrisc/trunk/orpsocv2/sw/include/board.h
2,40 → 2,16
#define _BOARD_H_
 
#define IN_CLK 50000000 // Hz
//#define IN_CLK 32000000 // Hz
//#define IN_CLK 30000000 // HZ
//#define IN_CLK 25000000 // HZ
//#define IN_CLK 24000000 // HZ
//#define IN_CLK 20000000 // HZ
//#define IN_CLK 18000000 // HZ
//#define IN_CLK 16000000 // HZ
 
//
// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
//
#define SDRAM_BASE 0x0
//#define MT48LC32M16A2 // 64MB SDRAM part
#define MT48LC16M16A2 // 32MB SDRAM part
//#define MT48LC4M16A2 // 8MB SDRAM part
#define RAM_BASE 0x00000000
 
#define UART0_BASE 0x90000000
#define UART0_IRQ 2
#define UART0_BAUD_RATE 115200
 
#define SPI0_BASE 0xb0000000
#define SPI0_IRQ 6
 
#define ETH0_BASE 0x92000000
#define ETH0_IRQ 4
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
#define ETH_MACADDR3 0x56
#define ETH_MACADDR4 0x78
#define ETH_MACADDR5 0x9a
 
 
//
// OR1200 tick timer period define
//
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S
43,7 → 43,7
 
#include "spr-defs.h"
#include "board.h"
#define RAM_START SDRAM_BASE
#define RAM_START RAM_BASE
/* Within the test we'll use following global variables:
/openrisc/trunk/orpsocv2/sw/Makefile.inc
67,9 → 67,9
OR1200_VERILOG_DEFINES=../../rtl/verilog/include/or1200_defines.v
OR1200_PROCESSED_VERILOG_DEFINES=../include/or1200-defines.h
 
#PROCESSED_DEFINES=$(DESIGN_PROCESSED_VERILOG_DEFINES) $(OR1200_PROCESSED_VERILOG_DEFINES)
PROCESSED_DEFINES= $(OR1200_PROCESSED_VERILOG_DEFINES)
PROCESSED_DEFINES=$(DESIGN_PROCESSED_VERILOG_DEFINES) $(OR1200_PROCESSED_VERILOG_DEFINES)
 
 
ELF_DEPENDS+=$(VECTORS_OBJ) $(PROCESSED_DEFINES) $(SUPPORT_FILES)
 
# Set V=1 when calling make to enable verbose output
/openrisc/trunk/orpsocv2/sw/support/simple-spi.c File deleted
/openrisc/trunk/orpsocv2/sw/support/Makefile
2,8 → 2,9
 
all: $(DESIGN_NAME)_support.a
 
SUPPORT_MODULES=exceptions int or32-utils simple-spi \
SUPPORT_MODULES=exceptions int or32-utils \
uart printf or1200-mmu
 
SUPPORT_OBJS=$(shell for mod in $(SUPPORT_MODULES); do echo "$$mod".o; done)
 
$(DESIGN_NAME)_support.a: $(SUPPORT_OBJS)

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