URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 369 to Rev 370
- ↔ Reverse comparison
Rev 369 → Rev 370
/trunk/or1200/rtl/verilog/sprs.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.10 2001/11/12 01:45:41 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
80,7 → 83,7
flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op, |
epcr, eear, esr, except_start, except_started, |
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr, |
spr_dat_cfgr, spr_dat_rf, spr_dat_pc, |
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, |
|
// From/to other RISC units |
spr_dat_pic, spr_dat_tt, spr_dat_pm, |
124,7 → 127,8
output [`SR_WIDTH-1:0] sr; // SR |
input [31:0] spr_dat_cfgr; // Data from CFGR |
input [31:0] spr_dat_rf; // Data from RF |
input [31:0] spr_dat_pc; // Data from PC |
input [31:0] spr_dat_npc; // Data from NPC |
input [31:0] spr_dat_ppc; // Data from PPC |
|
// |
// To/from other RISC units |
158,7 → 162,8
wire sr_we; // Write enable SR |
wire cfgr_sel; // Select for cfg regs |
wire rf_sel; // Select for RF |
wire pc_sel; // Select for PC |
wire npc_sel; // Select for NPC |
wire ppc_sel; // Select for PPC |
wire sr_sel; // Select for SR |
wire epcr_sel; // Select for EPCR0 |
wire eear_sel; // Select for EEAR0 |
254,7 → 259,8
// |
assign cfgr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:4] == `SPR_CFGR)); |
assign rf_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:5] == `SPR_RF)); |
assign pc_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_PC)); |
assign npc_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_NPC)); |
assign ppc_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_PPC)); |
assign sr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_SR)); |
assign epcr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EPCR)); |
assign eear_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EEAR)); |
264,7 → 270,7
// Write enables for system SPRs |
// |
assign sr_we = (write_spr && sr_sel) | (branch_op == `BRANCHOP_RFE); |
assign pc_we = (write_spr && pc_sel); |
assign pc_we = (write_spr && (npc_sel | ppc_sel)); |
assign epcr_we = (write_spr && epcr_sel); |
assign eear_we = (write_spr && eear_sel); |
assign esr_we = (write_spr && esr_sel); |
274,7 → 280,8
// |
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) | |
(spr_dat_rf & {32{read_spr & rf_sel}}) | |
(spr_dat_pc & {32{read_spr & pc_sel}}) | |
(spr_dat_npc & {32{read_spr & npc_sel}}) | |
(spr_dat_ppc & {32{read_spr & ppc_sel}}) | |
({{32-`SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) | |
(epcr & {32{read_spr & epcr_sel}}) | |
(eear & {32{read_spr & eear_sel}}) | |
/trunk/or1200/rtl/verilog/defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.17 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.16 2001/11/20 21:30:38 lampret |
// Added OR1200_REGISTERED_INPUTS. |
// |
128,12 → 131,12
// |
// Register OR1200 outputs |
// |
//`define OR1200_REGISTERED_OUTPUTS |
// `define OR1200_REGISTERED_OUTPUTS |
|
// |
// Register OR1200 inputs |
// |
//`define OR1200_REGISTERED_INPUTS |
// `define OR1200_REGISTERED_INPUTS |
|
// |
// Implement rotate in the ALU |
336,8 → 339,9
|
`define SPR_CFGR 7'd0 |
`define SPR_RF 6'd32 // 1024 >> 5 |
`define SPR_PC 11'd16 |
`define SPR_NPC 11'd16 |
`define SPR_SR 11'd17 |
`define SPR_PPC 11'd18 |
`define SPR_EPCR 11'd32 |
`define SPR_EEAR 11'd48 |
`define SPR_ESR 11'd64 |
/trunk/or1200/rtl/verilog/cpu.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.17 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.16 2001/11/20 00:57:22 lampret |
// Fixed width of du_except. |
// |
254,7 → 257,6
wire [`SR_WIDTH-1:0] sr; |
wire except_start; |
wire except_started; |
wire [31:0] wb_pc; |
wire [31:0] wb_insn; |
wire [15:0] spr_addrimm; |
wire sig_syscall; |
261,7 → 263,8
wire sig_trap; |
wire [31:0] spr_dat_cfgr; |
wire [31:0] spr_dat_rf; |
wire [31:0] spr_dat_pc; |
wire [31:0] spr_dat_npc; |
wire [31:0] spr_dat_ppc; |
wire force_dslot_fetch; |
wire if_stall; |
wire id_macrc_op; |
333,8 → 336,8
.except_start(except_start), |
.except_started(except_started), |
.except_stop(except_stop), |
.wb_pc(wb_pc), |
.ex_pc(spr_dat_pc), |
.wb_pc(spr_dat_ppc), |
.ex_pc(spr_dat_npc), |
|
.datain(operand_b), |
.du_dsr(du_dsr), |
539,7 → 542,8
.spr_dat_pm(spr_dat_pm), |
.spr_dat_cfgr(spr_dat_cfgr), |
.spr_dat_rf(spr_dat_rf), |
.spr_dat_pc(spr_dat_pc), |
.spr_dat_npc(spr_dat_npc), |
.spr_dat_ppc(spr_dat_ppc), |
.spr_dat_dmmu(spr_dat_dmmu), |
.spr_dat_immu(spr_dat_immu), |
.spr_dat_du(spr_dat_du), |
/trunk/or1200/rtl/verilog/generic_spram_512x20.v
182,11 → 182,7
// |
// Virtual Silicon Single-Port Synchronous SRAM |
// |
`ifdef UNUSED |
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp( |
`else |
virtualsilicon_ssp virtualsilicon_ssp( |
`endif |
.CK(clk), |
.ADR(addr), |
.DI(di), |