OpenCores
URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 37 to Rev 38
    ↔ Reverse comparison
  •

Rev 37 → Rev 38

/trunk/design/components.vhd
18,7 → 18,7
--
------------------------------------------------------------------------------
--
-- $Id: components.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
-- $Id: components.vhd,v 1.2 2008-11-07 04:54:32 jwdonal Exp $
--
-- Description:
-- This is a package that lists all of the components used in the design.
74,12 → 74,12
COMPONENT dcm_sys_to_lcd
PORT (
RST_IN,
CLKIN_IN : IN STD_LOGIC;
CLKIN_IN : IN std_logic;
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLKDV_OUT,
CLKFX_OUT : OUT STD_LOGIC
CLKFX_OUT : OUT std_logic
);
END COMPONENT dcm_sys_to_lcd;
 
119,7 → 119,7
--Video Controller
C_RL_STATUS,
C_UD_STATUS,
C_VQ_STATUS : STD_LOGIC;
C_VQ_STATUS : std_logic;
--VSYNCx Controller (pass thru)
C_VSYNC_TV,
142,11 → 142,11
PORT (
RSTx,
CLK_LCD : IN STD_LOGIC;
CLK_LCD : IN std_logic;
LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
LINE_NUM : OUT std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
HSYNCx,
VSYNCx,
153,7 → 153,7
ENAB,
RL,
UD,
VQ : OUT STD_LOGIC
VQ : OUT std_logic
);
END COMPONENT video_controller;
169,9 → 169,9
);
PORT (
RSTx,
CLK_LCD : IN STD_LOGIC;
CLK_LCD : IN std_logic;
HSYNCx : OUT STD_LOGIC
HSYNCx : OUT std_logic
);
END COMPONENT hsyncx_control;
 
189,11 → 189,11
PORT (
RSTx,
CLK_LCD,
HSYNCx : IN STD_LOGIC;
HSYNCx : IN std_logic;
LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
LINE_NUM : OUT std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
VSYNCx : OUT STD_LOGIC
VSYNCx : OUT std_logic
);
END COMPONENT vsyncx_control;
 
212,11 → 212,11
);
PORT (
RSTx,
CLK_LCD : IN STD_LOGIC;
CLK_LCD : IN std_logic;
CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : IN std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
ENAB : OUT STD_LOGIC
ENAB : OUT std_logic
);
END COMPONENT enab_control;
 
242,15 → 242,15
);
PORT (
RSTx,
CLK_LCD : IN STD_LOGIC;
CLK_LCD : IN std_logic;
LINE_NUM : IN STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
LINE_NUM : IN std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : IN std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
R,
G,
B : OUT STD_LOGIC_VECTOR(C_BIT_DEPTH/3-1 downto 0)
B : OUT std_logic_VECTOR(C_BIT_DEPTH/3-1 downto 0)
);
END COMPONENT image_gen_bram;
 
267,10 → 267,9
--image in each row would be "smeared" across the remaining pixels in the row!
COMPONENT image_gen_bram_red
PORT (
CLK,
SINIT : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(17-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(6-1 downto 0)
clka : IN std_logic;
addra : IN std_logic_VECTOR(17-1 downto 0);
douta : OUT std_logic_VECTOR(6-1 downto 0)
);
END COMPONENT;
ATTRIBUTE BOX_TYPE of image_gen_bram_red: component is "USER_BLACK_BOX";
277,10 → 276,9
COMPONENT image_gen_bram_green
PORT (
CLK,
SINIT : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(17-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(6-1 downto 0)
clka : IN std_logic;
addra : IN std_logic_VECTOR(17-1 downto 0);
douta : OUT std_logic_VECTOR(6-1 downto 0)
);
END COMPONENT;
ATTRIBUTE BOX_TYPE of image_gen_bram_green: component is "USER_BLACK_BOX";
287,10 → 285,9
COMPONENT image_gen_bram_blue
PORT (
CLK,
SINIT : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(17-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(6-1 downto 0)
clka : IN std_logic;
addra : IN std_logic_VECTOR(17-1 downto 0);
douta : OUT std_logic_VECTOR(6-1 downto 0)
);
END COMPONENT;
ATTRIBUTE BOX_TYPE of image_gen_bram_blue: component is "USER_BLACK_BOX";
/trunk/design/image_gen_bram.vhd
18,7 → 18,7
--
------------------------------------------------------------------------------
--
-- $Id: image_gen_bram.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
-- $Id: image_gen_bram.vhd,v 1.2 2008-11-07 04:54:32 jwdonal Exp $
--
-- Description: This file controls the BRAM components for each color.
--
126,32 → 126,29
--three components are initialized with 3 different COE files!
image_RED_data : image_gen_bram_red
port map (
CLK => CLK_LCD,
SINIT => SINIT_wire,
ADDR => ADDR_wire,
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
DOUT => R
douta => R
);
image_GREEN_data : image_gen_bram_green
port map (
CLK => CLK_LCD,
SINIT => SINIT_wire,
ADDR => ADDR_wire,
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
DOUT => G
douta => G
);
image_BLUE_data : image_gen_bram_blue
port map (
CLK => CLK_LCD,
SINIT => SINIT_wire,
ADDR => ADDR_wire,
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
DOUT => B
douta => B
);
 
 
162,7 → 159,8
-- the Xilinx core customization. The SINIT signal is enabled
-- b/w every line and b/w every new frame. This value is recommended
-- to be zero to conserver power but it doesn't really matter what
-- it is.
-- it is. In this design it is not connected but feel free to connect
-- it up yourself - everything should work exactly the same.
--
-- Inputs:
-- RSTx
/trunk/implement/results/lq057q3dc02_top_map.twr
36,8 → 36,8
NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%; multiplied by
16.00 and duty cycle corrected to 160 nS HIGH 80 nS
 
3903 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 6.871ns.
3691 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.746ns.
--------------------------------------------------------------------------------
 
================================================================================
59,7 → 59,7
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_100M_PAD | 6.871| | | |
CLK_100M_PAD | 5.746| | | |
---------------+---------+---------+---------+---------+
 
 
68,13 → 68,13
 
Timing errors: 0 Score: 0
 
Constraints cover 3903 paths, 0 nets, and 2359 connections
Constraints cover 3691 paths, 0 nets, and 1952 connections
 
Design statistics:
Minimum period: 6.871ns (Maximum frequency: 145.539MHz)
Minimum period: 5.746ns (Maximum frequency: 174.034MHz)
 
 
Analysis completed Thu Nov 06 13:56:36 2008
Analysis completed Thu Nov 06 18:46:07 2008
--------------------------------------------------------------------------------
 
Trace Settings:
/trunk/implement/results/lq057q3dc02_top_part.srp
47,30 → 47,30
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/components.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/components.vhd" in Library work_vhsic.
Package <components> compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/hsyncx_control.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/hsyncx_control.vhd" in Library work_vhsic.
Entity <hsyncx_control> compiled.
Entity <hsyncx_control> (Architecture <hsyncx_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/vsyncx_control.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/vsyncx_control.vhd" in Library work_vhsic.
Entity <vsyncx_control> compiled.
Entity <vsyncx_control> (Architecture <vsyncx_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/clk_lcd_cyc_cntr.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/clk_lcd_cyc_cntr.vhd" in Library work_vhsic.
Entity <clk_lcd_cyc_cntr> compiled.
Entity <clk_lcd_cyc_cntr> (Architecture <clk_lcd_cyc_cntr_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/enab_control.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/enab_control.vhd" in Library work_vhsic.
Entity <enab_control> compiled.
Entity <enab_control> (Architecture <enab_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/dcm_sys_to_lcd.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/dcm_sys_to_lcd.vhd" in Library work_vhsic.
Entity <dcm_sys_to_lcd> compiled.
Entity <dcm_sys_to_lcd> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/video_controller.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/video_controller.vhd" in Library work_vhsic.
Entity <video_controller> compiled.
Entity <video_controller> (Architecture <video_controller_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/image_gen_bram.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/image_gen_bram.vhd" in Library work_vhsic.
Entity <image_gen_bram> compiled.
Entity <image_gen_bram> (Architecture <image_gen_bram_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" in Library work_vhsic.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" in Library work_vhsic.
Entity <lq057q3dc02_top> compiled.
Entity <lq057q3dc02_top> (Architecture <lq057q3dc02_top_arch>) compiled.
 
169,9 → 169,9
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
C_VSYNC_TVS = 7
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLK0_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKFX_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLK0_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKFX_OUT' of component 'dcm_sys_to_lcd'.
Entity <lq057q3dc02_top> analyzed. Unit <lq057q3dc02_top> generated.
 
Analyzing Entity <dcm_sys_to_lcd> in library <work_vhsic> (Architecture <BEHAVIORAL>).
258,7 → 258,7
Performing bidirectional port resolution...
 
Synthesizing Unit <hsyncx_control>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/hsyncx_control.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/hsyncx_control.vhd".
Found 1-bit register for signal <HSYNCx>.
Found 10-bit comparator less for signal <HSYNCx$cmp_lt0000> created at line 136.
Found 9-bit up counter for signal <num_hsyncx_clks_reg>.
270,7 → 270,7
 
 
Synthesizing Unit <vsyncx_control>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/vsyncx_control.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/vsyncx_control.vhd".
Found finite state machine <FSM_0> for signal <Line_Cntr_cs>.
-----------------------------------------------------------------------
| States | 4 |
297,7 → 297,7
 
 
Synthesizing Unit <clk_lcd_cyc_cntr>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/clk_lcd_cyc_cntr.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/clk_lcd_cyc_cntr.vhd".
Found finite state machine <FSM_1> for signal <CLK_Cntr_cs>.
-----------------------------------------------------------------------
| States | 5 |
322,7 → 322,7
 
 
Synthesizing Unit <enab_control>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/enab_control.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/enab_control.vhd".
Found 1-bit register for signal <ENAB>.
Found 10-bit comparator greatequal for signal <ENAB$cmp_ge0000> created at line 131.
Found 10-bit comparator less for signal <ENAB$cmp_lt0000> created at line 131.
333,34 → 333,31
 
 
Synthesizing Unit <dcm_sys_to_lcd>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/dcm_sys_to_lcd.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/dcm_sys_to_lcd.vhd".
Unit <dcm_sys_to_lcd> synthesized.
 
 
Synthesizing Unit <video_controller>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/video_controller.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/video_controller.vhd".
Unit <video_controller> synthesized.
 
 
Synthesizing Unit <image_gen_bram>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/image_gen_bram.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/image_gen_bram.vhd".
WARNING:Xst:646 - Signal <SINIT_wire> is assigned but never used.
Found 17-bit up counter for signal <ADDR_wire>.
Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0000> created at line 235.
Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0001> created at line 241.
Found 10-bit comparator less for signal <ADDR_wire$cmp_lt0000> created at line 235.
Found 1-bit register for signal <SINIT_wire>.
Found 10-bit comparator greatequal for signal <SINIT_wire$cmp_ge0000> created at line 186.
Found 10-bit comparator less for signal <SINIT_wire$cmp_lt0000> created at line 186.
Found 10-bit comparator less for signal <SINIT_wire$cmp_lt0001> created at line 186.
Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0000> created at line 232.
Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0001> created at line 238.
Found 10-bit comparator less for signal <ADDR_wire$cmp_lt0000> created at line 232.
Found 10-bit comparator less for signal <ADDR_wire$cmp_lt0001> created at line 232.
Summary:
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 4 Comparator(s).
Unit <image_gen_bram> synthesized.
 
 
Synthesizing Unit <lq057q3dc02_top>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd".
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd".
Unit <lq057q3dc02_top> synthesized.
 
 
371,11 → 368,11
# Counters : 4
17-bit up counter : 1
9-bit up counter : 3
# Registers : 4
1-bit register : 4
# Comparators : 11
10-bit comparator greatequal : 4
10-bit comparator less : 7
# Registers : 3
1-bit register : 3
# Comparators : 9
10-bit comparator greatequal : 3
10-bit comparator less : 6
 
=========================================================================
 
414,11 → 411,11
# Counters : 4
17-bit up counter : 1
9-bit up counter : 3
# Registers : 9
Flip-Flops : 9
# Comparators : 11
10-bit comparator greatequal : 4
10-bit comparator less : 7
# Registers : 8
Flip-Flops : 8
# Comparators : 9
10-bit comparator greatequal : 3
10-bit comparator less : 6
 
=========================================================================
 
469,8 → 466,8
Final Register Report
 
Macro Statistics
# Registers : 53
Flip-Flops : 53
# Registers : 52
Flip-Flops : 52
 
=========================================================================
 
498,23 → 495,23
# IOs : 27
 
Cell Usage :
# BELS : 212
# BELS : 207
# GND : 6
# INV : 9
# LUT1 : 8
# LUT2 : 7
# LUT2_L : 4
# LUT3 : 26
# LUT3_D : 2
# LUT2_L : 5
# LUT3 : 25
# LUT3_D : 1
# LUT3_L : 1
# LUT4 : 55
# LUT4 : 52
# LUT4_L : 7
# MUXCY : 40
# MUXF5 : 2
# MUXF5 : 1
# VCC : 2
# XORCY : 43
# FlipFlops/Latches : 53
# FDC : 24
# FlipFlops/Latches : 52
# FDC : 23
# FDCE : 26
# FDP : 3
# Clock Buffers : 3
536,9 → 533,9
 
Selected Device : 2vp30ff896-7
 
Number of Slices: 60 out of 13696 0%
Number of Slice Flip Flops: 53 out of 27392 0%
Number of 4 input LUTs: 119 out of 27392 0%
Number of Slices: 58 out of 13696 0%
Number of Slice Flip Flops: 52 out of 27392 0%
Number of 4 input LUTs: 115 out of 27392 0%
Number of IOs: 27
Number of bonded IOBs: 26 out of 556 4%
Number of GCLKs: 3 out of 16 18%
565,7 → 562,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK_100M_PAD | DCM_INST:CLKDV | 53 |
CLK_100M_PAD | DCM_INST:CLKDV | 52 |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
573,10 → 570,10
-----------------------------------------------------------------------------------------------+----------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------+----------------------------------------------+-------+
V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv1_INV_0:O)| NONE(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_FFd3)| 12 |
V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv(V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv1_INV_0:O) | NONE(V_C/VSYNCx_C/line_num_reg_7) | 12 |
IMAGE/RSTx_inv(IMAGE/RSTx_inv1_INV_0:O) | NONE(IMAGE/ADDR_wire_15) | 18 |
V_C/HSYNCx_C/RSTx_inv(V_C/HSYNCx_C/RSTx_inv1_INV_0:O) | NONE(V_C/HSYNCx_C/num_hsyncx_clks_reg_2) | 10 |
V_C/HSYNCx_C/RSTx_inv(V_C/HSYNCx_C/RSTx_inv1_INV_0:O) | NONE(V_C/HSYNCx_C/num_hsyncx_clks_reg_5) | 10 |
IMAGE/RSTx_inv(IMAGE/RSTx_inv1_INV_0:O) | NONE(IMAGE/ADDR_wire_6) | 17 |
V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv(V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv1_INV_0:O) | NONE(V_C/VSYNCx_C/line_num_reg_5) | 12 |
V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv1_INV_0:O)| NONE(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_FFd1)| 12 |
V_C/ENAB_C/RSTx_inv(V_C/ENAB_C/RSTx_inv1_INV_0:O) | NONE(V_C/ENAB_C/ENAB) | 1 |
-----------------------------------------------------------------------------------------------+----------------------------------------------+-------+
 
596,7 → 593,7
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK_100M_PAD'
Clock period: 0.500ns (frequency: 2000.475MHz)
Total number of paths / destination ports: 2304 / 79
Total number of paths / destination ports: 2197 / 78
-------------------------------------------------------------------------
Delay: 3.999ns (Levels of Logic = 21)
Source: V_C/VSYNCx_C/line_num_reg_6 (FF)
612,7 → 609,7
end scope: 'VSYNCx_C'
end scope: 'V_C'
begin scope: 'IMAGE'
LUT4:I0->O 16 0.275 0.668 Mcount_ADDR_wire_lut<0>_SW0 (N146)
LUT4:I0->O 16 0.275 0.668 Mcount_ADDR_wire_lut<0>_SW0 (N92)
LUT4:I3->O 1 0.275 0.000 Mcount_ADDR_wire_lut<0> (N2)
MUXCY:S->O 1 0.334 0.000 Mcount_ADDR_wire_cy<0> (Mcount_ADDR_wire_cy<0>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<1> (Mcount_ADDR_wire_cy<1>)
638,7 → 635,7
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_100M_PAD'
Total number of paths / destination ports: 57 / 57
Total number of paths / destination ports: 54 / 54
-------------------------------------------------------------------------
Offset: 3.390ns (Levels of Logic = 2)
Source: V_C/HSYNCx_C/HSYNCx (FF)
662,14 → 659,14
Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Delay: 2.924ns (Levels of Logic = 2)
Source: IMAGE/image_BLUE_data:DOUT<5> (PAD)
Source: IMAGE/image_BLUE_data:douta<5> (PAD)
Destination: B<5> (PAD)
 
Data Path: IMAGE/image_BLUE_data:DOUT<5> to B<5>
Data Path: IMAGE/image_BLUE_data:douta<5> to B<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
image_gen_bram_blue:DOUT<5> 1 0.000 0.000 image_BLUE_data (B<5>)
image_gen_bram_blue:douta<5> 1 0.000 0.000 image_BLUE_data (B<5>)
end scope: 'IMAGE'
OBUF:I->O 2.592 B_5_OBUF (B<5>)
----------------------------------------
677,7 → 674,7
(100.0% logic, 0.0% route)
 
=========================================================================
CPU : 13.19 / 13.31 s | Elapsed : 13.00 / 14.00 s
CPU : 13.47 / 13.59 s | Elapsed : 13.00 / 13.00 s
-->
 
684,6 → 681,6
Total memory usage is 206148 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 21 ( 0 filtered)
Number of warnings : 22 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
/trunk/implement/results/lq057q3dc02_top.twr
33,8 → 33,8
NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%; multiplied by
16.00 and duty cycle corrected to 160 nS HIGH 80 nS
 
3903 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 10.079ns.
3691 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 9.208ns.
--------------------------------------------------------------------------------
 
================================================================================
56,7 → 56,7
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_100M_PAD | 10.079| | | |
CLK_100M_PAD | 9.208| | | |
---------------+---------+---------+---------+---------+
 
 
65,13 → 65,13
 
Timing errors: 0 Score: 0
 
Constraints cover 3903 paths, 0 nets, and 2359 connections
Constraints cover 3691 paths, 0 nets, and 1952 connections
 
Design statistics:
Minimum period: 10.079ns (Maximum frequency: 99.216MHz)
Minimum period: 9.208ns (Maximum frequency: 108.601MHz)
 
 
Analysis completed Thu Nov 06 13:57:08 2008
Analysis completed Thu Nov 06 18:46:44 2008
--------------------------------------------------------------------------------
 
Trace Settings:
/trunk/implement/results/lq057q3dc02_top.map
8,8 → 8,8
Target Device : xc2vp30
Target Package : ff896
Target Speed : -7
Mapper Version : virtex2p -- $Revision: 1.1 $
Mapped Date : Thu Nov 06 13:56:04 2008
Mapper Version : virtex2p -- $Revision: 1.2 $
Mapped Date : Thu Nov 06 18:45:32 2008
 
Mapping design into LUTs...
Writing file lq057q3dc02_top.ngm...
18,42 → 18,42
Running timing-driven packing...
 
Phase 1.1
Phase 1.1 (Checksum:98abc4) REAL time: 2 secs
Phase 1.1 (Checksum:98a19b) REAL time: 3 secs
 
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 2 secs
Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs
 
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 2 secs
Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs
 
Phase 4.2
.
Phase 4.2 (Checksum:26259fc) REAL time: 2 secs
Phase 4.2 (Checksum:26259fc) REAL time: 3 secs
 
Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 2 secs
Phase 5.30 (Checksum:2faf07b) REAL time: 3 secs
 
Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 3 secs
Phase 6.3 (Checksum:39386fa) REAL time: 4 secs
 
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs
Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs
 
Phase 8.4
.....................
Phase 8.4 (Checksum:4c4b3f8) REAL time: 7 secs
.........
Phase 8.4 (Checksum:4c4b3f8) REAL time: 9 secs
 
Phase 9.28
Phase 9.28 (Checksum:55d4a77) REAL time: 8 secs
Phase 9.28 (Checksum:55d4a77) REAL time: 9 secs
 
Phase 10.8
.......................................
..
..........................................................
.........
.
...............
...............
...............
Phase 10.8 (Checksum:f0addd) REAL time: 11 secs
...............
Phase 10.8 (Checksum:caed37) REAL time: 11 secs
 
Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 11 secs
73,8 → 73,8
Phase 16.24
Phase 16.24 (Checksum:98967f0) REAL time: 13 secs
 
REAL time consumed by placer: 14 secs
CPU time consumed by placer: 13 secs
REAL time consumed by placer: 13 secs
CPU time consumed by placer: 12 secs
Inspecting route info ...
Route info done.
 
85,13 → 85,13
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 85 out of 27,392 1%
Number of 4 input LUTs: 385 out of 27,392 1%
Number of Slice Flip Flops: 66 out of 27,392 1%
Number of 4 input LUTs: 189 out of 27,392 1%
Logic Distribution:
Number of occupied Slices: 250 out of 13,696 1%
Total Number of 4 input LUTs: 405 out of 27,392 1%
Number used as logic: 385
Number used as a route-thru: 20
Number of occupied Slices: 127 out of 13,696 1%
Total Number of 4 input LUTs: 197 out of 27,392 1%
Number used as logic: 189
Number used as a route-thru: 8
 
Number of bonded IOBs: 27 out of 556 4%
IOB Flip Flops: 1
102,11 → 102,11
Number of GTs: 0 out of 8 0%
Number of GT10s: 0 out of 0 0%
 
Total equivalent gate count for design: 5,712,197
Total equivalent gate count for design: 5,710,614
Additional JTAG gate count for IOBs: 1,296
Peak Memory Usage: 238 MB
Total REAL time to MAP completion: 23 secs
Total CPU time to MAP completion: 22 secs
Peak Memory Usage: 228 MB
Total REAL time to MAP completion: 24 secs
Total CPU time to MAP completion: 21 secs
 
Mapping completed.
See MAP report file "lq057q3dc02_top.mrp" for details.
/trunk/implement/results/lq057q3dc02_top.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/implement/results/lq057q3dc02_top.mrp
8,8 → 8,8
Target Device : xc2vp30
Target Package : ff896
Target Speed : -7
Mapper Version : virtex2p -- $Revision: 1.1 $
Mapped Date : Thu Nov 06 13:56:04 2008
Mapper Version : virtex2p -- $Revision: 1.2 $
Mapped Date : Thu Nov 06 18:45:32 2008
 
Design Summary
--------------
16,13 → 16,13
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 85 out of 27,392 1%
Number of 4 input LUTs: 385 out of 27,392 1%
Number of Slice Flip Flops: 66 out of 27,392 1%
Number of 4 input LUTs: 189 out of 27,392 1%
Logic Distribution:
Number of occupied Slices: 250 out of 13,696 1%
Total Number of 4 input LUTs: 405 out of 27,392 1%
Number used as logic: 385
Number used as a route-thru: 20
Number of occupied Slices: 127 out of 13,696 1%
Total Number of 4 input LUTs: 197 out of 27,392 1%
Number used as logic: 189
Number used as a route-thru: 8
 
Number of bonded IOBs: 27 out of 556 4%
IOB Flip Flops: 1
33,11 → 33,11
Number of GTs: 0 out of 8 0%
Number of GT10s: 0 out of 0 0%
 
Total equivalent gate count for design: 5,712,197
Total equivalent gate count for design: 5,710,614
Additional JTAG gate count for IOBs: 1,296
Peak Memory Usage: 238 MB
Total REAL time to MAP completion: 23 secs
Total CPU time to MAP completion: 22 secs
Peak Memory Usage: 228 MB
Total REAL time to MAP completion: 24 secs
Total CPU time to MAP completion: 21 secs
 
Table of Contents
-----------------
66,7 → 66,7
N2,
DCM_LCD_CLK/CLKFX_OUT,
DCM_LCD_CLK/N0,
IMAGE/N196,
IMAGE/N136,
V_C/VSYNCx_C/N42
To see the details of these warning messages, please use the -detail switch.
 
94,7 → 94,7
 
Section 4 - Removed Logic Summary
---------------------------------
9 block(s) removed
15 block(s) removed
14 block(s) optimized away
10 signal(s) removed
 
119,7 → 119,7
The signal "DCM_LCD_CLK/CLKFX_BUF" is sourceless and has been removed.
Sourceless block "DCM_LCD_CLK/CLKFX_BUFG_INST" (CKBUF) removed.
The signal "DCM_LCD_CLK/N0" is sourceless and has been removed.
The signal "IMAGE/N196" is sourceless and has been removed.
The signal "IMAGE/N136" is sourceless and has been removed.
The signal "V_C/VSYNCx_C/N42" is sourceless and has been removed.
The signal "V_C/CLK_LCD_CYCLE_Cntr/N119" is sourceless and has been removed.
The signal "V_C/ENAB_C/N65" is sourceless and has been removed.
126,6 → 126,12
The signal "V_C/ENAB_C/N66" is sourceless and has been removed.
Unused block "DCM_LCD_CLK/XST_VCC" (ONE) removed.
Unused block "IMAGE/XST_VCC" (ONE) removed.
Unused block "IMAGE/image_BLUE_data/GND" (ZERO) removed.
Unused block "IMAGE/image_BLUE_data/VCC" (ONE) removed.
Unused block "IMAGE/image_GREEN_data/GND" (ZERO) removed.
Unused block "IMAGE/image_GREEN_data/VCC" (ONE) removed.
Unused block "IMAGE/image_RED_data/GND" (ZERO) removed.
Unused block "IMAGE/image_RED_data/VCC" (ONE) removed.
Unused block "V_C/CLK_LCD_CYCLE_Cntr/XST_VCC" (ONE) removed.
Unused block "V_C/ENAB_C/XST_GND" (ZERO) removed.
Unused block "V_C/ENAB_C/XST_VCC" (ONE) removed.
135,12 → 141,12
TYPE BLOCK
GND DCM_LCD_CLK/XST_GND
GND IMAGE/XST_GND
GND IMAGE/image_BLUE_data/GND
VCC IMAGE/image_BLUE_data/VCC
GND IMAGE/image_GREEN_data/GND
VCC IMAGE/image_GREEN_data/VCC
GND IMAGE/image_RED_data/GND
VCC IMAGE/image_RED_data/VCC
GND IMAGE/image_BLUE_data/BU2/XST_GND
VCC IMAGE/image_BLUE_data/BU2/XST_VCC
GND IMAGE/image_GREEN_data/BU2/XST_GND
VCC IMAGE/image_GREEN_data/BU2/XST_VCC
GND IMAGE/image_RED_data/BU2/XST_GND
VCC IMAGE/image_RED_data/BU2/XST_VCC
GND V_C/CLK_LCD_CYCLE_Cntr/XST_GND
GND V_C/HSYNCx_C/XST_GND
VCC V_C/HSYNCx_C/XST_VCC
229,8 → 235,8
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP | 153.129ns| 6.871ns| 0| 0
V_BUF" derived from NET "DCM_LCD_CLK/CLK | HOLD | 0.622ns| | 0| 0
PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP | 154.254ns| 5.746ns| 0| 0
V_BUF" derived from NET "DCM_LCD_CLK/CLK | HOLD | 0.608ns| | 0| 0
IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50% mu | | | | |
ltiplied by 16.00 and duty cycle correcte | | | | |
d to 160 nS HIGH 80 nS | | | | |
/trunk/implement/results/lq057q3dc02_top.blc
5,26 → 5,11
lq057q3dc02_top.ngc
 
Reading NGO file
"D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/implement/results/lq057
q3dc02_top_part.ngc" ...
Launcher: The source netlist for "image_gen_bram_red.ngo" was not found; the
current NGO file will be used and no new NGO description will be compiled. This
probably means that the source netlist was moved or deleted.
Loading design module
"D:\MyDocuments\OpenCores\projects\lq057q3dc02\hdl\vhsic\netlists\image_gen_bram
_red.ngo"...
Launcher: The source netlist for "image_gen_bram_green.ngo" was not found; the
current NGO file will be used and no new NGO description will be compiled. This
probably means that the source netlist was moved or deleted.
Loading design module
"D:\MyDocuments\OpenCores\projects\lq057q3dc02\hdl\vhsic\netlists\image_gen_bram
_green.ngo"...
Launcher: The source netlist for "image_gen_bram_blue.ngo" was not found; the
current NGO file will be used and no new NGO description will be compiled. This
probably means that the source netlist was moved or deleted.
Loading design module
"D:\MyDocuments\OpenCores\projects\lq057q3dc02\hdl\vhsic\netlists\image_gen_bram
_blue.ngo"...
"D:/MyDocuments/OpenCores/projects/lq057q3dc02/implement/results/lq057q3dc02_top
_part.ngc" ...
Loading design module "..\..\netlists/image_gen_bram_red.ngc"...
Loading design module "..\..\netlists/image_gen_bram_green.ngc"...
Loading design module "..\..\netlists/image_gen_bram_blue.ngc"...
 
Applying constraints in "board.ucf" to the design...
 
/trunk/implement/results/lq057q3dc02_top.bld
4,8 → 4,8
Command Line: ngdbuild lq057q3dc02_top.ngc lq057q3dc02_top.ngd
 
Reading NGO file
"D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/implement/results/lq057
q3dc02_top.ngc" ...
"D:/MyDocuments/OpenCores/projects/lq057q3dc02/implement/results/lq057q3dc02_top
.ngc" ...
 
Checking timing specifications ...
Checking expanded design ...
/trunk/implement/results/lq057q3dc02_top.par
1,7 → 1,7
Release 9.2.04i par J.40
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
 
NAUTILUS:: Thu Nov 06 13:56:37 2008
NAUTILUS:: Thu Nov 06 18:46:08 2008
 
par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf
 
27,38 → 27,38
Number of LOCed IOBs 27 out of 27 100%
 
Number of RAMB16s 87 out of 136 63%
Number of SLICEs 250 out of 13696 1%
Number of SLICEs 127 out of 13696 1%
 
 
Overall effort level (-ol): High
Router effort level (-rl): High
 
Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 8 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
 
Starting Router
 
Phase 1: 2989 unrouted; REAL time: 19 secs
Phase 1: 4052 unrouted; REAL time: 21 secs
 
Phase 2: 2827 unrouted; REAL time: 19 secs
Phase 2: 3381 unrouted; REAL time: 22 secs
 
Phase 3: 411 unrouted; REAL time: 21 secs
Phase 3: 340 unrouted; REAL time: 26 secs
 
Phase 4: 411 unrouted; (0) REAL time: 21 secs
Phase 4: 340 unrouted; (0) REAL time: 26 secs
 
Phase 5: 411 unrouted; (0) REAL time: 21 secs
Phase 5: 340 unrouted; (0) REAL time: 26 secs
 
Phase 6: 411 unrouted; (0) REAL time: 21 secs
Phase 6: 340 unrouted; (0) REAL time: 26 secs
 
Phase 7: 0 unrouted; (0) REAL time: 22 secs
Phase 7: 0 unrouted; (0) REAL time: 27 secs
 
Phase 8: 0 unrouted; (0) REAL time: 23 secs
Phase 8: 0 unrouted; (0) REAL time: 28 secs
 
WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
 
Total REAL time to Router completion: 23 secs
Total CPU time to Router completion: 23 secs
Total REAL time to Router completion: 28 secs
Total CPU time to Router completion: 28 secs
 
Partition Implementation Status
-------------------------------
76,7 → 76,7
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_LCD_OBUF | BUFGMUX6P| No | 155 | 0.234 | 1.229 |
| CLK_LCD_OBUF | BUFGMUX6P| No | 135 | 0.261 | 1.238 |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
90,15 → 90,15
 
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
 
The AVERAGE CONNECTION DELAY for this design is: 2.107
The MAXIMUM PIN DELAY IS: 8.688
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 7.641
The AVERAGE CONNECTION DELAY for this design is: 2.320
The MAXIMUM PIN DELAY IS: 8.568
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 7.164
 
Listing Pin Delays by value: (nsec)
 
d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 9.00 d >= 9.00
--------- --------- --------- --------- --------- ---------
1599 1024 311 73 8 0
1084 783 326 65 4 0
 
Timing Score: 0
 
111,8 → 111,8
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP | 149.921ns| 10.079ns| 0| 0
V_BUF" derived from NET "DCM_LCD_CLK/CLK | HOLD | 0.562ns| | 0| 0
PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP | 150.792ns| 9.208ns| 0| 0
V_BUF" derived from NET "DCM_LCD_CLK/CLK | HOLD | 0.609ns| | 0| 0
IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD | N/A | N/A| N/A| N/A| N/A
131,10 → 131,10
 
All signals are completely routed.
 
Total REAL time to PAR completion: 25 secs
Total CPU time to PAR completion: 25 secs
Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 30 secs
 
Peak Memory Usage: 196 MB
Peak Memory Usage: 201 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
/trunk/implement/results/lq057q3dc02_top.bgn
6,7 → 6,7
speed -7
Opened constraints file lq057q3dc02_top.pcf.
 
Thu Nov 06 13:57:11 2008
Thu Nov 06 18:46:48 2008
 
bitgen -g StartUpClk:JTAGCLK -g GTS_cycle:1 -g GWE_cycle:1 -g LCK_cycle:2 -g DONE_cycle:4 -w lq057q3dc02_top.ncd
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.