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<b><font size=+2 face="Helvetica, Arial"
color=#bf0000>Project Name: MIPS-lite core</font></b>
<p>
<font size=+1><b>Description</b></font>
<P>
MIPS-lite is a "clean room" VHDL implementation of a MIPS CPU.
It supports a simplified MIPS III+ instruction set with a two-stage pipeline.
Only User Mode instructions are supported.
 
<p>
<font size=+1><b>Block Diagram</b></font>
<p>
<center>
<img src="cpu.gif">
</center>
<br>
<font size=+1><b>Example Instruction</b></font>
<p>
As an example, an ADD instruction would take the following steps:
<ol>
<li>The "pc_next" entity would pass the program
counter (PC) to the "mem_ctrl" entity. [First Stage of Pipeline]</li>
<li>"Mem_ctrl" passes the opcode to the "control" entity.</li>
<li>"Control" converts the 32-bit opcode to a 60-bit VLWI opcode
and sends control signals to the other entities.</li>
<li>Based on the rs_index and rt_index control signals, "reg_bank"
sends the 32-bit reg_source and reg_target to "bus_mux".</li>
<li>Based on the a_source and b_source control signals, "bus_mux"
multiplexes reg_source onto a_bus and reg_target onto b_bus.</li>
<li>Based on the alu_func control signals, "alu" adds the values
from a_bus and b_bus and places the result on c_bus.</li>
<li>Based on the c_source control signals, "bus_bux" multiplexes
c_bus onto reg_dest.</li>
<li>Based on the rd_index control signal, "reg_bank" saves
reg_dest into the correct register.</li>
</ol>
<font size=+1><b>Features</b></font>
<p>
The CPU is implemented as a two-stage pipeline with step #1 in the
first stage and steps #2-8 occurring the second stage.
Each instruction takes one clock cycle, except memory accesses,
which take two clock cycles, and multiplication and division, which
can be accessed in 32 clock cycles.
<br>
<br>
There are several control lines not shown in the diagram.
A pause (wait-state) line will cause the pipeline to pause
if the multiplication results are accessed before the
multiplication is complete.
 
<p>
<font size=+1><b>Supporting Documentation</b></font>
<p>
The implementation is based on information found in:
<ul>
<li>"MIPS RISC Architecture" by Gerry Kane and Joe Heinrich and</li>
<li>"The Designer's Guide to VHDL" by Peter J. Ashenden</li>
</ul>
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<font size=+1><b>Tools</b></font>
<p>
The tools used include VHDL Synopsys, ModelTech, and the Microsoft
MIPS C compiler.
 
<p>
<font size=+1><b>Registers</b></font>
<p>
All of the registers are clocked by the single master clock.
The registers used in the design are grouped by entity and listed below:
<pre width=80>
mem_ctrl
===========================================
| Register Name | Type | Width |
===========================================
| next_opcode_reg_reg | Flip-flop | 32 |
| opcode_reg_reg | Flip-flop | 32 |
| setup_done_reg | Flip-flop | 1 |
===========================================
mult
===========================================
| Register Name | Type | Width |
===========================================
| answer_reg_reg | Flip-flop | 32 |
| count_reg_reg | Flip-flop | 6 |
| do_div_reg_reg | Flip-flop | 1 |
| do_signed_reg_reg | Flip-flop | 1 |
| reg_a_reg | Flip-flop | 32 |
| reg_b_reg | Flip-flop | 64 |
===========================================
pc_next
===========================================
| Register Name | Type | Width |
===========================================
| pc_reg_reg | Flip-flop | 30 |
===========================================
reg_bank
===========================================
| Register Name | Type | Width |
===========================================
| reg01_reg | Flip-flop | 32 |
| reg02_reg | Flip-flop | 32 |
| reg03_reg | Flip-flop | 32 |
| reg04_reg | Flip-flop | 32 |
| reg05_reg | Flip-flop | 32 |
| reg06_reg | Flip-flop | 32 |
| reg07_reg | Flip-flop | 32 |
| reg08_reg | Flip-flop | 32 |
| reg09_reg | Flip-flop | 32 |
| reg10_reg | Flip-flop | 32 |
| reg11_reg | Flip-flop | 32 |
| reg12_reg | Flip-flop | 32 |
| reg13_reg | Flip-flop | 32 |
| reg14_reg | Flip-flop | 32 |
| reg15_reg | Flip-flop | 32 |
| reg16_reg | Flip-flop | 32 |
| reg17_reg | Flip-flop | 32 |
| reg18_reg | Flip-flop | 32 |
| reg19_reg | Flip-flop | 32 |
| reg20_reg | Flip-flop | 32 |
| reg21_reg | Flip-flop | 32 |
| reg22_reg | Flip-flop | 32 |
| reg23_reg | Flip-flop | 32 |
| reg24_reg | Flip-flop | 32 |
| reg25_reg | Flip-flop | 32 |
| reg26_reg | Flip-flop | 32 |
| reg27_reg | Flip-flop | 32 |
| reg28_reg | Flip-flop | 32 |
| reg29_reg | Flip-flop | 32 |
| reg30_reg | Flip-flop | 32 |
| reg31_reg | Flip-flop | 32 |
| reg_epc_reg | Flip-flop | 32 |
| reg_status_reg | Flip-flop | 1 |
===========================================
</pre>
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<font size=+1><b>Preliminary Synthesis</b></font>
<p>
The CPU core was synthesized for 0.13 um line widths with a predicted
area less than 0.2 millimeters squared. The predicted maximum
latency was less than 6 ns for a maximum clock speed of 150 MHz.
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<b><font size=+2 color=#bf0000>Project: MIPS-lite core</font></b><p><b><font size=+1>Details</font></b> <p>Category: <a href='/projects?category=microprocessor'>Microprocessor</a><br>Last updated: 16/1/2002<br>Created: 25/9/2001<br>Wishbone compliant core: No<br>Stage: Production/Stable<br>Mailing list: <a href='/forums/cores'>Cores</a><p><b><font size=+1>Description</font></b>
<p>MIPS-lite is a "clean room" VHDL implementation of a MIPS CPU. It supports the MIPS I instruction set with a two-stage pipeline. Interrupts and User Mode instructions are supported. <br><p><b><font size=+1>Block diagram</font></b>
<p><p><center><img src='cpu.gif' border=0></center><p><b><font size=+1>Example Instruction</font></b>
<p>As an example, an ADD instruction would take the following steps:
<br><ul>
1.The "pc_next" entity would pass the program counter (PC) to the "mem_ctrl" entity. [First Stage of Pipeline]
<br> 2."Mem_ctrl" passes the opcode to the "control" entity.
<br> 3."Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
<br> 4.Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".
<br> 5.Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
<br> 6.Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
<br> 7.Based on the c_source control signals, "bus_bux" multiplexes c_bus onto reg_dest.
<br> 8.Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.
<br></ul><p><b><font size=+1>Features</font></b>
<p>The CPU is implemented as a two-stage pipeline with step #1 in the first stage and steps #2-8 occurring the second stage. Most instructions take one clock cycle. Interrupts are supported. A four cycle memory write is also supported for non-clocked memories.
<br>
<br>There are several control lines not shown in the diagram. A pause (wait-state) line will cause the pipeline to pause if the multiplication results are accessed before the multiplication is complete. <br><p><b><font size=+1>Supporting Documentation</font></b>
<p>The implementation is based on information found in:
<br>
A preliminary synthesis yields the following cells and die area.
I think that optimization caused the mips_cpu entity
to be smaller than the sum of its
components.
If one assumes that a standard cell is composed of three gates,
then this is approximately a 20K gate design. [Is this correct??]
It is interesting to note that the register bank requires over 60% of the area.
<pre width=80>
Block ports nets cells cell_area ~% delay(ns)
------ ----- ---- ----- --------- --- ---------
alu 101 919 850 7503 12 1.11
bus_mux 283 672 486 4906 8 0.35
control 93 296 263 2250 4 0.29
mem_ctrl 271 455 318 3299 5 0.95
mult 101 1111 1043 9342 15 0.72 ??
pc_next 94 277 215 1756 3 0.15
reg_bank 116 2650 2599 39477 62 1.02
shifter 71 423 384 3026 5 1.51
mips_cpu 201 555 45 63888 100 5.61
total 1331 7358 6203
</pre>
 
<font size=+1><b>List of Files</b></font>
<p>
<ul>
<br><ul><li>"MIPS RISC Architecture" by Gerry Kane and Joe Heinrich and
</li><li>"The Designer's Guide to VHDL" by Peter J. Ashenden
</li><li><a href="http://www.mips.com/declassified/Declassified_2001/MD00086-2B-MIPS32BIS-AFP-00.95.pdf">MIPS32(TM) Architecture for Programmers Volume II: The MIPS32(TM) Instruction Set</a>
</li></ul><p><b><font size=+1>Tools</font></b>
<p>The tools used include VHDL Synopsys, ModelTech, the free VHDL simulator from <a href="http://www.symphonyeda.com/">Symphony</a>, and the <a href="/cores/mips/Gccmips.zip">GCC compiler</a> (121 KB for Windows PC host, MIPS target; optimization -O doesn't work).
<br>
<br><p><b><font size=+1>Registers</font></b>
<p>All of the registers are clocked by the single master clock. The registers used in the design are grouped by entity and listed below:
<br>
<br><pre>
<br> mem_ctrl
<br> ===========================================
<br> | Register Name | Type | Width |
<br> ===========================================
<br> | next_opcode_reg | Flip-flop | 32 |
<br> | opcode_reg | Flip-flop | 32 |
<br> | setup_done_reg | Flip-flop | 1 |
<br> ===========================================
<br>
<br> mips_cpu
<br> ===========================================
<br> | Register Name | Type | Width |
<br> ===========================================
<br> | intr_signal | Flip-flop | 1 |
<br> | reset_reg | Flip-flop | 1 |
<br> ===========================================
<br>
<br> mult
<br> ===========================================
<br> | Register Name | Type | Width |
<br> ===========================================
<br> | answer_reg | Flip-flop | 32 |
<br> | count_reg | Flip-flop | 6 |
<br> | do_div_reg | Flip-flop | 1 |
<br> | do_signed_reg | Flip-flop | 1 |
<br> | reg_a | Flip-flop | 32 |
<br> | reg_b | Flip-flop | 64 |
<br> ===========================================
<br>
<br> pc_next
<br> ===========================================
<br> | Register Name | Type | Width |
<br> ===========================================
<br> | pc_reg | Flip-flop | 30 |
<br> ===========================================
<br>
<br> reg_bank (configured to used dual port memory)
<br> ===========================================
<br> | Register Name | Type | Width |
<br> ===========================================
<br> | reg00_reg | Flip-flop | 32 |
<br> | ... |
<br> | reg31_reg | Flip-flop | 32 |
<br> | reg_status_reg | Flip-flop | 1 |
<br> ===========================================
<br>
<br></pre><br><p><b><font size=+1>Preliminary Synthesis</font></b>
<p>The CPU core was synthesized for 0.13 um line widths with a predicted area less than 0.2 millimeters squared. The predicted maximum latency was less than 6 ns for a maximum clock speed of 150 MHz.
<br>
<br>A preliminary synthesis yields the following cells and die area. If one assumes that a standard cell is composed of three gates, then this is approximately a 20K gate design. It is interesting to note that the register bank requires over 60% of the area.
<br><pre>
<br> Block ports nets cells cell_area ~% delay(ns)
<br> ------ ----- ---- ----- --------- --- ---------
<br> alu 101 919 850 7503 12 1.11
<br> bus_mux 283 672 486 4906 8 0.35
<br> control 93 296 263 2250 4 0.29
<br> mem_ctrl 271 455 318 3299 5 0.95
<br> mult 101 1111 1043 9342 15 0.72
<br> pc_next 94 277 215 1756 3 0.15
<br> reg_bank 116 2650 2599 39477 62 1.02
<br> shifter 71 423 384 3026 5 1.51
<br> mips_cpu 201 555 45 63888 100 5.61
<br>
<br> total 1331 7358 6203
<br>
<br></pre><br><p><b><font size=+1>List of Files</font></b>
<p><ul>
<table border="2" style="border-color:Black;border-collapse:collapse;">
<tr>
<td>FILE</td>
176,7 → 322,7
</td><tr>
</tr><tr>
<td>makefile</td>
<td>Makefile for the HP workstation for Synopsys</td>
<td>Makefile for the PC based VHDL simulator</td>
</tr><tr>
<td>code.txt</td>
<td>Input opcodes for the test bench -- test.exe "converted"</td>
221,6 → 367,12
<td>makefile</td>
<td>Makefile for the PC for creating "code.txt"</td>
</tr><tr>
<td>boot.asm</td>
<td>Initializes $gp and $sp, clears .bss</td>
</tr><tr>
<td>opcodes.asm</td>
<td>Tests all the MIPS I opcodes</td>
</tr><tr>
<td>convert.c</td>
<td>Converts test.exe to code.txt</td>
</tr><tr>
230,11 → 382,17
<td>test.c</td>
<td>Test program (opcodes) for the MIPS CPU</td>
</tr><tr>
<td>pi.c</td>
<td>Calculates the first 16 digits of PI</td>
</tr><tr>
<td>count.c</td>
<td>Test program that counts using words</td>
</tr><tr>
<td>output.txt</td>
<td>Output from the test bench</td>
</tr><tr>
<td>index.shtml</td>
<td>This help file</td>
<td>Old copy of this help file</td>
</tr><tr>
<td>cpu.gif</td>
<td>Block Diagram</td>
241,91 → 399,94
</tr>
</table>
</ul>
<p><b><font size=+1>Downloads</font></b>
<p><table border=0 cellpadding=0 cellspacing=0 bgcolor='#000000' width=100%><tr><td><table border=0 cellpadding=3 cellspacing=1 width=100%><tr bgcolor='#c0e0ff'><td valign=top><b>Date</b></td><td valign=top><b>Description</b></td><td valign=top><b>Link</b></td></tr><tr bgcolor='#ffffff'><td valign=top>15/10/2001</td><td valign=top>Whole MIPS project<br></td><td valign=top><a href='/cgi-bin/cvsget.cgi/mips'>mips</a></td></tr></table></td></tr></table><p><b><font size=+1>Convert</font></b>
<p>The program "convert" changes the file "test.exe" into the HEX file "code.txt". The register $gp is initialized, and the .bss segment is cleared.
<br><p><b><font size=+1>Big/Little Endian</font></b>
<p>The MIPS CPU operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd. <br><p><b><font size=+1>Legal Notice</font></b>
<p><font color=red>MIPS is a registered trademark of MIPS Technologies, Inc. If you use this core you are responsible for all legal issues. This "clean room" implementation of a MIPS CPU does not negate MIPS Technologies, Inc. of their trademark, copyrights, or patents....
<br>
<br>Free for commercial and non-commercial use as long as the author and warning notices are maintained.
<br>
<br>This software is provided by Steve Rhoads "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.
<br></font><br><p><b><font size=+1>Bus Interface</font></b>
<p>All signals are active high. Writing to memory normally takes four cycles to meet address hold times. Addresses with mem_address(31)='1' take two cycles (assumed to be clocked). Below are the signals for writing a character to address 0xffff:
<br>
<br><pre>
<br> entity mips_cpu is
<br> port(clk : in std_logic;
<br> reset_in : in std_logic;
<br> intr_in : in std_logic;
<br>
<br> mem_address : out std_logic_vector(31 downto 0);
<br> mem_data_w : out std_logic_vector(31 downto 0);
<br> mem_data_r : in std_logic_vector(31 downto 0);
<br> mem_byte_sel: out std_logic_vector(3 downto 0);
<br> mem_write : out std_logic;
<br> mem_pause : in std_logic);
<br> end; --entity mips_cpu
<br>
<br>
<br> mem_write
<br> interrupt mem_byte_sel
<br> reset mem_pause
<br> ns mem_address m_data_w m_data_r
<br> ===========================================
<br> 6700 0 0 0 000002A4 ZZZZZZZZ A0AE0000 0 0 ( fetch write opcode)
<br> 6800 0 0 0 000002B0 ZZZZZZZZ 0443FFF6 0 0 (1 fetch NEXT opcode)
<br> 6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (2 address hold)
<br> 7000 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1 (3 write the low byte)
<br> 7100 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (4 address hold)
<br> 7200 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0 ( execute NEXT opcode)
<br>
<br></pre><br><p><b><font size=+1>Status</font></b>
<p><ul><li>All MIPS I instructions are implemented and tested with the following limitations (no exceptions; all 32-bit memory accesses must be long word aligned)
</li><li>See "opcodes.asm" for regression test.
</li><li>Tested with several C programs: Calculating PI; Prime Numbers; Showing Numbers Using Words.
</li><li>Supports Interrupts
</li><li>Runs in a Xilinx FPGA
</li></ul><p><b><font size=+1>Maintainers</font></b>
<p><ul><li><a href='/people/rhoads'>Steve Rhoads</a></li></ul><p>
 
<p>
<font size=+1><b>Download Files</b></font>
<p>
Use CVS to download the files in the "mips" project.
To run a CGI script to run CVS to get all the files click
<a href="http://www.opencores.org/cgi-bin/cvsget.cgi?module=mips">
here</a>.
 
<p>
<font size=+1><b>Convert</b></font>
<p>
The program "convert" changes the file "test.exe" into the HEX file "code.txt".
The opcodes in "test.exe" are changed to Big Endian.
All absolute jumps are changed to relative jumps.
The first opcode is also changed to set up the stack pointer.
 
<p>
<font size=+1><b>Big/Little Endian</b></font>
<p>
The MIPS CPU operates in Big Endian mode by default. To operate in
Little Endian mode, change "little_endian" from "00" to "11" in
the file mem_ctrl.vhd.
 
<p>
<font size=+1><b>Legal Notice</b></font>
<p>
<font color="#FF0000">
MIPS is a registered trademark of MIPS Technologies, Inc.
If you use this core you are responsible for all legal issues.
This "clean room" implementation of a MIPS CPU does not negate
MIPS Technologies, Inc. of their trademark, copyrights, or patents....
<p>
Free for commercial and non-commercial use as long as the author and
warning notices are maintained.
<br>
<br>
This software is provided by Steve Rhoads "as is" and
any express or implied warranties, including, but not limited to, the
implied warranties of merchantability and fitness for a particular purpose
are disclaimed. In no event shall the author or contributors be liable
for any direct, indirect, incidental, special, exemplary, or consequential
damages (including, but not limited to, procurement of substitute goods
or services; loss of use, data, or profits; or business interruption)
however caused and on any theory of liability, whether in contract, strict
liability, or tort (including negligence or otherwise) arising in any way
out of the use of this software, even if advised of the possibility of
such damage.
</font>
<p>
<p><b><font size="+1">Bus Interface</font></b></p>
<p>
<pre width=80>
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic; --interrupt line
 
--memory access buses
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0); --avoided tri-state
mem_data_r : in std_logic_vector(31 downto 0);
mem_sel : out std_logic_vector(3 downto 0); --byte lines
mem_write : out std_logic;
mem_pause : in std_logic
);
</pre>
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<font size=+1><b>Current Status</b></font>
<ul>
<li>The test bench needs to be strengthened.</li>
<li>Need feedback on the design.</li>
<li>Need feedback on the tools.</li>
<li>Need to add simulation of a cache.</li>
</ul>
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<p>
<font size=+1><b>Maintainer</b></font>
<ul>Steve Rhoads,
<a href="mailto:rhoads@opencores.org_NOSPAM">rhoads@opencores.org_NOSPAM</a></ul>
<p>
<ul>*** I am not an experienced VHDL designer ***
Please let me know of any incorrect statements in this document.</ul>
<p>
<font size=+1><b>Mailing-list</b></font>
<p>
<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
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