URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 371 to Rev 372
- ↔ Reverse comparison
Rev 371 → Rev 372
/trunk/insight/gdb/config/or1k/tm-or1k.h
120,6 → 120,7
#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7) |
#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16) |
#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17) |
#define PPC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 18) |
#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid)) |
#define EPCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 32 + (cid)) |
#define EPCR0_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 32) |
158,7 → 159,7
|
/* Changed by CZ 21/06/01 */ |
#define DRR_TE (0x00002000) |
#define DRR_BE (0x00001000) |
#define DRR_SSE (0x00001000) |
#define DRR_SCE (0x00000800) |
#define DRR_RE (0x00000400) |
#define DRR_IME (0x00000200) |
280,6 → 281,9
|
#define DECR_PC_AFTER_BREAK 0 |
|
/* Don't step over l.trap */ |
#define CANNOT_STEP_BREAKPOINT |
|
extern int or1k_insert_breakpoint (CORE_ADDR addr, char *contents_cache); |
#define target_insert_hw_breakpoint(addr, cache) or1k_insert_breakpoint (addr, cache) |
|
/trunk/insight/gdb/remote-or1k.c
45,6 → 45,7
/* The following prototype is necessary or the compiler will not |
correctly promote the data argument to ULONGEST */ |
static void or1k_write_reg (unsigned int, ULONGEST); |
static int insn_has_delay_slot (unsigned int); |
|
/* JTAG or1k target ops. */ |
extern void jtag_init PARAMS ((char * args)); |
521,7 → 522,7
or1k_write_spr_reg (SR_SPRNUM, or1k_read_spr_reg(SR_SPRNUM) | 0x2); |
|
/* Stop when breakpoint occurs. */ |
or1k_write_spr_reg (DSR_SPRNUM, 0x2000); |
or1k_write_spr_reg (DSR_SPRNUM, dsr = 0x2000); |
|
do_cleanups (old_cleanups); |
|
731,7 → 732,15
int pid, step; |
enum target_signal siggnal; |
{ |
debug ("pc = %08x\n", read_pc()); |
unsigned int pc; |
unsigned int ppc; |
unsigned int npc; |
unsigned int val; |
|
pc = read_pc(); |
npc = or1k_read_spr_reg (PC_SPRNUM); |
ppc = or1k_read_spr_reg (PPC_SPRNUM); |
debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc); |
debug ("resume %i, %i, %i\n",step, siggnal, or1k_status); |
if (or1k_status != TARGET_STOPPED) |
if (or1k_status == TARGET_RUNNING) |
747,11 → 756,42
|
/* Else clause added by CZ 26/06/01 */ |
if (step) |
{ |
{ |
/* HW STEP. Set DMR1_ST. */ |
dmr1 |= DMR1_ST; |
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
dmr1 &= ~DMR1_ST; |
|
if (breakpoint_here_p (pc) && ((ppc + 4) != npc)) |
{ |
/* Trapped on delay slot instruction. */ |
/* Set PC to branch insn preceding delay slot. */ |
or1k_write_spr_reg (PC_SPRNUM, ppc - 4); |
|
or1k_unstall (); |
|
or1k_set_chain (SC_REGISTER); |
val = or1k_read_reg (JTAG_RISCOP); |
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
} |
else if (breakpoint_here_p (npc) && insn_has_delay_slot (or1k_fetch_instruction (ppc))) |
{ |
/* Steping to the trap insn in delay slot - we need to execute branch insn again */ |
debug ("resume: steping to the trap insn in delay slot\n"); |
or1k_write_spr_reg (PC_SPRNUM, ppc); |
|
or1k_unstall (); |
|
or1k_set_chain (SC_REGISTER); |
val = or1k_read_reg (JTAG_RISCOP); |
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
} |
else if (breakpoint_here_p (pc)) |
or1k_write_spr_reg (PC_SPRNUM, pc); |
} |
else |
{ |
774,10 → 814,11
{ |
unsigned long val; |
unsigned long pc; |
unsigned long npc; |
unsigned long ppc; |
char buf[MAX_REGISTER_RAW_SIZE]; |
interrupt_count = 0; |
|
debug ("pc = %08x\n", read_pc()); |
debug ("wait %i %i\n", pid, or1k_status); |
/* If we have not sent a single step or continue command, then the |
board is waiting for us to do something. Return a status |
801,24 → 842,25
do { |
or1k_set_chain (SC_REGISTER); |
val = or1k_read_reg (JTAG_RISCOP); |
|
|
/* When we press Ctrl-C, interrupt count is set, but we must wait |
for or1k_read_reg to finish, otherwise we would interrupt transaction. */ |
if (interrupt_count) |
or1k_stop (); |
or1k_stop (); |
|
usleep (10); |
debug ("%i", val); |
} while ((val & 1) == 0); |
|
} while ((val & 1) == 0); |
|
drr = or1k_read_spr_reg (DRR_SPRNUM); |
|
|
/* Restore old INT signal handler */ |
signal (SIGINT, ofunc); |
|
/* If we encounter breakpoint, drr is not set, so we set it manually. */ |
if (!drr) |
drr |= DRR_BE; |
/* Single step does not set trap exception, so we set it manually to simplify our code */ |
dmr1 = or1k_read_spr_reg (DMR1_SPRNUM); |
if (dmr1 & DMR1_ST) |
drr |= DRR_TE; |
|
status->kind = TARGET_WAITKIND_STOPPED; |
|
827,48 → 869,96
|
registers_changed (); |
pc = read_pc (); |
debug ("pc = %08x\n", pc); |
npc = or1k_read_spr_reg (PC_SPRNUM); |
ppc = or1k_read_spr_reg (PPC_SPRNUM); |
debug ("npc = %08x ppc = %08x\n", npc, ppc); |
|
if (drr & DRR_RSTE) |
status->value.sig = TARGET_SIGNAL_REALTIME_33; |
if (drr & DRR_TE) |
{ |
/* If single step is not set, we should correct the pc. */ |
if (!(dmr1 & DMR1_ST)) |
/* PC has already stepped over the l.trap instruction. */ |
pc = ppc; |
status->value.sig = TARGET_SIGNAL_TRAP; |
drr &= ~DRR_TE; |
} |
else if (drr & DRR_RSTE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_33; |
drr &= ~DRR_RSTE; |
} |
else if (drr & DRR_BUSEE) |
status->value.sig = TARGET_SIGNAL_BUS; |
else if (drr & DRR_DPFE) |
status->value.sig = TARGET_SIGNAL_REALTIME_34; |
else if (drr & DRR_IPFE) |
status->value.sig = TARGET_SIGNAL_REALTIME_35; |
else if (drr & DRR_LPINTE) |
status->value.sig = TARGET_SIGNAL_INT; |
{ |
status->value.sig = TARGET_SIGNAL_BUS; |
drr &= ~DRR_BUSEE; |
} |
else if (drr & DRR_AE) |
status->value.sig = TARGET_SIGNAL_REALTIME_36; |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_36; |
drr &= ~DRR_AE; |
} |
else if (drr & DRR_IIE) |
status->value.sig = TARGET_SIGNAL_ILL; |
else if (drr & DRR_HPINTE) |
status->value.sig = TARGET_SIGNAL_INT; |
{ |
status->value.sig = TARGET_SIGNAL_ILL; |
drr &= ~DRR_IIE; |
} |
else if (drr & DRR_RE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_39; |
drr &= ~DRR_RE; |
} |
else if (drr & DRR_IME) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_38; |
drr &= ~DRR_IME; |
} |
else if (drr & DRR_DME) |
status->value.sig = TARGET_SIGNAL_REALTIME_37; |
else if (drr & DRR_IME) |
status->value.sig = TARGET_SIGNAL_REALTIME_38; |
else if (drr & DRR_RE) |
status->value.sig = TARGET_SIGNAL_REALTIME_39; |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_37; |
drr &= ~DRR_DME; |
} |
else if (drr & DRR_DPFE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_34; |
drr &= ~DRR_DPFE; |
} |
else if (drr & DRR_IPFE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_35; |
drr &= ~DRR_DPFE; |
} |
else if (drr & DRR_SCE) |
status->value.sig = TARGET_SIGNAL_REALTIME_40; |
else if (drr & DRR_BE) |
status->value.sig = TARGET_SIGNAL_TRAP; |
else if (drr & DRR_TE) |
{ |
/* PC has already stepped over the l.trap instruction. */ |
pc -= 8; |
status->value.sig = TARGET_SIGNAL_TRAP; |
} else { |
status->value.sig = TARGET_SIGNAL_REALTIME_40; |
drr &= ~DRR_SCE; |
} |
else if (drr & DRR_HPINTE) |
{ |
status->value.sig = TARGET_SIGNAL_INT; |
drr &= ~DRR_HPINTE; |
} |
else if (drr & DRR_LPINTE) |
{ |
status->value.sig = TARGET_SIGNAL_INT; |
drr &= ~DRR_LPINTE; |
} |
else |
{ |
status->value.sig = TARGET_SIGNAL_UNKNOWN; |
warning ("Invalid exception occured."); |
} |
} |
|
/* Update drr register */ |
or1k_write_spr_reg (DRR_SPRNUM, drr); |
|
/* Write into PC flushes the pipeline! */ |
/* We got the number the register holds, but gdb expects to see a |
value in the target byte ordering. */ |
write_pc (pc); |
/* write_pc (pc); |
*/ |
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc); |
supply_register (PC_REGNUM, buf); |
|
/*or1k_write_spr_reg (PC_SPRNUM, pc); |
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc); |
supply_register (PC_REGNUM, buf);*/ |
1662,6 → 1752,15
printf_filtered ("\n"); |
} |
} |
static int |
insn_has_delay_slot (insn) |
unsigned int insn; |
{ |
if (((insn >> 26) <= 4) || ((insn >> 26) == 17) || ((insn >> 26) == 18)) |
return 1; |
else |
return 0; |
} |
|
void |
_initialize_remote_or1k () |
/trunk/insight/gdb/or1k-tdep.c
43,17 → 43,20
/* Group reg name size. See or1k_reg_names. */ |
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = { |
72, 0, 0, 6, 4, 2, |
22, 16, 1, 3, 2, 8}; |
22, 16, 1, 3, 2, 8 |
}; |
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = { |
0, 0, 0, 253, 254, 256, |
0, 248, 16, 16, 255, 0}; |
0, 248, 16, 16, 255, 0 |
}; |
|
/* Generated reg names (max valid alias index). |
See or1k_spr_reg_name. */ |
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = { |
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1, |
78+1, 263+1, 16+1, 18+1, 256+1, 7+1}; |
78+1, 263+1, 16+1, 18+1, 256+1, 7+1 |
}; |
|
/* Register names. */ |
char *or1k_reg_names[] = { |
107,8 → 110,8
static char *or1k_gdb_reg_names[] = { |
|
/* general purpose registers */ |
"R0", "R1(SP)", "R2(FP)", "R3(A0)", "R4(A1)", "R5(A2)", "R6(A3)", "R7(A4)", |
"R8(A5)", "R9(LR)", "R10", "R11(RV)", "R12", "R13", "R14", "R15", |
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", |
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", |
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31", |
|
122,8 → 125,8
}; |
|
static char *or1k_group_names[] = { |
"SYS", "DMMU", "IMMU", "DCACHE", "ICACHE", "MAC", "DEBUG", "PERF", "POWER", |
"PIC", "TIMER", "CONFIG" |
"SYS", "DMMU", "IMMU", "DCACHE", "ICACHE", "MAC", "DEBUG", "PERF", |
"POWER", "PIC", "TIMER", "CONFIG" |
}; |
|
/* Table of or1k signals. */ |
1007,16 → 1010,14
} |
|
/* Return nonzero when instruction has delay slot. */ |
|
static int |
is_delayed (insn) |
unsigned long insn; |
{ |
int i; |
for (i = 0; i < num_opcodes; ++i) |
if ((or32_opcodes[i].flags & OR32_IF_DELAY) |
&& (or32_opcode_match (insn, or32_opcodes[i].encoding))) |
break; |
return (i < num_opcodes); |
int index; |
index = insn_decode (insn); |
return or32_opcodes[index].flags & OR32_IF_DELAY; |
} |
|
int |
2254,7 → 2255,7
void |
_initialize_or1k_tdep () |
{ |
|
build_automata (); |
/* Added by CZ 26/06/01 */ |
if(TARGET_BYTE_ORDER == BIG_ENDIAN) |
tm_print_insn = print_insn_big_or32; |
2320,3 → 2321,4
add_com ("sim", class_obscure, sim_command, |
"Send a extended command to the simulator."); |
} |
|
/trunk/gdb-5.0/gdb/remote-or1k.c
45,6 → 45,7
/* The following prototype is necessary or the compiler will not |
correctly promote the data argument to ULONGEST */ |
static void or1k_write_reg (unsigned int, ULONGEST); |
static int insn_has_delay_slot (unsigned int); |
|
/* JTAG or1k target ops. */ |
extern void jtag_init PARAMS ((char * args)); |
521,7 → 522,7
or1k_write_spr_reg (SR_SPRNUM, or1k_read_spr_reg(SR_SPRNUM) | 0x2); |
|
/* Stop when breakpoint occurs. */ |
or1k_write_spr_reg (DSR_SPRNUM, 0x2000); |
or1k_write_spr_reg (DSR_SPRNUM, dsr = 0x2000); |
|
do_cleanups (old_cleanups); |
|
731,7 → 732,15
int pid, step; |
enum target_signal siggnal; |
{ |
debug ("pc = %08x\n", read_pc()); |
unsigned int pc; |
unsigned int ppc; |
unsigned int npc; |
unsigned int val; |
|
pc = read_pc(); |
npc = or1k_read_spr_reg (PC_SPRNUM); |
ppc = or1k_read_spr_reg (PPC_SPRNUM); |
debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc); |
debug ("resume %i, %i, %i\n",step, siggnal, or1k_status); |
if (or1k_status != TARGET_STOPPED) |
if (or1k_status == TARGET_RUNNING) |
747,11 → 756,42
|
/* Else clause added by CZ 26/06/01 */ |
if (step) |
{ |
{ |
/* HW STEP. Set DMR1_ST. */ |
dmr1 |= DMR1_ST; |
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
dmr1 &= ~DMR1_ST; |
|
if (breakpoint_here_p (pc) && ((ppc + 4) != npc)) |
{ |
/* Trapped on delay slot instruction. */ |
/* Set PC to branch insn preceding delay slot. */ |
or1k_write_spr_reg (PC_SPRNUM, ppc - 4); |
|
or1k_unstall (); |
|
or1k_set_chain (SC_REGISTER); |
val = or1k_read_reg (JTAG_RISCOP); |
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
} |
else if (breakpoint_here_p (npc) && insn_has_delay_slot (or1k_fetch_instruction (ppc))) |
{ |
/* Steping to the trap insn in delay slot - we need to execute branch insn again */ |
debug ("resume: steping to the trap insn in delay slot\n"); |
or1k_write_spr_reg (PC_SPRNUM, ppc); |
|
or1k_unstall (); |
|
or1k_set_chain (SC_REGISTER); |
val = or1k_read_reg (JTAG_RISCOP); |
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
} |
else if (breakpoint_here_p (pc)) |
or1k_write_spr_reg (PC_SPRNUM, pc); |
} |
else |
{ |
774,10 → 814,11
{ |
unsigned long val; |
unsigned long pc; |
unsigned long npc; |
unsigned long ppc; |
char buf[MAX_REGISTER_RAW_SIZE]; |
interrupt_count = 0; |
|
debug ("pc = %08x\n", read_pc()); |
debug ("wait %i %i\n", pid, or1k_status); |
/* If we have not sent a single step or continue command, then the |
board is waiting for us to do something. Return a status |
801,24 → 842,25
do { |
or1k_set_chain (SC_REGISTER); |
val = or1k_read_reg (JTAG_RISCOP); |
|
|
/* When we press Ctrl-C, interrupt count is set, but we must wait |
for or1k_read_reg to finish, otherwise we would interrupt transaction. */ |
if (interrupt_count) |
or1k_stop (); |
or1k_stop (); |
|
usleep (10); |
debug ("%i", val); |
} while ((val & 1) == 0); |
|
} while ((val & 1) == 0); |
|
drr = or1k_read_spr_reg (DRR_SPRNUM); |
|
|
/* Restore old INT signal handler */ |
signal (SIGINT, ofunc); |
|
/* If we encounter breakpoint, drr is not set, so we set it manually. */ |
if (!drr) |
drr |= DRR_BE; |
/* Single step does not set trap exception, so we set it manually to simplify our code */ |
dmr1 = or1k_read_spr_reg (DMR1_SPRNUM); |
if (dmr1 & DMR1_ST) |
drr |= DRR_TE; |
|
status->kind = TARGET_WAITKIND_STOPPED; |
|
827,48 → 869,96
|
registers_changed (); |
pc = read_pc (); |
debug ("pc = %08x\n", pc); |
npc = or1k_read_spr_reg (PC_SPRNUM); |
ppc = or1k_read_spr_reg (PPC_SPRNUM); |
debug ("npc = %08x ppc = %08x\n", npc, ppc); |
|
if (drr & DRR_RSTE) |
status->value.sig = TARGET_SIGNAL_REALTIME_33; |
if (drr & DRR_TE) |
{ |
/* If single step is not set, we should correct the pc. */ |
if (!(dmr1 & DMR1_ST)) |
/* PC has already stepped over the l.trap instruction. */ |
pc = ppc; |
status->value.sig = TARGET_SIGNAL_TRAP; |
drr &= ~DRR_TE; |
} |
else if (drr & DRR_RSTE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_33; |
drr &= ~DRR_RSTE; |
} |
else if (drr & DRR_BUSEE) |
status->value.sig = TARGET_SIGNAL_BUS; |
else if (drr & DRR_DPFE) |
status->value.sig = TARGET_SIGNAL_REALTIME_34; |
else if (drr & DRR_IPFE) |
status->value.sig = TARGET_SIGNAL_REALTIME_35; |
else if (drr & DRR_LPINTE) |
status->value.sig = TARGET_SIGNAL_INT; |
{ |
status->value.sig = TARGET_SIGNAL_BUS; |
drr &= ~DRR_BUSEE; |
} |
else if (drr & DRR_AE) |
status->value.sig = TARGET_SIGNAL_REALTIME_36; |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_36; |
drr &= ~DRR_AE; |
} |
else if (drr & DRR_IIE) |
status->value.sig = TARGET_SIGNAL_ILL; |
else if (drr & DRR_HPINTE) |
status->value.sig = TARGET_SIGNAL_INT; |
{ |
status->value.sig = TARGET_SIGNAL_ILL; |
drr &= ~DRR_IIE; |
} |
else if (drr & DRR_RE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_39; |
drr &= ~DRR_RE; |
} |
else if (drr & DRR_IME) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_38; |
drr &= ~DRR_IME; |
} |
else if (drr & DRR_DME) |
status->value.sig = TARGET_SIGNAL_REALTIME_37; |
else if (drr & DRR_IME) |
status->value.sig = TARGET_SIGNAL_REALTIME_38; |
else if (drr & DRR_RE) |
status->value.sig = TARGET_SIGNAL_REALTIME_39; |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_37; |
drr &= ~DRR_DME; |
} |
else if (drr & DRR_DPFE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_34; |
drr &= ~DRR_DPFE; |
} |
else if (drr & DRR_IPFE) |
{ |
status->value.sig = TARGET_SIGNAL_REALTIME_35; |
drr &= ~DRR_DPFE; |
} |
else if (drr & DRR_SCE) |
status->value.sig = TARGET_SIGNAL_REALTIME_40; |
else if (drr & DRR_BE) |
status->value.sig = TARGET_SIGNAL_TRAP; |
else if (drr & DRR_TE) |
{ |
/* PC has already stepped over the l.trap instruction. */ |
pc -= 8; |
status->value.sig = TARGET_SIGNAL_TRAP; |
} else { |
status->value.sig = TARGET_SIGNAL_REALTIME_40; |
drr &= ~DRR_SCE; |
} |
else if (drr & DRR_HPINTE) |
{ |
status->value.sig = TARGET_SIGNAL_INT; |
drr &= ~DRR_HPINTE; |
} |
else if (drr & DRR_LPINTE) |
{ |
status->value.sig = TARGET_SIGNAL_INT; |
drr &= ~DRR_LPINTE; |
} |
else |
{ |
status->value.sig = TARGET_SIGNAL_UNKNOWN; |
warning ("Invalid exception occured."); |
} |
} |
|
/* Update drr register */ |
or1k_write_spr_reg (DRR_SPRNUM, drr); |
|
/* Write into PC flushes the pipeline! */ |
/* We got the number the register holds, but gdb expects to see a |
value in the target byte ordering. */ |
write_pc (pc); |
/* write_pc (pc); |
*/ |
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc); |
supply_register (PC_REGNUM, buf); |
|
/*or1k_write_spr_reg (PC_SPRNUM, pc); |
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc); |
supply_register (PC_REGNUM, buf);*/ |
1662,6 → 1752,15
printf_filtered ("\n"); |
} |
} |
static int |
insn_has_delay_slot (insn) |
unsigned int insn; |
{ |
if (((insn >> 26) <= 4) || ((insn >> 26) == 17) || ((insn >> 26) == 18)) |
return 1; |
else |
return 0; |
} |
|
void |
_initialize_remote_or1k () |
/trunk/gdb-5.0/gdb/or1k-tdep.c
43,17 → 43,20
/* Group reg name size. See or1k_reg_names. */ |
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = { |
72, 0, 0, 6, 4, 2, |
22, 16, 1, 3, 2, 8}; |
22, 16, 1, 3, 2, 8 |
}; |
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = { |
0, 0, 0, 253, 254, 256, |
0, 248, 16, 16, 255, 0}; |
0, 248, 16, 16, 255, 0 |
}; |
|
/* Generated reg names (max valid alias index). |
See or1k_spr_reg_name. */ |
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = { |
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1, |
78+1, 263+1, 16+1, 18+1, 256+1, 7+1}; |
78+1, 263+1, 16+1, 18+1, 256+1, 7+1 |
}; |
|
/* Register names. */ |
char *or1k_reg_names[] = { |
107,8 → 110,8
static char *or1k_gdb_reg_names[] = { |
|
/* general purpose registers */ |
"R0", "R1(SP)", "R2(FP)", "R3(A0)", "R4(A1)", "R5(A2)", "R6(A3)", "R7(A4)", |
"R8(A5)", "R9(LR)", "R10", "R11(RV)", "R12", "R13", "R14", "R15", |
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", |
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", |
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31", |
|
122,8 → 125,8
}; |
|
static char *or1k_group_names[] = { |
"SYS", "DMMU", "IMMU", "DCACHE", "ICACHE", "MAC", "DEBUG", "PERF", "POWER", |
"PIC", "TIMER", "CONFIG" |
"SYS", "DMMU", "IMMU", "DCACHE", "ICACHE", "MAC", "DEBUG", "PERF", |
"POWER", "PIC", "TIMER", "CONFIG" |
}; |
|
/* Table of or1k signals. */ |
1007,16 → 1010,14
} |
|
/* Return nonzero when instruction has delay slot. */ |
|
static int |
is_delayed (insn) |
unsigned long insn; |
{ |
int i; |
for (i = 0; i < num_opcodes; ++i) |
if ((or32_opcodes[i].flags & OR32_IF_DELAY) |
&& (or32_opcode_match (insn, or32_opcodes[i].encoding))) |
break; |
return (i < num_opcodes); |
int index; |
index = insn_decode (insn); |
return or32_opcodes[index].flags & OR32_IF_DELAY; |
} |
|
int |
2254,7 → 2255,7
void |
_initialize_or1k_tdep () |
{ |
|
build_automata (); |
/* Added by CZ 26/06/01 */ |
if(TARGET_BYTE_ORDER == BIG_ENDIAN) |
tm_print_insn = print_insn_big_or32; |
2320,3 → 2321,4
add_com ("sim", class_obscure, sim_command, |
"Send a extended command to the simulator."); |
} |
|
/trunk/gdb-5.0/gdb/config/or1k/tm-or1k.h
120,6 → 120,7
#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7) |
#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16) |
#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17) |
#define PPC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 18) |
#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid)) |
#define EPCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 32 + (cid)) |
#define EPCR0_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 32) |
158,7 → 159,7
|
/* Changed by CZ 21/06/01 */ |
#define DRR_TE (0x00002000) |
#define DRR_BE (0x00001000) |
#define DRR_SSE (0x00001000) |
#define DRR_SCE (0x00000800) |
#define DRR_RE (0x00000400) |
#define DRR_IME (0x00000200) |
280,6 → 281,9
|
#define DECR_PC_AFTER_BREAK 0 |
|
/* Don't step over l.trap */ |
#define CANNOT_STEP_BREAKPOINT |
|
extern int or1k_insert_breakpoint (CORE_ADDR addr, char *contents_cache); |
#define target_insert_hw_breakpoint(addr, cache) or1k_insert_breakpoint (addr, cache) |
|
/trunk/gdb-5.0/opcodes/Makefile.in
180,6 → 180,7
m10300-dis.c \ |
m10300-opc.c \ |
or32-dis.c \ |
or32.c \ |
ns32k-dis.c \ |
pj-dis.c \ |
pj-opc.c \ |
244,6 → 245,7
mips-opc.lo \ |
mips16-opc.lo \ |
or32-dis.lo \ |
or32.lo \ |
pj-dis.lo \ |
pj-opc.lo \ |
ppc-dis.lo \ |
/trunk/gdb-5.0/opcodes/configure.in
174,8 → 174,7
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; |
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; |
bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; |
bfd_or32_arch) ta="$ta or32-dis.lo" ;; |
bfd_or16_arch) ta="$ta or16-dis.lo" ;; |
bfd_or32_arch) ta="$ta or32-dis.lo or32.lo" ;; |
bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; |
bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; |
bfd_pyramid_arch) ;; |
/trunk/gdb-5.0/opcodes/configure
3952,8 → 3952,7
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; |
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; |
bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; |
bfd_or32_arch) ta="$ta or32-dis.lo" ;; |
bfd_or16_arch) ta="$ta or16-dis.lo" ;; |
bfd_or32_arch) ta="$ta or32-dis.lo or32.lo" ;; |
bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; |
bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; |
bfd_pyramid_arch) ;; |
/trunk/gdb-5.0/opcodes/or32-dis.c
28,34 → 28,8
#include <string.h> |
#include <stdlib.h> |
|
CONST unsigned int num_opcodes = (((sizeof or32_opcodes) / (sizeof or32_opcodes[0])) - 1); |
|
#define EXTEND29(x) ((x) & 0x10000000 ? ((x) | 0xf0000000) : ((x))) |
|
/* Calculates instruction length in bytes. Either 2 or 4 for OR16 |
and always 4 for OR32. */ |
int insn_len (char *insn) |
{ |
CONST struct or32_opcode *pinsn; |
char *enc; |
int len = 0; |
|
for(pinsn = or32_opcodes; strlen(pinsn->name); pinsn++) { |
if (strcmp(pinsn->name, insn) == 0) { |
for (enc = pinsn->encoding; *enc != '\0'; enc++) |
if ((*enc == '0') && (*(enc+1) == 'x')) { |
len += 4; |
enc += 2; |
} |
else if (!isspace(*enc)) |
len++; |
return len / 8; |
} |
} |
printf("insn_len(%s): Unknown instruction.\n", insn); |
exit(1); |
} |
|
/* Now find the four bytes of INSN_CH and put them in *INSN. */ |
static void |
find_bytes_big (insn_ch, insn) |
67,45 → 41,10
((unsigned long)insn_ch[2] << 8) + |
(unsigned long)insn_ch[3]; |
#if DEBUG |
printf("find_bytes_big3: %x\n", *insn); |
printf("find_bytes_big3: %x\n", *insn); |
#endif |
} |
|
/* Is individual insn's operand signed or unsigned? */ |
int letter_signed(char l) |
{ |
struct or32_letter *pletter; |
|
for(pletter = or32_letters; pletter->letter != '\0'; pletter++) |
if (pletter->letter == l) |
return pletter->sign; |
|
printf("letter_signed(%c): Unknown letter.\n", l); |
return 0; |
} |
|
/* Number of letters in the individual lettered operand. */ |
int letter_range(char l) |
{ |
CONST struct or32_opcode *pinsn; |
char *enc; |
int range = 0; |
|
for(pinsn = or32_opcodes; strlen(pinsn->name); pinsn++) { |
if (strchr(pinsn->encoding,l)) { |
for (enc = pinsn->encoding; *enc != '\0'; enc++) |
if ((*enc == '0') && (*(enc+1) == 'x')) { |
enc += 2; |
} |
else if (*enc == l) |
range++; |
return range; |
} |
} |
printf("\nABORT: letter_range(%c): Never used letter.\n", l); |
exit(1); |
} |
|
static void |
find_bytes_little (insn_ch, insn) |
unsigned char *insn_ch; |
135,64 → 74,71
for (enc = enc_initial; *enc != '\0'; enc++) |
if (*enc == param_ch) |
{ |
if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) |
continue; |
else |
param_pos++; |
if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) |
continue; |
else |
param_pos++; |
} |
|
#if DEBUG |
printf("or32_extract: %c %x ", param_ch, param_pos); |
#endif |
opc_pos = 32; |
for (enc = enc_initial; *enc != '\0'; ) |
if ((*enc == '0') && (*(enc+1) == 'x')) { |
opc_pos -= 4; |
if ((param_ch == '0') || (param_ch == '1')) { |
unsigned long tmp = strtol(enc, NULL, 16); |
opc_pos = 32; |
for (enc = enc_initial; *enc != '\0'; ) |
if ((*enc == '0') && (*(enc+1) == 'x')) |
{ |
opc_pos -= 4; |
if ((param_ch == '0') || (param_ch == '1')) |
{ |
unsigned long tmp = strtol(enc, NULL, 16); |
#if DEBUG |
printf(" enc=%s, tmp=%x ", enc, tmp); |
printf(" enc=%s, tmp=%x ", enc, tmp); |
#endif |
if (param_ch == '0') |
tmp = 15 - tmp; |
ret |= tmp << opc_pos; |
} |
enc += 3; |
} |
else if ((*enc == '0') || (*enc == '1')) { |
opc_pos--; |
if (param_ch == *enc) |
ret |= 1 << opc_pos; |
enc++; |
} |
else if (*enc == param_ch) { |
opc_pos--; |
param_pos--; |
if (param_ch == '0') |
tmp = 15 - tmp; |
ret |= tmp << opc_pos; |
} |
enc += 3; |
} |
else if ((*enc == '0') || (*enc == '1')) |
{ |
opc_pos--; |
if (param_ch == *enc) |
ret |= 1 << opc_pos; |
enc++; |
} |
else if (*enc == param_ch) |
{ |
opc_pos--; |
param_pos--; |
#if DEBUG |
printf("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); |
printf("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); |
#endif |
ret += ((insn >> opc_pos) & 0x1) << param_pos; |
if (!param_pos && letter_signed(param_ch) && ret >> (letter_range(param_ch) - 1)) { |
ret += ((insn >> opc_pos) & 0x1) << param_pos; |
if (!param_pos && letter_signed(param_ch) && ret >> (letter_range(param_ch) - 1)) |
{ |
#if DEBUG |
printf("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); |
printf("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); |
#endif |
ret |= 0xffffffff << letter_range(param_ch); |
ret |= 0xffffffff << letter_range(param_ch); |
#if DEBUG |
printf("\n after conversion to signed: ret=%x\n", ret); |
printf("\n after conversion to signed: ret=%x\n", ret); |
#endif |
} |
enc++; |
} |
else if (isalpha(*enc)) { |
opc_pos--; |
enc++; |
} |
else if (*enc == '-') { |
opc_pos--; |
enc++; |
} |
else |
enc++; |
} |
enc++; |
} |
else if (isalpha(*enc)) |
{ |
opc_pos--; |
enc++; |
} |
else if (*enc == '-') |
{ |
opc_pos--; |
enc++; |
} |
else |
enc++; |
|
#if DEBUG |
printf("ret=%x\n", ret); |
219,7 → 165,7
#endif |
if ((insn & ones) != ones) { |
#if DEBUG |
printf("ret1\n"); |
printf("ret1\n"); |
#endif |
return 0; |
} |
/trunk/gdb-5.0/opcodes/po/POTFILES.in
49,9 → 49,8
mips-dis.c |
mips-opc.c |
mips16-opc.c |
or16-dis.c |
or32-dis.c |
or1k-dis.c |
or32.c |
ns32k-dis.c |
pj-dis.c |
pj-opc.c |
/trunk/gdb-5.0/opcodes/Makefile.am
76,6 → 76,8
m10300-dis.c \ |
m10300-opc.c \ |
ns32k-dis.c \ |
or32-dis.c \ |
or32.c \ |
pj-dis.c \ |
pj-opc.c \ |
ppc-dis.c \ |
137,6 → 139,8
mips-dis.lo \ |
mips-opc.lo \ |
mips16-opc.lo \ |
or32-dis.lo \ |
or32.lo \ |
pj-dis.lo \ |
pj-opc.lo \ |
ppc-dis.lo \ |
351,6 → 355,7
ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ |
sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \ |
opintl.h |
or32-dis.lo: or32-dis.c $(INCDIR)/opcode/or32.h |
pj-dis.lo: pj-dis.c $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h \ |
$(BFD_H) $(INCDIR)/ansidecl.h |
pj-opc.lo: pj-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/pj.h |