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Rev 371 → Rev 372
/phr/trunk/doc/papers/PHR/CASE2014/beamer/PHRbeamer.tex
6,12 → 6,11
\usepackage{multirow} |
\usepackage{multicol} |
\usepackage{graphicx} |
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%\usepackage[hyphens]{url} |
%\usepackage[hyphenbreaks]{breakurl} |
\usepackage{url} |
\usepackage[hyphenbreaks]{breakurl} |
\usepackage[hyphens]{url} |
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% \usepackage{comment} |
% \excludecomment{figure} |
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\graphicspath{{images/}} |
%\graphicspath{{images/images-from-uEA2014/}} |
255,6 → 254,8
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\section{Antecedentes} %%%%%%%%%%%%%%%% |
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\subsection[Placa CPLD]{Kit de Desarrollo Educativo con CPLD} |
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\begin{frame} |
\frametitle{Kit de Desarrollo educativo con CPLD} |
\begin{center} |
271,6 → 272,8
\end{center} |
\end{frame} |
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\subsection{Proyecto FPGALibre} |
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\begin{frame} |
\frametitle{FPGALibre.sourceforge.net} |
\begin{center} |
292,21 → 295,21
por INTI – Electrónica e Informática. |
Toda la información de la tarjeta |
S3PROTO-MINI se encuentra en el |
sitio del proyecto FPGALibre |
sitio del proyecto FPGALibre\cite{s3proto-mini}. |
\end{block} |
|
\begin{block}{Proyecto S3PROTO} |
El proyecto S3PROTO tiene como |
objetivo final crear una plataforma |
FPGA que pueda alojar un diseño |
con un procesador LEON3 (GRLib) y |
un sistema GNU/Linux embebido. |
Para lograr esto es necesario |
primero abordar diseños multicapas y |
con chips FPGA de encapsulado |
BGA. Con este propósito se realizó el |
diseño de la S3PROTO-MIN |
\end{block} |
% \begin{block}{Proyecto S3PROTO} |
% El proyecto S3PROTO tiene como |
% objetivo final crear una plataforma |
% FPGA que pueda alojar un diseño |
% con un procesador LEON3 (GRLib) y |
% un sistema GNU/Linux embebido. |
% Para lograr esto es necesario |
% primero abordar diseños multicapas y |
% con chips FPGA de encapsulado |
% BGA. Con este propósito se realizó el |
% diseño de la S3PROTO-MIN |
% \end{block} |
|
\end{center} |
\end{frame} |
390,26 → 393,48
\end{columns} |
\end{frame} |
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% \begin{frame} |
% \frametitle{Plataforma de Hardware Reconfigurable} |
% \begin{center} |
% \includegraphics[width=1\textwidth]{images-from-uEA2014/phr_small.png} |
% \end{center} |
% \end{frame} |
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% \begin{frame} |
% \frametitle{Hardware libre} |
% \begin{center} |
% \includegraphics[width=0.9\textwidth]{images-from-uEA2014/Ohw-logo.pdf} |
% \end{center} |
% \end{frame} |
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|
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
\section{Placa PHR} |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\begin{frame} |
\frametitle{Plataforma de Hardware Reconfigurable} |
\frametitle{Placa PHR} |
\begin{center} |
\includegraphics[width=1\textwidth]{images-from-uEA2014/phr_small.png} |
\includegraphics[width=\textwidth]{images-from-uEA2014/phr_text.png} |
\end{center} |
\end{frame} |
|
\begin{frame} |
\frametitle{Hardware libre} |
\frametitle{Diagrama de bloques del Hardware} |
%\transfade |
\begin{center} |
\includegraphics[width=0.9\textwidth]{images-from-uEA2014/Ohw-logo.pdf} |
\includegraphics<1>[width=0.9\textwidth]{images-from-uEA2014/block1.pdf} |
\includegraphics<2>[width=0.9\textwidth]{images-from-uEA2014/block2.pdf} |
\includegraphics<3>[width=0.9\textwidth]{images-from-uEA2014/block3.pdf} |
\end{center} |
\end{frame} |
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|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
\section[Dispositivos]{Dispositivos Principales} |
\subsection[Dispositivos]{Dispositivos Principales} |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\subsection{FPGA} %%%%%%%%%%%%%%%%%%%%%%%%%%% |
\subsubsection{FPGA} %%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\begin{frame} |
\frametitle{FPGA} |
464,7 → 489,7
\end{center} |
\end{frame} |
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\subsection{Memoria de Configuración} %%%%%%%%%%%%%%%%%%%%%%%%%%% |
\subsubsection{Memoria de Configuración} %%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\begin{frame} |
\frametitle{Tipo de memoria para la familia Spartan-3A} |
490,27 → 515,6
\end{center} |
\end{frame} |
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
\section{Placa PHR} |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\begin{frame} |
\frametitle{Placa PHR} |
\begin{center} |
\includegraphics[width=\textwidth]{images-from-uEA2014/phr_text.png} |
\end{center} |
\end{frame} |
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\begin{frame} |
\frametitle{Diagrama de bloques del Hardware} |
%\transfade |
\begin{center} |
\includegraphics<1>[width=0.9\textwidth]{images-from-uEA2014/block1.pdf} |
\includegraphics<2>[width=0.9\textwidth]{images-from-uEA2014/block2.pdf} |
\includegraphics<3>[width=0.9\textwidth]{images-from-uEA2014/block3.pdf} |
\end{center} |
\end{frame} |
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\subsection{Características} %%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\begin{frame} |
538,20 → 542,20
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\end{frame} |
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\begin{frame} |
\frametitle{El chip FPGA (XC3S200A)} |
\begin{description}[E/S pares diferenciales máximo:] |
\item [Número de compuertas:] 200K |
\item [Celdas lógicas equivalentes:] 4032 |
\item [CLBs:] 448 |
\item [Bits de RAM distribuida:] 28K |
\item [Bits de Bloques de RAM:] 288K |
\item [Multiplicadores dedicados:] 16 |
\item [DCMs:] 4 |
\item [Máximo número de E/S:] 248 |
\item [E/S pares diferenciales máximo:] 112 |
\end{description} |
\end{frame} |
% \begin{frame} |
% \frametitle{El chip FPGA (XC3S200A)} |
% \begin{description}[E/S pares diferenciales máximo:] |
% \item [Número de compuertas:] 200K |
% \item [Celdas lógicas equivalentes:] 4032 |
% \item [CLBs:] 448 |
% \item [Bits de RAM distribuida:] 28K |
% \item [Bits de Bloques de RAM:] 288K |
% \item [Multiplicadores dedicados:] 16 |
% \item [DCMs:] 4 |
% \item [Máximo número de E/S:] 248 |
% \item [E/S pares diferenciales máximo:] 112 |
% \end{description} |
% \end{frame} |
|
|
\begin{frame}[b] |
669,12 → 673,12
\end{itemize} |
\end{frame} |
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\begin{frame} |
\frametitle{Arranque} |
\begin{center} |
\includegraphics[width=0.9\textwidth]{images-from-uEA2014/arranque.pdf} |
\end{center} |
\end{frame} |
% \begin{frame} |
% \frametitle{Arranque} |
% \begin{center} |
% \includegraphics[width=0.9\textwidth]{images-from-uEA2014/arranque.pdf} |
% \end{center} |
% \end{frame} |
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
829,7 → 833,7
\appendix |
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
\section*{Terminando} |
\section*{OpenHardware} |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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\subsection{Comunidad} %%%%%%%%%%%%%%%% |
925,6 → 929,10
\beamertemplatebookbibitems |
\bibitem{act-curricula} |
P.~Cayuela, \emph{Actualización de la currícula -- Incorporación de la lógica programable en ingeniería}, Jornada de Investigación y Desarrollo en Ingeniería de Software (JIDIS'07). Córdoba Argentina. 2007. |
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\beamertemplatebookbibitems |
\bibitem{s3proto-mini} |
FPGALibre, \emph{S3PROTO-MINI - Proyecto FPGA Libre - SourceForge}, url: \texttt{\burl{http://fpgalibre.sourceforge.net/varios/brochure-s3proto-mini.pdf}}. |
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\end{thebibliography} |
\end{frame} |
931,12 → 939,19
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\subsection{Fin} %%%%%%%%%%%%%%%% |
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% \begin{frame} |
% \frametitle{¿Preguntas?} |
% \begin{center} |
% \includegraphics[height=0.9\textheight]{images-from-uEA2014/question_.pdf} |
% \end{center} |
% \end{frame} |
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\begin{frame} |
\frametitle{¿Preguntas?} |
\begin{center} |
\includegraphics[height=0.9\textheight]{images-from-uEA2014/question_.pdf} |
\end{center} |
\frametitle{Fin} |
\begin{center} |
¡Muchas gracias!\\ |
¿Preguntas? |
\end{center} |
\end{frame} |
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\end{document} |