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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 374 to Rev 375
    ↔ Reverse comparison
  •

Rev 374 → Rev 375

/trunk/insight/gdb/remote-or1k.c
161,8 → 161,7
/* Reason of last stop. */
static int hit_watchpoint = 0;
static int hit_breakpoint = 0;
static int next_breakpoint = 0;
static int prev_step_insn_has_delay_slot = 0;
static int new_pc_set = 0;
 
/* Current register values. */
unsigned int dmr1 = 0;
300,7 → 299,7
or1k_write_reg (regno, (ULONGEST)data);
if (regno == PC_SPRNUM) {
hit_breakpoint = 0;
prev_step_insn_has_delay_slot = 0;
new_pc_set = 1;
}
}
 
743,6 → 742,7
unsigned int ppc;
unsigned int npc;
unsigned int val;
unsigned int ppc_insn;
pc = read_pc();
npc = or1k_read_spr_reg (PC_SPRNUM);
761,6 → 761,8
 
or1k_commit_debug_registers ();
 
ppc_insn = or1k_fetch_instruction(ppc);
 
/* Else clause added by CZ 26/06/01 */
if (step)
{
769,9 → 771,29
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
dmr1 &= ~DMR1_ST;
 
prev_step_insn_has_delay_slot = insn_has_delay_slot (or1k_fetch_instruction (ppc));
if (new_pc_set)
{
or1k_write_spr_reg (PC_SPRNUM, pc);
new_pc_set = 0;
}
else if (insn_has_delay_slot (ppc_insn) && (ppc != pc))
{
/* Steping across delay slot insn - we have to reexcute branch insn */
 
if (hit_breakpoint && ((ppc + 4) != npc))
if(breakpoint_here_p (ppc))
or1k_write_mem(ppc, ppc_insn);
or1k_write_spr_reg (PC_SPRNUM, ppc);
 
or1k_unstall ();
 
or1k_set_chain (SC_REGISTER);
val = or1k_read_reg (JTAG_RISCOP);
do {
val = or1k_read_reg (JTAG_RISCOP);
} while ((val & 1) == 0);
}
else if (hit_breakpoint && ((ppc + 4) != npc))
{
/* Trapped on delay slot instruction. */
/* Set PC to branch insn preceding delay slot. */
785,32 → 807,47
val = or1k_read_reg (JTAG_RISCOP);
} while ((val & 1) == 0);
}
else if (next_breakpoint && insn_has_delay_slot (or1k_fetch_instruction (ppc)))
else
or1k_write_spr_reg (PC_SPRNUM, pc);
 
}
else
{
dmr1 &= ~DMR1_ST;
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
 
if (new_pc_set)
{
/* Steping to the trap insn in delay slot - we need to execute branch insn again */
debug ("resume: steping to the trap insn in delay slot\n");
or1k_write_spr_reg (PC_SPRNUM, pc);
new_pc_set = 0;
}
else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc))
or1k_write_spr_reg (PC_SPRNUM, ppc);
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc))
{
or1k_write_mem(ppc, ppc_insn);
 
dmr1 |= DMR1_ST;
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
dmr1 &= ~DMR1_ST;
 
or1k_write_spr_reg (PC_SPRNUM, ppc);
or1k_unstall ();
 
or1k_set_chain (SC_REGISTER);
val = or1k_read_reg (JTAG_RISCOP);
do {
val = or1k_read_reg (JTAG_RISCOP);
} while ((val & 1) == 0);
or1k_write_mem(ppc, 0x21000001);
 
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
}
else if (hit_breakpoint)
else
or1k_write_spr_reg (PC_SPRNUM, pc);
}
else
{
dmr1 &= ~DMR1_ST;
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
if (prev_step_insn_has_delay_slot)
or1k_write_spr_reg (PC_SPRNUM, ppc);
else
or1k_write_spr_reg (PC_SPRNUM, npc);
}
 
/* We can now continue normally, independent of step */
or1k_unstall ();
827,7 → 864,6
{
unsigned long val;
unsigned long pc;
unsigned long npc;
unsigned long ppc;
char buf[MAX_REGISTER_RAW_SIZE];
interrupt_count = 0;
882,9 → 918,8
 
registers_changed ();
pc = read_pc ();
npc = or1k_read_spr_reg (PC_SPRNUM);
ppc = or1k_read_spr_reg (PPC_SPRNUM);
debug ("npc = %08x ppc = %08x\n", npc, ppc);
debug ("ppc = %08x\n", ppc);
 
if (drr & DRR_TE)
{
973,7 → 1008,6
supply_register (PC_REGNUM, buf);
 
hit_breakpoint = breakpoint_here_p (pc);
next_breakpoint = breakpoint_here_p (npc);
/*or1k_write_spr_reg (PC_SPRNUM, pc);
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
/trunk/gdb-5.0/gdb/remote-or1k.c
161,8 → 161,7
/* Reason of last stop. */
static int hit_watchpoint = 0;
static int hit_breakpoint = 0;
static int next_breakpoint = 0;
static int prev_step_insn_has_delay_slot = 0;
static int new_pc_set = 0;
 
/* Current register values. */
unsigned int dmr1 = 0;
300,7 → 299,7
or1k_write_reg (regno, (ULONGEST)data);
if (regno == PC_SPRNUM) {
hit_breakpoint = 0;
prev_step_insn_has_delay_slot = 0;
new_pc_set = 1;
}
}
 
743,6 → 742,7
unsigned int ppc;
unsigned int npc;
unsigned int val;
unsigned int ppc_insn;
pc = read_pc();
npc = or1k_read_spr_reg (PC_SPRNUM);
761,6 → 761,8
 
or1k_commit_debug_registers ();
 
ppc_insn = or1k_fetch_instruction(ppc);
 
/* Else clause added by CZ 26/06/01 */
if (step)
{
769,9 → 771,29
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
dmr1 &= ~DMR1_ST;
 
prev_step_insn_has_delay_slot = insn_has_delay_slot (or1k_fetch_instruction (ppc));
if (new_pc_set)
{
or1k_write_spr_reg (PC_SPRNUM, pc);
new_pc_set = 0;
}
else if (insn_has_delay_slot (ppc_insn) && (ppc != pc))
{
/* Steping across delay slot insn - we have to reexcute branch insn */
 
if (hit_breakpoint && ((ppc + 4) != npc))
if(breakpoint_here_p (ppc))
or1k_write_mem(ppc, ppc_insn);
or1k_write_spr_reg (PC_SPRNUM, ppc);
 
or1k_unstall ();
 
or1k_set_chain (SC_REGISTER);
val = or1k_read_reg (JTAG_RISCOP);
do {
val = or1k_read_reg (JTAG_RISCOP);
} while ((val & 1) == 0);
}
else if (hit_breakpoint && ((ppc + 4) != npc))
{
/* Trapped on delay slot instruction. */
/* Set PC to branch insn preceding delay slot. */
785,32 → 807,47
val = or1k_read_reg (JTAG_RISCOP);
} while ((val & 1) == 0);
}
else if (next_breakpoint && insn_has_delay_slot (or1k_fetch_instruction (ppc)))
else
or1k_write_spr_reg (PC_SPRNUM, pc);
 
}
else
{
dmr1 &= ~DMR1_ST;
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
 
if (new_pc_set)
{
/* Steping to the trap insn in delay slot - we need to execute branch insn again */
debug ("resume: steping to the trap insn in delay slot\n");
or1k_write_spr_reg (PC_SPRNUM, pc);
new_pc_set = 0;
}
else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc))
or1k_write_spr_reg (PC_SPRNUM, ppc);
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc))
{
or1k_write_mem(ppc, ppc_insn);
 
dmr1 |= DMR1_ST;
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
dmr1 &= ~DMR1_ST;
 
or1k_write_spr_reg (PC_SPRNUM, ppc);
or1k_unstall ();
 
or1k_set_chain (SC_REGISTER);
val = or1k_read_reg (JTAG_RISCOP);
do {
val = or1k_read_reg (JTAG_RISCOP);
} while ((val & 1) == 0);
or1k_write_mem(ppc, 0x21000001);
 
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
}
else if (hit_breakpoint)
else
or1k_write_spr_reg (PC_SPRNUM, pc);
}
else
{
dmr1 &= ~DMR1_ST;
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
if (prev_step_insn_has_delay_slot)
or1k_write_spr_reg (PC_SPRNUM, ppc);
else
or1k_write_spr_reg (PC_SPRNUM, npc);
}
 
/* We can now continue normally, independent of step */
or1k_unstall ();
827,7 → 864,6
{
unsigned long val;
unsigned long pc;
unsigned long npc;
unsigned long ppc;
char buf[MAX_REGISTER_RAW_SIZE];
interrupt_count = 0;
882,9 → 918,8
 
registers_changed ();
pc = read_pc ();
npc = or1k_read_spr_reg (PC_SPRNUM);
ppc = or1k_read_spr_reg (PPC_SPRNUM);
debug ("npc = %08x ppc = %08x\n", npc, ppc);
debug ("ppc = %08x\n", ppc);
 
if (drr & DRR_TE)
{
973,7 → 1008,6
supply_register (PC_REGNUM, buf);
 
hit_breakpoint = breakpoint_here_p (pc);
next_breakpoint = breakpoint_here_p (npc);
/*or1k_write_spr_reg (PC_SPRNUM, pc);
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);

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