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https://opencores.org/ocsvn/phr/phr/trunk
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- from Rev 376 to Rev 377
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Rev 376 → Rev 377
/phr/trunk/doc/eventos/PHRposter SASE14/posterSASE14.pdf
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/phr/trunk/doc/eventos/PHRposter SASE14/latex/images/front-end-raster.png
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phr/trunk/doc/eventos/PHRposter SASE14/latex/images/front-end-raster.png
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Index: phr/trunk/doc/eventos/PHRposter SASE14/latex/poster.tex
===================================================================
--- phr/trunk/doc/eventos/PHRposter SASE14/latex/poster.tex (revision 376)
+++ phr/trunk/doc/eventos/PHRposter SASE14/latex/poster.tex (revision 377)
@@ -27,6 +27,9 @@
\setlength{\parsep}{0pt}%
}
+
+\hyphenation{prin-ci-pian-te e-ner-gí-a re-gu-la-da co-ne-xión}
+
\begin{document}
\begin{poster}{
@@ -69,8 +72,10 @@
{ % poster Authors
\large{\\[0.5ex]
Luis Alberto Guanuco (lguanuco@electronica.frc.utn.edu.ar)\\
- Sergio Daniel Olmedo (solmedo@scdt.frc.utn.edu.ar)\\
- Alexis Maximiliano Quinteros (50214@electronica.frc.utn.edu.ar)}
+ Maximiliano Quinteros (50214@electronica.frc.utn.edu.ar)} \\
+ Sergio Daniel Olmedo (solmedo@scdt.frc.utn.edu.ar)
+
+
}
{ % University logo (top-right logo)
@@ -78,10 +83,13 @@
\begin{tabular}{r}
-\vspace {2cm}\\
+\vspace {1.9cm}\\
- \includegraphics[height=0.04\textheight]{CUDARlogo.pdf}\\
- \includegraphics[height=0.035\textheight]{UTNlogo.pdf}
+ \includegraphics[height=0.030\textheight]{UTNlogo.pdf} \\
+%\vspace {0.5cm} \\
+\\
+ \includegraphics[height=0.035\textheight]{CUDARlogo.pdf}
+
\end{tabular}
}
@@ -148,9 +156,9 @@
\end{center}
La PHR consiste fundamentalmente en tres módulos
-de soporte físico. El módulo principal es la \emph{placa PHR} donde se encuentran el chip FPGA, relojes,
-interfaces de entradas y salidas, periféricos (tales como LEDs, botones, llaves DIP, Displays de siete
-segmentos), etc. Además tiene conectores especiales para otros dos módulos sin los cuales la placa principal carece de funcionalidad.
+de soporte físico. El módulo principal es la \emph{placa PHR} donde se encuentran el chip FPGA, su memoria de configuración, relojes,
+interfaces de entradas/salidas y periféricos tales como LEDs, botones, llaves (DIP) y displays de siete
+segmentos. Los módulos \emph{S3Power} y \emph{OOCDLink} ofrecen alimentación y conectividad con una computadora respectivammente.
@@ -158,8 +166,8 @@
\subsection*{Placa S3Power}
-Fue desarrollada por el \emph{Instituto Nacional de Tecnología Industrial} (INTI) y está disponible libremente. Permite suministrar energía regulada con tres valores de tensión (1.2V, 2.5V y 3.3V) y distintas características de arranque.
-La función la realiza principalmente el chip TPS75003 el cuál incluye un regulador lineal y controladores para dos fuentes conmutadas. %Los voltajes utilizados por la FPGA son de 1.2V, 2.5V y 3.3V.
+Fue desarrollada por el \emph{Instituto Nacional de Tecnología Industrial} (INTI) y está disponible libremente[1]. Permite suministrar energía regulada con tres valores de tensión (1.2V, 2.5V y 3.3V).
+La función la realiza un dispositivo que integra un regulador lineal y controladores para dos fuentes conmutadas. %Los voltajes utilizados por la FPGA son de 1.2V, 2.5V y 3.3V.inci
\begin{center}
\includegraphics[height=0.247\textwidth]{s3power.png}
@@ -173,7 +181,7 @@
\vspace{-0.13cm}
Facilita la comunicación entre una computadora y la placa PHR. Su característica modular, o de circuito separado de la placa PHR principal, hace que su utilización no quede restringida a la FPGA y posibilita la interacción con los multiples dispositivos que soportan JTAG.
-Utiliza el chip FT2232D que establece una interfaz JTAG controlable mediante una conexión USB.
+El dispositivo central controla mediante una conexión USB protocolos de comunicación serial como JTAG, SPI e I2C.
\vspace{-0.55cm}
@@ -191,13 +199,12 @@
\headerbox{Configuración de la FPGA}{name=trece,column=4,below=dos, span=2}{
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{center}
-\includegraphics[width=.9\textwidth]{front-end.pdf}
+\includegraphics[width=.86\textwidth]{front-end-raster.png}
\end{center}
-Para transferir el diseño del usuario a la FPGA, PHR se sirve de las funciones de \textbf{xc3sprog}, un conjunto de aplicaciones de licencia libre que funciona en linea de comandos y que puede programar varios dispositivos mediante JTAG.
-
+Para transferir el diseño del usuario a la FPGA, PHR se sirve de las funciones de \textbf{xc3sprog} [2], un conjunto de aplicaciones de licencia libre que funciona en linea de comandos y que puede programar varios dispositivos mediante JTAG.
No obstante su funcionalidad, xc3sprog puede resultar no intuitivo para el usuario principiante,
-por lo que se ofrece una interfaz gráfica para invocar a xc3sprog de una manera muy simple.
+por lo que se ofrece una interfaz gráfica que permite invocar a xc3sprog de una manera muy simple.
}
@@ -215,6 +222,7 @@
[1] \emph{Módulo de alimentación para placas con dispositivos FPGA}, Christian Huy y Diego
Brengi, \emph{Instituto Nacional de Tecnología Industrial}.
+[2] http://xc3sprog.sourceforge.net
}