URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 378 to Rev 379
- ↔ Reverse comparison
Rev 378 → Rev 379
/trunk/insight/gdb/remote-or1k.c
773,6 → 773,7
|
if (new_pc_set) |
{ |
debug("resume: 1\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
new_pc_set = 0; |
} |
779,6 → 780,7
else if (insn_has_delay_slot (ppc_insn) && (ppc != pc)) |
{ |
/* Steping across delay slot insn - we have to reexcute branch insn */ |
debug("resume: 2\n"); |
|
if(breakpoint_here_p (ppc)) |
or1k_write_mem(ppc, ppc_insn); |
792,9 → 794,12
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
|
new_pc_set = 0; |
} |
else if (hit_breakpoint && ((ppc + 4) != npc)) |
{ |
debug("resume: 3\n"); |
/* Trapped on delay slot instruction. */ |
/* Set PC to branch insn preceding delay slot. */ |
or1k_write_spr_reg (PC_SPRNUM, ppc - 4); |
806,10 → 811,16
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
|
new_pc_set = 0; |
} |
else |
or1k_write_spr_reg (PC_SPRNUM, pc); |
{ |
debug("resume: 4\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
|
new_pc_set = 0; |
} |
} |
else |
{ |
818,13 → 829,21
|
if (new_pc_set) |
{ |
debug("resume: 5\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
|
new_pc_set = 0; |
} |
else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc)) |
{ |
debug("resume: 6\n"); |
or1k_write_spr_reg (PC_SPRNUM, ppc); |
|
new_pc_set = 0; |
} |
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc)) |
{ |
debug("resume: 7\n"); |
or1k_write_mem(ppc, ppc_insn); |
|
dmr1 |= DMR1_ST; |
844,9 → 863,16
or1k_write_mem(ppc, 0x21000001); |
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
|
new_pc_set = 0; |
} |
else |
or1k_write_spr_reg (PC_SPRNUM, pc); |
{ |
debug("resume: 8\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
|
new_pc_set = 0; |
} |
} |
|
/* We can now continue normally, independent of step */ |
/trunk/gdb-5.0/gdb/remote-or1k.c
773,6 → 773,7
|
if (new_pc_set) |
{ |
debug("resume: 1\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
new_pc_set = 0; |
} |
779,6 → 780,7
else if (insn_has_delay_slot (ppc_insn) && (ppc != pc)) |
{ |
/* Steping across delay slot insn - we have to reexcute branch insn */ |
debug("resume: 2\n"); |
|
if(breakpoint_here_p (ppc)) |
or1k_write_mem(ppc, ppc_insn); |
792,9 → 794,12
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
|
new_pc_set = 0; |
} |
else if (hit_breakpoint && ((ppc + 4) != npc)) |
{ |
debug("resume: 3\n"); |
/* Trapped on delay slot instruction. */ |
/* Set PC to branch insn preceding delay slot. */ |
or1k_write_spr_reg (PC_SPRNUM, ppc - 4); |
806,10 → 811,16
do { |
val = or1k_read_reg (JTAG_RISCOP); |
} while ((val & 1) == 0); |
|
new_pc_set = 0; |
} |
else |
or1k_write_spr_reg (PC_SPRNUM, pc); |
{ |
debug("resume: 4\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
|
new_pc_set = 0; |
} |
} |
else |
{ |
818,13 → 829,21
|
if (new_pc_set) |
{ |
debug("resume: 5\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
|
new_pc_set = 0; |
} |
else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc)) |
{ |
debug("resume: 6\n"); |
or1k_write_spr_reg (PC_SPRNUM, ppc); |
|
new_pc_set = 0; |
} |
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc)) |
{ |
debug("resume: 7\n"); |
or1k_write_mem(ppc, ppc_insn); |
|
dmr1 |= DMR1_ST; |
844,9 → 863,16
or1k_write_mem(ppc, 0x21000001); |
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1); |
|
new_pc_set = 0; |
} |
else |
or1k_write_spr_reg (PC_SPRNUM, pc); |
{ |
debug("resume: 8\n"); |
or1k_write_spr_reg (PC_SPRNUM, pc); |
|
new_pc_set = 0; |
} |
} |
|
/* We can now continue normally, independent of step */ |