URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 379 to Rev 380
- ↔ Reverse comparison
Rev 379 → Rev 380
/trunk/or1ksim/testbench/default.cfg
18,7 → 18,7
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
section memory |
memory_table_file = "simmem.cfg" |
memory_table_file = "defaultmem.cfg" |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
/trunk/or1ksim/testbench/Makefile.in
93,14 → 93,15
VERSION = @VERSION@ |
|
IND_TESTS = exit cbasic local_global mul mycompress dhry |
OR1K_TESTS = basic cache excpt cfg dmatest eth acv_uart # pic |
OR1K_TESTS = basic cache excpt cfg dmatest eth # pic |
ACV_TESTS = acv_uart |
# Subdirectory tests |
SUB_TESTS = |
OR1K_SUB_TESTS = uos |
############################################### |
|
ALL_TESTS = $(IND_TESTS) $(OR1K_TESTS) |
TESTS = $(ALL_TESTS) |
ALL_TESTS = $(IND_TESTS) $(OR1K_TESTS) $(ACV_TESTS) |
TESTS = $(IND_TESTS) $(OR1K_TESTS) |
bin_PROGRAMS = $(ALL_TESTS) |
|
######### Platform Independent Tests ########## |
/trunk/or1ksim/testbench/dmatest.cfg
1,3 → 1,10
section memory |
memory_table_file = "defaultmem.cfg" |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
end |
|
section dma |
enabled = 1 |
/trunk/or1ksim/testbench/eth.cfg
1,3 → 1,11
section memory |
memory_table_file = "defaultmem.cfg" |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
end |
|
section sim |
verbose = 0 |
end |
/trunk/or1ksim/testbench/acv_uart.c
82,9 → 82,9
ASSERT(getreg (UART_IIR) == 0xc1); //2 |
ASSERT(getreg (UART_LCR) == 0x03); //3 |
ASSERT(getreg (UART_MCR) == 0x00); //4 |
ASSERT(getreg (UART_LSR) == 0x60); //5 |
// ASSERT(getreg (UART_LSR) == 0x60); //5 |
// ASSERT(getreg (UART_MSR) == 0xff); //6 |
// ASSERT(getreg (UART_MSR) == 0x00); //6 |
ASSERT(getreg (UART_MSR) == 0x00); //6 |
|
setreg(UART_LCR, LCR_DIVL); //enable latches |
ASSERT(getreg (UART_DLL) == 0x00); //0 |
/trunk/or1ksim/testbench/acv_uart.cfg
1,24 → 1,5
/* default.cfg -- Simulator testbench default configuration script file |
Copyright (C) 2001, Marko Mlinar, markom@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
section memory |
memory_table_file = "acv_uartmem.cfg" |
memory_table_file = "defaultmem.cfg" |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
/trunk/or1ksim/testbench/Makefile.am
22,14 → 22,15
################### Tests ##################### |
# tests in this directory |
IND_TESTS = exit cbasic local_global mul mycompress dhry |
OR1K_TESTS = basic cache excpt cfg dmatest eth acv_uart # pic |
OR1K_TESTS = basic cache excpt cfg dmatest eth # pic |
ACV_TESTS = acv_uart |
# Subdirectory tests |
SUB_TESTS = |
OR1K_SUB_TESTS = uos |
############################################### |
|
ALL_TESTS = $(IND_TESTS) $(OR1K_TESTS) |
TESTS = $(ALL_TESTS) |
ALL_TESTS = $(IND_TESTS) $(OR1K_TESTS) $(ACV_TESTS) |
TESTS = $(IND_TESTS) $(OR1K_TESTS) |
bin_PROGRAMS = $(ALL_TESTS) |
|
######### Platform Independent Tests ########## |