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Rev 38 → Rev 39

/trunk/bench/verilog/can_testbench.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.25 2003/02/18 00:19:39 mohor
// Temporary backup version (still fully operable).
//
// Revision 1.24 2003/02/14 20:16:53 mohor
// Several registers added. Not finished, yet.
//
163,6 → 166,7
wire tx_oen;
wire wb_ack_o;
wire irq;
wire clkout;
 
wire tx_3st;
wire rx_and_tx;
192,25 → 196,26
.rx(rx_and_tx),
.tx(tx),
.tx_oen(tx_oen),
.irq(irq)
.irq(irq),
.clkout(clkout)
);
 
assign tx_3st = tx_oen? 1'bz : tx;
 
 
// Generate wishbone clock signal 10 MHz FIX ME
// Generate wishbone clock signal 10 MHz
initial
begin
wb_clk_i=0;
forever #20 wb_clk_i = ~wb_clk_i;
forever #50 wb_clk_i = ~wb_clk_i;
end
 
 
// Generate clock signal 24 MHz FIX ME
// Generate clock signal 24 MHz
initial
begin
clk=0;
forever #20 clk = ~clk;
forever #21 clk = ~clk;
end
 
 
247,7 → 252,7
end
 
//assign rx_and_tx = rx & delayed_tx; FIX ME !!!
assign rx_and_tx = rx & (delayed_tx | tx_bypassed);
assign rx_and_tx = rx & (delayed_tx | tx_bypassed); // When this signal is on, tx is not looped back to the rx.
 
 
// Main testbench
264,7 → 269,7
 
// Set Clock Divider register
extended_mode = 1'b0;
write_register(8'd31, {extended_mode, 7'h0}); // Setting the normal mode (not extended)
write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
 
 
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
293,32 → 298,23
repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
// This difference is resynchronized later.
 
// After exiting the reset mode
repeat (7) send_bit(1); // Sending EOF
repeat (3) send_bit(1); // Sending Interframe
// After exiting the reset mode sending bus free
repeat (11) send_bit(1);
 
// test_synchronization;
 
 
/*
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
begin
// test_empty_fifo_ext; // test currently switched off
test_full_fifo_ext; // test currently switched on
// send_frame_ext; // test currently switched off
end
else
begin
// test_empty_fifo; // test currently switched off
// test_full_fifo; // test currently switched off
send_frame; // test currently switched off
// bus_off_test; // test currently switched off
// manual_frame; // test currently switched off
// forced_bus_off; // test currently switched on
end
*/
self_reception_request;
 
// test_synchronization; // test currently switched off
// test_empty_fifo_ext; // test currently switched off
// test_full_fifo_ext; // test currently switched off
// send_frame_ext; // test currently switched off
// test_empty_fifo; // test currently switched off
// test_full_fifo; // test currently switched off
// send_frame; // test currently switched off
// bus_off_test; // test currently switched off
// forced_bus_off; // test currently switched off
// send_frame_basic; // test currently switched off
// send_frame_extended; // test currently switched off
self_reception_request; // test currently switched on
// manual_frame_basic; // test currently switched off
// manual_frame_ext; // test currently switched off
$display("CAN Testbench finished !");
$stop;
end
359,11 → 355,28
endtask // forced_bus_off
 
 
task manual_frame; // Testbench sends a frame
task manual_frame_basic; // Testbench sends a basic format frame
begin
 
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
 
// Switch-on reset mode
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
// Set Acceptance Code and Acceptance Mask registers
write_register(8'd4, 8'h28); // acceptance code
write_register(8'd5, 8'hff); // acceptance mask
repeat (100) @ (posedge clk);
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
// After exiting the reset mode sending bus free
repeat (11) send_bit(1);
 
 
write_register(8'd10, 8'h55); // Writing ID[10:3] = 0x55
write_register(8'd11, 8'h57); // Writing ID[2:0] = 0x2, rtr = 1, length = 7
write_register(8'd12, 8'h00); // data byte 1
write_register(8'd13, 8'h00); // data byte 2
write_register(8'd14, 8'h00); // data byte 3
373,28 → 386,31
write_register(8'd18, 8'h00); // data byte 7
write_register(8'd19, 8'h00); // data byte 8
 
tx_bypassed = 0; // When this signal is on, tx is not looped back to the rx.
fork
begin
tx_request_command;
// self_reception_request_command;
end
 
begin
#2000;
#2200;
 
repeat (16)
repeat (1)
begin
send_bit(0); // SOF
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // RTR
send_bit(0); // IDE
send_bit(0); // r0
403,173 → 419,177
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC stuff
send_bit(0); // CRC 6
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC DELIM
send_bit(1); // ACK ack error
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // INTER
end // repeat
 
// Node is error passive now.
repeat (20)
begin
send_bit(0); // SOF
send_bit(1); // ID
send_bit(1); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // RTR
send_bit(0); // IDE
send_bit(0); // r0
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(1); // CRC stuff
send_bit(0); // CRC 0
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(1); // CRC 5
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC b
send_bit(1); // CRC DELIM
send_bit(1); // ACK ack error
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(0); // ACK
send_bit(1); // ACK DELIM
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
end // repeat
 
// Node is bus-off now
 
#100000;
end
join
 
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
repeat (128 * 11)
begin
send_bit(1);
end // repeat
 
end
read_receive_buffer;
release_rx_buffer_command;
 
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
 
#4000000;
 
end
endtask // manual_frame_basic
 
 
 
task manual_frame_ext; // Testbench sends an extended format frame
begin
 
 
// Switch-on reset mode
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
 
// Set Clock Divider register
extended_mode = 1'b1;
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
// Set Acceptance Code and Acceptance Mask registers
write_register(8'd16, 8'ha6); // acceptance code 0
write_register(8'd17, 8'h00); // acceptance code 1
write_register(8'd18, 8'h5a); // acceptance code 2
write_register(8'd19, 8'hac); // acceptance code 3
write_register(8'd20, 8'h00); // acceptance mask 0
write_register(8'd21, 8'h00); // acceptance mask 1
write_register(8'd22, 8'h00); // acceptance mask 2
write_register(8'd23, 8'h00); // acceptance mask 3
repeat (100) @ (posedge clk);
join
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
// After exiting the reset mode sending bus free
repeat (11) send_bit(1);
 
 
// Extended frame format
// Writing TX frame information + identifier + data
write_register(8'd16, 8'hc5); // Frame format = 1, Remote transmision request = 1, DLC = 5
write_register(8'd17, 8'ha6); // ID[28:21] = a6
write_register(8'd18, 8'h00); // ID[20:13] = 00
write_register(8'd19, 8'h5a); // ID[12:5] = 5a
write_register(8'd20, 8'ha8); // ID[4:0] = 15
// write_register(8'd21, 8'h78); RTR does not send any data
// write_register(8'd22, 8'h9a);
// write_register(8'd23, 8'hbc);
// write_register(8'd24, 8'hde);
// write_register(8'd25, 8'hf0);
// write_register(8'd26, 8'h0f);
// write_register(8'd27, 8'hed);
// write_register(8'd28, 8'hcb);
 
 
// Enabling IRQ's (extended mode)
write_register(8'd4, 8'hff);
 
// tx_bypassed = 1; // When this signal is on, tx is not looped back to the rx.
fork
begin
tx_request_command;
// self_reception_request_command;
end
 
begin
#1100;
#2400;
 
send_bit(1); // To spend some time before transmitter is ready.
 
repeat (1)
begin
send_bit(0); // SOF
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // ID
send_bit(0); // ID a
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // ID
send_bit(0); // ID 6
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // RTR
send_bit(0); // IDE
send_bit(1); // IDE
send_bit(0); // ID 0
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID 0
send_bit(1); // ID stuff
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID 6
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID a
send_bit(1); // ID 1
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID 5
send_bit(1); // RTR
send_bit(0); // r1
send_bit(0); // r0
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(0); // CRC 4
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC d
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC 3
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC 9
send_bit(1); // CRC DELIM
send_bit(0); // ACK
send_bit(1); // ACK DELIM
584,14 → 604,14
send_bit(1); // INTER
send_bit(1); // INTER
end // repeat
 
 
end
 
join
 
 
 
 
 
read_receive_buffer;
release_rx_buffer_command;
 
599,10 → 619,19
release_rx_buffer_command;
read_receive_buffer;
 
// Read irq register
#1 read_register(8'd3);
 
// Read error code capture register
read_register(8'd12);
 
// Read error capture code register
// read_register(8'd12);
 
#4000000;
 
end
endtask
endtask // manual_frame_ext
 
 
 
876,42 → 905,21
 
 
 
task send_frame; // CAN IP core sends frames
task send_frame_basic; // CAN IP core sends frames
begin
 
if(extended_mode) // Extended mode
begin
write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
write_register(8'd12, 8'h56); // data byte 1
write_register(8'd13, 8'h78); // data byte 2
write_register(8'd14, 8'h9a); // data byte 3
write_register(8'd15, 8'hbc); // data byte 4
write_register(8'd16, 8'hde); // data byte 5
write_register(8'd17, 8'hf0); // data byte 6
write_register(8'd18, 8'h0f); // data byte 7
write_register(8'd19, 8'hed); // data byte 8
 
// Writing TX frame information + identifier + data
write_register(8'd16, 8'h12);
write_register(8'd17, 8'h34);
write_register(8'd18, 8'h56);
write_register(8'd19, 8'h78);
write_register(8'd20, 8'h9a);
write_register(8'd21, 8'hbc);
write_register(8'd22, 8'hde);
write_register(8'd23, 8'hf0);
write_register(8'd24, 8'h0f);
write_register(8'd25, 8'hed);
write_register(8'd26, 8'hcb);
write_register(8'd27, 8'ha9);
write_register(8'd28, 8'h87);
end
else
begin
write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
write_register(8'd12, 8'h56); // data byte 1
write_register(8'd13, 8'h78); // data byte 2
write_register(8'd14, 8'h9a); // data byte 3
write_register(8'd15, 8'hbc); // data byte 4
write_register(8'd16, 8'hde); // data byte 5
write_register(8'd17, 8'hf0); // data byte 6
write_register(8'd18, 8'h0f); // data byte 7
write_register(8'd19, 8'hed); // data byte 8
end
 
 
// Enable irqs (basic mode)
write_register(8'd0, 8'h1e);
 
918,7 → 926,9
 
fork
 
begin
#2500;
$display("\n\nStart receiving data from CAN bus");
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
925,10 → 935,134
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
end
 
begin
tx_request_command;
end
 
begin
// Transmitting acknowledge
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
#1 rx = 0;
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
#1 rx = 1;
end
 
 
join
 
read_receive_buffer;
release_rx_buffer_command;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
 
#200000;
 
read_receive_buffer;
 
// Read irq register
read_register(8'd3);
#1000;
 
end
endtask // send_frame_basic
 
 
 
task send_frame_extended; // CAN IP core sends basic or extended frames in extended mode
begin
 
// Switch-on reset mode
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
// Set Clock Divider register
extended_mode = 1'b1;
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
// Set Acceptance Code and Acceptance Mask registers
write_register(8'd16, 8'ha6); // acceptance code 0
write_register(8'd17, 8'hb0); // acceptance code 1
write_register(8'd18, 8'h12); // acceptance code 2
write_register(8'd19, 8'h30); // acceptance code 3
write_register(8'd20, 8'h00); // acceptance mask 0
write_register(8'd21, 8'h00); // acceptance mask 1
write_register(8'd22, 8'h00); // acceptance mask 2
write_register(8'd23, 8'h00); // acceptance mask 3
 
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
// After exiting the reset mode sending bus free
repeat (11) send_bit(1);
 
 
/* Basic frame format
// Writing TX frame information + identifier + data
write_register(8'd16, 8'h45); // Frame format = 0, Remote transmision request = 1, DLC = 5
write_register(8'd17, 8'ha6); // ID[28:21] = a6
write_register(8'd18, 8'ha0); // ID[20:18] = 5
// write_register(8'd19, 8'h78); RTR does not send any data
// write_register(8'd20, 8'h9a);
// write_register(8'd21, 8'hbc);
// write_register(8'd22, 8'hde);
// write_register(8'd23, 8'hf0);
// write_register(8'd24, 8'h0f);
// write_register(8'd25, 8'hed);
// write_register(8'd26, 8'hcb);
// write_register(8'd27, 8'ha9);
// write_register(8'd28, 8'h87);
*/
 
// Extended frame format
// Writing TX frame information + identifier + data
write_register(8'd16, 8'hc5); // Frame format = 1, Remote transmision request = 1, DLC = 5
write_register(8'd17, 8'ha6); // ID[28:21] = a6
write_register(8'd18, 8'h00); // ID[20:13] = 00
write_register(8'd19, 8'h5a); // ID[12:5] = 5a
write_register(8'd20, 8'ha8); // ID[4:0] = 15
// write_register(8'd21, 8'h78); RTR does not send any data
// write_register(8'd22, 8'h9a);
// write_register(8'd23, 8'hbc);
// write_register(8'd24, 8'hde);
// write_register(8'd25, 8'hf0);
// write_register(8'd26, 8'h0f);
// write_register(8'd27, 8'hed);
// write_register(8'd28, 8'hcb);
 
 
// Enabling IRQ's (extended mode)
write_register(8'd4, 8'hff);
 
 
fork
begin
#2700;
$display("\n\nStart receiving data from CAN bus");
/* Standard frame format
receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h1, 15'h2d9c); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h2, 15'h46b4); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h0, 15'h42cd); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h1, 15'h555f); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h2, 15'h6742); // mode, rtr, id, length, crc
*/
 
// Extended frame format
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h0, 15'h23aa); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
 
end
 
begin
tx_request_command;
end
 
940,7 → 1074,47
#1 rx = 1;
end
 
begin // Reading irq and arbitration lost capture register
 
repeat(1)
begin
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
begin
@ (posedge clk);
end
 
// Read irq register
#1 read_register(8'd3);
// Read arbitration lost capture register
read_register(8'd11);
end
 
 
repeat(1)
begin
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
begin
@ (posedge clk);
end
 
// Read irq register
#1 read_register(8'd3);
end
 
repeat(1)
begin
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
begin
@ (posedge clk);
end
 
// Read arbitration lost capture register
read_register(8'd11);
end
 
end
 
join
 
read_receive_buffer;
963,7 → 1137,7
#1000;
 
end
endtask // send_frame
endtask // send_frame_extended
 
 
 
1016,7 → 1190,6
// Enabling IRQ's (extended mode)
write_register(8'd4, 8'hff);
 
// tx_request_command;
self_reception_request_command;
 
#400000;
1738,6 → 1911,14
$display("*E (%0t) ERROR: acknowledge_error", $time);
end
 
/*
// bit error monitor
always @ (posedge clk)
begin
if (can_testbench.i_can_top.i_can_bsp.bit_err)
$display("*E (%0t) ERROR: bit_error", $time);
end
*/
 
endmodule
 
/trunk/rtl/verilog/can_top.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2003/02/18 00:10:15 mohor
// Most of the registers added. Registers "arbitration lost capture", "error code
// capture" + few more still need to be added.
//
// Revision 1.16 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
127,6 → 131,7
tx,
tx_oen,
irq,
clkout
);
 
parameter Tp = 1;
145,6 → 150,7
output tx;
output tx_oen;
output irq;
output clkout;
 
reg [7:0] wb_dat_o;
reg wb_ack_o;
153,8 → 159,6
reg cs_sync1;
reg cs_sync2;
reg cs_sync3;
reg cs_sync_rst1;
reg cs_sync_rst2;
 
reg cs_ack1;
reg cs_ack2;
177,6 → 181,13
wire self_rx_request;
wire single_shot_transmission;
 
/* Arbitration Lost Capture Register */
wire read_arbitration_lost_capture_reg;
 
/* Error Code Capture Register */
wire read_error_code_capture_reg;
wire [7:0] error_capture_code;
 
/* Bus Timing 0 register */
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
197,9 → 208,6
 
/* Clock Divider register */
wire extended_mode;
wire rx_int_enable;
wire clock_off;
wire [2:0] cd;
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
267,10 → 275,12
wire need_to_tx;
wire overrun;
wire info_empty;
wire go_error_frame;
wire priority_lost;
wire set_bus_error_irq;
wire set_arbitration_lost_irq;
wire [4:0] arbitration_lost_capture;
wire node_error_passive;
wire node_error_active;
wire [6:0] rx_message_counter;
 
 
 
300,10 → 310,12
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.go_error_frame(go_error_frame),
.priority_lost(priority_lost),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
 
 
/* Mode register */
320,6 → 332,13
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
 
/* Arbitration Lost Capture Register */
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
 
/* Error Code Capture Register */
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
 
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
340,9 → 359,7
 
/* Clock Divider register */
.extended_mode(extended_mode),
.rx_int_enable(rx_int_enable),
.clock_off(clock_off),
.cd(cd),
.clkout(clkout),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
460,7 → 477,13
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
 
/* Arbitration Lost Capture Register */
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
 
/* Error Code Capture Register */
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
 
/* Error Warning Limit register */
.error_warning_limit(error_warning_limit),
 
488,10 → 511,12
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.go_error_frame(go_error_frame),
.priority_lost(priority_lost),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
558,75 → 583,26
 
 
 
// FIX ME !!! This wishbone interface is not OK, yet.
// Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk clock domain.
always @ (posedge clk)
begin
if (cs_ack2)
begin
cs_sync1 <=#Tp 1'b0;
cs_sync2 <=#Tp 1'b0;
cs_sync3 <=#Tp 1'b0;
end
else
begin
cs_sync1 <=#Tp (wb_cyc_i & wb_stb_i);
cs_sync2 <=#Tp cs_sync1;
cs_sync3 <=#Tp cs_sync2;
end
end
 
 
assign cs = cs_sync2 & (~cs_sync3);
 
 
always @ (posedge wb_clk_i)
begin
if (wb_ack_o)
begin
cs_ack1 <=#Tp 1'b0;
cs_ack2 <=#Tp 1'b0;
cs_ack3 <=#Tp 1'b0;
end
else
begin
cs_ack1 <=#Tp cs_sync2;
cs_ack2 <=#Tp cs_ack1;
cs_ack3 <=#Tp cs_ack2;
end
end
 
 
 
// Generating acknowledge signal
always @ (posedge wb_clk_i)
begin
wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
end
 
 
 
 
 
/*
// Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk clock domain.
reg rst_blocked_ack;
reg cs_sync_rst1;
reg cs_sync_rst2;
 
always @ (posedge clk)
always @ (posedge clk or posedge wb_rst_i)
begin
if (cs_sync_rst2 & ({~rst_blocked_ack} ))
if (wb_rst_i)
begin
cs_sync1 <=#Tp 1'b0;
cs_sync2 <=#Tp 1'b0;
cs_sync3 <=#Tp 1'b0;
cs_sync_rst1 <=#Tp 1'b0;
cs_sync_rst2 <=#Tp 1'b0;
cs_sync1 <=# 1'b0;
cs_sync2 <=# 1'b0;
cs_sync3 <=# 1'b0;
cs_sync_rst1 <=# 1'b0;
cs_sync_rst2 <=# 1'b0;
end
else
begin
cs_sync1 <=#Tp (wb_cyc_i & wb_stb_i);
cs_sync2 <=#Tp cs_sync1;
cs_sync3 <=#Tp cs_sync2;
cs_sync1 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2);
cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2);
cs_sync3 <=#Tp cs_sync2 & (~cs_sync_rst2);
cs_sync_rst1 <=#Tp cs_ack3;
cs_sync_rst2 <=#Tp cs_sync_rst1;
end
633,7 → 609,6
end
 
 
 
assign cs = cs_sync2 & (~cs_sync3);
 
 
653,15 → 628,4
end
 
 
always @ (posedge wb_clk_i)
begin
if (cs_ack3)
rst_blocked_ack <=#Tp 1'b0;
else if (cs_ack1)
rst_blocked_ack <=#Tp 1'b1;
end
*/
 
 
 
endmodule
/trunk/rtl/verilog/can_fifo.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10 2003/02/11 00:56:06 mohor
// Wishbone interface added.
//
108,7 → 111,8
release_buffer,
extended_mode,
overrun,
info_empty
info_empty,
info_cnt
 
);
 
126,6 → 130,7
output [7:0] data_out;
output overrun;
output info_empty;
output [6:0] info_cnt;
 
 
reg [7:0] fifo [0:63];
/trunk/rtl/verilog/can_bsp.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.24 2003/02/18 00:10:15 mohor
// Most of the registers added. Registers "arbitration lost capture", "error code
// capture" + few more still need to be added.
//
// Revision 1.23 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
166,6 → 170,13
self_rx_request,
single_shot_transmission,
 
/* Arbitration Lost Capture Register */
read_arbitration_lost_capture_reg,
 
/* Error Code Capture Register */
read_error_code_capture_reg,
error_capture_code,
 
/* Error Warning Limit register */
error_warning_limit,
 
192,10 → 203,12
need_to_tx,
overrun,
info_empty,
go_error_frame,
priority_lost,
set_bus_error_irq,
set_arbitration_lost_irq,
arbitration_lost_capture,
node_error_passive,
node_error_active,
rx_message_counter,
 
 
 
269,6 → 282,13
input self_rx_request;
input single_shot_transmission;
 
/* Arbitration Lost Capture Register */
input read_arbitration_lost_capture_reg;
 
/* Error Code Capture Register */
input read_error_code_capture_reg;
output [7:0] error_capture_code;
 
/* Error Warning Limit register */
input [7:0] error_warning_limit;
 
292,10 → 312,12
output need_to_tx;
output overrun;
output info_empty;
output go_error_frame;
output priority_lost;
output set_bus_error_irq;
output set_arbitration_lost_irq;
output [4:0] arbitration_lost_capture;
output node_error_passive;
output node_error_active;
output [6:0] rx_message_counter;
 
 
/* This section is for BASIC and EXTENDED mode */
398,7 → 420,11
reg tx;
reg crc_err;
 
reg priority_lost;
reg arbitration_lost;
reg arbitration_lost_q;
reg [4:0] arbitration_lost_capture;
reg arbitration_cnt_en;
reg arbitration_blocked;
reg tx_q;
 
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
438,6 → 464,13
reg go_error_frame_q;
reg error_flag_over_blocked;
 
reg [7:0] error_capture_code;
reg [7:6] error_capture_code_type;
reg error_capture_code_blocked;
 
wire [4:0] error_capture_code_segment;
wire error_capture_code_direction;
 
wire bit_de_stuff;
wire bit_de_stuff_tx;
 
460,6 → 493,7
wire go_rx_eof;
wire go_overload_frame;
wire go_rx_inter;
wire go_error_frame;
 
wire go_crc_enable;
wire rst_crc_enable;
569,7 → 603,7
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
 
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
assign bit_err_exc1 = tx_state & arbitration_field & tx;
assign bit_err_exc2 = rx_ack & tx;
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
1291,9 → 1325,8
.release_buffer(release_buffer),
.extended_mode(extended_mode),
.overrun(overrun),
.info_empty(info_empty)
 
.info_empty(info_empty),
.info_cnt(rx_message_counter)
);
 
 
1594,7 → 1627,7
end
 
 
assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~priority_lost) | single_shot_transmission);
assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
 
 
always @ (posedge clk or posedge rst)
1618,7 → 1651,7
begin
if (rst)
tx_state <= 1'b0;
else if (reset_mode | go_rx_inter | error_frame | priority_lost)
else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
tx_state <=#Tp 1'b0;
else if (go_tx)
tx_state <=#Tp 1'b1;
1647,7 → 1680,7
transmitting <= 1'b0;
else if (go_error_frame | go_overload_frame | go_tx)
transmitting <=#Tp 1'b1;
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (priority_lost & tx_state))
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
transmitting <=#Tp 1'b0;
end
 
1701,18 → 1734,61
always @ (posedge clk or posedge rst)
begin
if (rst)
priority_lost <= 1'b0;
arbitration_lost <= 1'b0;
else if (go_rx_idle | error_frame | reset_mode)
priority_lost <=#Tp 1'b0;
arbitration_lost <=#Tp 1'b0;
else if (tx_state & sample_point & tx & arbitration_field)
priority_lost <=#Tp (~sampled_bit);
arbitration_lost <=#Tp (~sampled_bit);
end
 
 
always @ (posedge clk)
begin
arbitration_lost_q <=#Tp arbitration_lost;
end
 
 
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_cnt_en <= 1'b0;
else if (arbitration_blocked)
arbitration_cnt_en <=#Tp 1'b0;
else if (rx_id1 & sample_point & (~arbitration_blocked))
arbitration_cnt_en <=#Tp 1'b1;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_blocked <= 1'b0;
else if (read_arbitration_lost_capture_reg)
arbitration_blocked <=#Tp 1'b0;
else if (set_arbitration_lost_irq)
arbitration_blocked <=#Tp 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_lost_capture <= 5'h0;
else if (read_arbitration_lost_capture_reg)
arbitration_lost_capture <=#Tp 5'h0;
else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
rx_err_cnt <= 'h0;
else if (we_rx_err_cnt & (~node_bus_off))
rx_err_cnt <=#Tp {1'b0, data_in};
1865,4 → 1941,53
assign transmit_status = transmitting | (extended_mode & waiting_for_bus_free);
assign receive_status = (~rx_idle) & (~transmitting) | (extended_mode & waiting_for_bus_free);
 
 
/* Error code capture register */
always @ (posedge clk or posedge rst)
begin
if (rst)
error_capture_code <= 8'h0;
else if (read_error_code_capture_reg)
error_capture_code <=#Tp 8'h0;
else if (set_bus_error_irq)
error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
end
 
 
 
assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
assign error_capture_code_direction = ~transmitting;
 
 
always @ (bit_err or form_err or stuff_err)
begin
if (bit_err)
error_capture_code_type[7:6] <= 2'b00;
else if (form_err)
error_capture_code_type[7:6] <= 2'b01;
else if (stuff_err)
error_capture_code_type[7:6] <= 2'b10;
else
error_capture_code_type[7:6] <= 2'b11;
end
 
 
assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
error_capture_code_blocked <= 1'b0;
else if (read_error_code_capture_reg)
error_capture_code_blocked <=#Tp 1'b0;
else if (set_bus_error_irq)
error_capture_code_blocked <=#Tp 1'b1;
end
 
 
endmodule
/trunk/rtl/verilog/can_registers.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15 2003/02/18 00:10:15 mohor
// Most of the registers added. Registers "arbitration lost capture", "error code
// capture" + few more still need to be added.
//
// Revision 1.14 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
128,10 → 132,12
need_to_tx,
overrun,
info_empty,
go_error_frame,
priority_lost,
set_bus_error_irq,
set_arbitration_lost_irq,
arbitration_lost_capture,
node_error_passive,
node_error_active,
rx_message_counter,
 
 
/* Mode register */
149,6 → 155,13
self_rx_request,
single_shot_transmission,
 
/* Arbitration Lost Capture Register */
read_arbitration_lost_capture_reg,
 
/* Error Code Capture Register */
read_error_code_capture_reg,
error_capture_code,
 
/* Bus Timing 0 register */
baud_r_presc,
sync_jump_width,
169,9 → 182,7
 
/* Clock Divider register */
extended_mode,
rx_int_enable,
clock_off,
cd,
clkout,
/* This section is for BASIC and EXTENDED mode */
242,10 → 253,12
input need_to_tx;
input overrun;
input info_empty;
input go_error_frame;
input priority_lost;
input set_bus_error_irq;
input set_arbitration_lost_irq;
input [4:0] arbitration_lost_capture;
input node_error_passive;
input node_error_active;
input [6:0] rx_message_counter;
 
 
 
263,6 → 276,13
output self_rx_request;
output single_shot_transmission;
 
/* Arbitration Lost Capture Register */
output read_arbitration_lost_capture_reg;
 
/* Error Code Capture Register */
output read_error_code_capture_reg;
input [7:0] error_capture_code;
 
/* Bus Timing 0 register */
output [5:0] baud_r_presc;
output [1:0] sync_jump_width;
284,9 → 304,7
 
/* Clock Divider register */
output extended_mode;
output rx_int_enable;
output clock_off;
output [2:0] cd;
output clkout;
 
 
/* This section is for BASIC and EXTENDED mode */
338,7 → 356,6
reg info_empty_q;
reg error_status_q;
reg node_bus_off_q;
reg priority_lost_q;
reg node_error_passive_q;
reg transmit_buffer_status;
reg single_shot_transmission;
364,8 → 381,9
 
wire read = cs & (~we);
wire read_irq_reg = read & (addr == 8'd3);
assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 8'd11);
assign read_error_code_capture_reg = read & extended_mode & (addr == 8'd12);
 
 
/* This section is for BASIC and EXTENDED mode */
wire we_acceptance_code_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
wire we_acceptance_mask_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
408,7 → 426,6
info_empty_q <=#Tp info_empty;
error_status_q <=#Tp error_status;
node_bus_off_q <=#Tp node_bus_off;
priority_lost_q <=#Tp priority_lost;
node_error_passive_q <=#Tp node_error_passive;
end
 
652,13 → 669,29
 
/* Clock Divider register */
wire [7:0] clock_divider;
can_register #(5) CLOCK_DIVIDER_REG_HI
( .data_in(data_in[7:3]),
.data_out(clock_divider[7:3]),
wire clock_off;
wire [2:0] cd;
reg [2:0] clkout_div;
reg [2:0] clkout_cnt;
reg clkout_tmp;
reg clkout;
 
can_register #(1) CLOCK_DIVIDER_REG_7
( .data_in(data_in[7]),
.data_out(clock_divider[7]),
.we(we_clock_divider_hi),
.clk(clk)
);
 
assign clock_divider[6:4] = 3'h0;
 
can_register #(1) CLOCK_DIVIDER_REG_3
( .data_in(data_in[3]),
.data_out(clock_divider[3]),
.we(we_clock_divider_hi),
.clk(clk)
);
 
can_register #(3) CLOCK_DIVIDER_REG_LOW
( .data_in(data_in[2:0]),
.data_out(clock_divider[2:0]),
667,10 → 700,60
);
 
assign extended_mode = clock_divider[7];
assign rx_int_enable = clock_divider[5];
assign clock_off = clock_divider[3];
assign cd[2:0] = clock_divider[2:0];
assign clock_off = clock_divider[3];
assign cd[2:0] = clock_divider[2:0];
 
 
 
always @ (cd)
begin
case (cd) // synopsys_full_case synopsys_paralel_case
3'b000 : clkout_div <= 0;
3'b001 : clkout_div <= 1;
3'b010 : clkout_div <= 2;
3'b011 : clkout_div <= 3;
3'b100 : clkout_div <= 4;
3'b101 : clkout_div <= 5;
3'b110 : clkout_div <= 6;
3'b111 : clkout_div <= 0;
endcase
end
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
clkout_cnt <= 3'h0;
else if (clkout_cnt == clkout_div)
clkout_cnt <=#Tp 3'h0;
else
clkout_cnt <= clkout_cnt + 1'b1;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
clkout_tmp <= 1'b0;
else if (clkout_cnt == clkout_div)
clkout_tmp <=#Tp ~clkout_tmp;
end
 
 
 
always @ (cd or clk or clkout_tmp)
begin
if (clock_off)
clkout <=#Tp 1'b1;
else if (&cd)
clkout <=#Tp clk;
else
clkout <=#Tp clkout_tmp;
end
 
 
/* End Clock Divider register */
 
 
911,7 → 994,8
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
arbitration_lost_capture or rx_message_counter or mode_basic
)
begin
if(read) // read
926,6 → 1010,8
8'd4 : data_out <= irq_en_ext;
8'd6 : data_out <= bus_timing_0;
8'd7 : data_out <= bus_timing_1;
8'd11 : data_out <= {3'h0, arbitration_lost_capture[4:0]};
8'd12 : data_out <= error_capture_code;
8'd13 : data_out <= error_warning_limit;
8'd14 : data_out <= rx_err_cnt;
8'd15 : data_out <= tx_err_cnt;
942,9 → 1028,9
8'd26 : data_out <= 8'h0;
8'd27 : data_out <= 8'h0;
8'd28 : data_out <= 8'h0;
8'd29 : data_out <= {1'b0, rx_message_counter};
8'd31 : data_out <= clock_divider;
8'd31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]};
default: data_out <= 8'h0;
endcase
end
969,7 → 1055,7
8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
8'd31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]};
8'd31 : data_out <= clock_divider;
default: data_out <= 8'h0;
endcase
1040,7 → 1126,7
begin
if (rst)
bus_error_irq <= 1'b0;
else if (go_error_frame & bus_error_irq_en)
else if (set_bus_error_irq & bus_error_irq_en)
bus_error_irq <=#Tp 1'b1;
else if (read_irq_reg)
bus_error_irq <=#Tp 1'b0;
1052,7 → 1138,7
begin
if (rst)
arbitration_lost_irq <= 1'b0;
else if (priority_lost & (~priority_lost_q) & arbitration_lost_irq_en)
else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
arbitration_lost_irq <=#Tp 1'b1;
else if (read_irq_reg)
arbitration_lost_irq <=#Tp 1'b0;
1073,10 → 1159,8
 
 
 
// FIX ME !!!
assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};
 
// FIX ME !!!
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;
 
 

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