URL
https://opencores.org/ocsvn/pltbutils/pltbutils/trunk
Subversion Repositories pltbutils
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- This comparison shows the changes necessary to convert path
/
- from Rev 38 to Rev 39
- ↔ Reverse comparison
Rev 38 → Rev 39
/pltbutils/trunk/example/vhdl/tb_example.vhd
22,7 → 22,7
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- |
---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
48,8 → 48,6
---------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use std.textio.all; |
use work.txt_util.all; |
use work.pltbutils_func_pkg.all; |
use work.pltbutils_comp_pkg.all; |
|
64,17 → 62,8
architecture bhv of tb_example is |
|
-- Simulation status- and control signals |
signal test_num : integer; |
-- VHDL-1993: |
--signal test_name : string(pltbutils_test_name'range); |
--signal info : string(pltbutils_info'range); |
-- VHDL-2002: |
signal test_name : string(pltbutils_sc.test_name'range); |
signal info : string(pltbutils_sc.info'range); |
|
signal checks : integer; |
signal errors : integer; |
signal stop_sim : std_logic; |
-- for accessing .stop_sim and for viewing in waveform window |
signal pltbs : pltbs_t := C_PLTBS_INIT; |
|
-- DUT stimuli and response signals |
signal clk : std_logic; |
86,22 → 75,7
signal carry_out : std_logic; |
|
begin |
|
-- Simulation status and control for viewing in waveform window |
-- VHDL-1993: |
--test_num <= pltbutils_test_num; |
--test_name <= pltbutils_test_name; |
--checks <= pltbutils_chk_cnt; |
--errors <= pltbutils_err_cnt; |
-- VHDL-2002: |
test_num <= pltbutils_sc.test_num; |
test_name <= pltbutils_sc.test_name; |
info <= pltbutils_sc.info; |
checks <= pltbutils_sc.chk_cnt; |
errors <= pltbutils_sc.err_cnt; |
stop_sim <= pltbutils_sc.stop_sim; |
|
|
dut0 : entity work.dut_example |
generic map ( |
G_WIDTH => G_WIDTH, |
123,7 → 97,7
) |
port map( |
clk_o => clk, |
stop_sim_i => stop_sim |
stop_sim_i => pltbs.stop_sim |
); |
|
tc0 : entity work.tc_example |
132,6 → 106,7
G_DISABLE_BUGS => G_DISABLE_BUGS |
) |
port map( |
pltbs => pltbs, |
clk => clk, |
rst => rst, |
carry_in => carry_in, |