URL
https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk
Subversion Repositories simple_fm_receiver
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 38 to Rev 39
- ↔ Reverse comparison
Rev 38 → Rev 39
/simple_fm_receiver/trunk/source/adder_09bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 09 bit with output 10 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/rom.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : COS ROM (1024 = 2^10 = 10 bit maps) |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/fm.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : FM core component to connect all other component |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_16bit_u.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 16 bit with output 16 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/loop_filter.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : loop filter in PLL loop |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_10bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 10 bit with output 11 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_11bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 11 bit with output 12 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_12bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 12 bit with output 13 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/fir.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : FIR low pass filter |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_13bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 13 bit with output 14 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_14bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 14 bit with output 15 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_15bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 15 bit with output 16 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_16bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 16 bit with output 17 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/adder_18bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Ripple carry adder 18 bit with output 18 bit |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/phase_detector.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : multiply input signal with signal nco |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/sub_12bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Subtractor 12 bit used in loop filter |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/addacc.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Accumulator used in NCO of PLL in FM Receiver |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/fulladder.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Simple one bit adder with carry |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/simple_fm_receiver/trunk/source/mult_8bit.vhdl
13,10 → 13,7
------------------------------------------------------------------------------- |
-- Description : Multiplier used in phase detector |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif Endro Nugroho |
-------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
/simple_fm_receiver/trunk/source/nco.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Works like VCO in analog PLL |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |