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/phr/trunk/codigo/implementaciones/adc/pmod/sevseg_display.vhd
0,0 → 1,94
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
 
 
entity sevseg_display is
Port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (15 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0);
char_sel : out STD_LOGIC_VECTOR (3 downto 0));
end sevseg_display;
 
architecture Behavioral of sevseg_display is
signal count : unsigned (1 downto 0);
signal char : std_logic_vector (3 downto 0);
begin
 
counter: process (clock, reset)
variable count_var : unsigned (1 downto 0) := "00";
begin
if reset='1' then
count_var := (others => '0');
elsif falling_edge(clock) then
count_var := count + 1;
end if;
count <= count_var;
end process;
 
char_selector: process (clock, count)
begin
if rising_edge(clock) then
case count is
when "00" => char_sel <= "1110";
when "01" => char_sel <= "1101";
when "10" => char_sel <= "1011";
when "11" => char_sel <= "0111";
when others => char_sel <= "1111";
end case;
end if;
end process;
 
data_selector: process (clock, count)
begin
if rising_edge (clock) then
case count is
when "00" => char <= data(3 downto 0);
when "01" => char <= data(7 downto 4);
when "10" => char <= data(11 downto 8);
when "11" => char <= data(15 downto 12);
when others => char <= "0000";
end case;
end if;
end process;
 
 
bin2seven: process (char, reset)
variable segments_var : STD_LOGIC_VECTOR (6 downto 0);
begin
 
if reset = '1' then
segments_var := "1111111";
else
case char is
when "0000" => segments_var := "0000001"; -- 0
when "0001" => segments_var := "1001111"; -- 1
when "0010" => segments_var := "0010010"; -- 2
when "0011" => segments_var := "0000110"; -- 3
when "0100" => segments_var := "1001100"; -- 4
when "0101" => segments_var := "0100100"; -- 5
when "0110" => segments_var := "0100000"; -- 6
when "0111" => segments_var := "0001111"; -- 7
when "1000" => segments_var := "0000000"; -- 8
when "1001" => segments_var := "0000100"; -- 9
when "1010" => segments_var := "0001000"; -- a
when "1011" => segments_var := "1100000"; -- b
when "1100" => segments_var := "0110001"; -- c
when "1101" => segments_var := "1000010"; -- d
when "1110" => segments_var := "0110000"; -- e
when "1111" => segments_var := "0111000"; -- f
when others => segments_var := "1111110";
end case;
end if;
segments <= segments_var;
end process;
 
 
end Behavioral;
 
/phr/trunk/codigo/implementaciones/adc/pmod/displayPmod.vhd
0,0 → 1,96
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
 
entity displayPmod is
Port (
clock : in STD_LOGIC;
slow_clock : in STD_LOGIC;
reset : in STD_LOGIC;
convert_button : in std_logic;
pmod_sdata1 : in std_logic;
pmod_sdata2 : in std_logic;
pmod_sclk : out std_logic;
pmod_ncs : out std_logic;
display_char : out STD_LOGIC_VECTOR (3 downto 0);
display_seg : out STD_LOGIC_VECTOR (6 downto 0));
end displayPmod;
 
architecture Behavioral of displayPmod is
 
COMPONENT AD1RefComp
PORT(
CLK : IN std_logic;
RST : IN std_logic;
SDATA1 : IN std_logic;
SDATA2 : IN std_logic;
START : IN std_logic;
SCLK : OUT std_logic;
nCS : OUT std_logic;
DATA1 : OUT std_logic_vector(11 downto 0);
DATA2 : OUT std_logic_vector(11 downto 0);
DONE : OUT std_logic
);
END COMPONENT;
COMPONENT sevseg_display
PORT(
clock : IN std_logic;
reset : IN std_logic;
data : IN std_logic_vector(15 downto 0);
segments : OUT std_logic_vector(6 downto 0);
char_sel : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal data1 : std_logic_vector (15 downto 0) := (others => '0');
signal data2 : std_logic_vector (15 downto 0) := (others => '0');
signal done : std_logic;
signal Sstart_conv : std_logic_vector (9 downto 0) := (others => '0');
begin
 
Inst_AD1RefComp: AD1RefComp PORT MAP(
CLK => clock,
RST => reset,
SDATA1 => pmod_sdata1,
SDATA2 => pmod_sdata2,
SCLK => pmod_sclk,
nCS => pmod_ncs,
DATA1 => data1 (11 downto 0),
DATA2 => data2 (11 downto 0),
--START => convert_button,
START => Sstart_conv(9),
DONE => done
);
process(clock)
begin
if(falling_edge(clock)) then
Sstart_conv <= Sstart_conv(8 downto 0) & done;
end if;
end process;
data1(15 downto 12) <= "0000";
 
 
Inst_sevseg_display: sevseg_display PORT MAP(
clock => slow_clock,
reset => reset,
data => data1,
--data => "0000000000011111",
segments => display_seg (6 downto 0),
char_sel => display_char (3 downto 0)
);
 
end Behavioral;
 
/phr/trunk/codigo/implementaciones/adc/pmod/displayPmod_pad.txt
0,0 → 1,130
Release 14.2 - par P.28xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
 
Fri Aug 22 20:43:09 2014
 
 
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
 
INPUT FILE: displayPmod_map.ncd
OUTPUT FILE: displayPmod_pad.txt
PART TYPE: xc3s200a
SPEED GRADE: -4
PACKAGE: vq100
 
Pinout by Pin Number:
 
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name |Pin Usage |Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|P1 | | |TMS | | | | | | | | | | | |
|P2 | | |TDI | | | | | | | | | | | |
|P3 | |DIFFMLR |IO_L01P_3 |UNUSED | |3 | | | | | | | | |
|P4 | |DIFFSLR |IO_L01N_3 |UNUSED | |3 | | | | | | | | |
|P5 | |DIFFMLR |IO_L02P_3 |UNUSED | |3 | | | | | | | | |
|P6 | |DIFFSLR |IO_L02N_3 |UNUSED | |3 | | | | | | | | |
|P7 | |DIFFSI_NDT|IP_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|P8 | | |GND | | | | | | | | | | | |
|P9 | |DIFFMLR |IO_L03P_3/LHCLK0 |UNUSED | |3 | | | | | | | | |
|P10 | |DIFFSLR |IO_L03N_3/LHCLK1 |UNUSED | |3 | | | | | | | | |
|P11 | | |VCCO_3 | | |3 | | | | |any******| | | |
|P12 | |DIFFMLR |IO_L04P_3/LHCLK2 |UNUSED | |3 | | | | | | | | |
|P13 | |DIFFSLR |IO_L04N_3/IRDY2/LHCLK3|UNUSED | |3 | | | | | | | | |
|P14 | | |GND | | | | | | | | | | | |
|P15 | |DIFFMLR |IO_L05P_3/TRDY2/LHCLK6|UNUSED | |3 | | | | | | | | |
|P16 | |DIFFSLR |IO_L05N_3/LHCLK7 |UNUSED | |3 | | | | | | | | |
|P17 | | |VCCINT | | | | | | | |1.2 | | | |
|P18 | | |GND | | | | | | | | | | | |
|P19 | |DIFFMLR |IO_L06P_3 |UNUSED | |3 | | | | | | | | |
|P20 | |DIFFSLR |IO_L06N_3 |UNUSED | |3 | | | | | | | | |
|P21 | |DIFFMI_NDT|IP_3 |UNUSED | |3 | | | | | | | | |
|P22 | | |VCCAUX | | | | | | | |2.5 | | | |
|P23 | |DIFFMTB |IO_L01P_2/M1 |UNUSED | |2 | | | | | | | | |
|P24 | |DIFFMTB |IO_L02P_2/M2 |UNUSED | |2 | | | | | | | | |
|P25 | |DIFFSTB |IO_L01N_2/M0 |UNUSED | |2 | | | | | | | | |
|P26 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P27 | |DIFFSTB |IO_L02N_2/CSO_B |UNUSED | |2 | | | | | | | | |
|P28 |display_seg<2> |IOB |IO_L03P_2/RDWR_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P29 | |DIFFSTB |IO_L03N_2/VS2 |UNUSED | |2 | | | | | | | | |
|P30 | |DIFFMTB |IO_L04P_2/VS1 |UNUSED | |2 | | | | | | | | |
|P31 | |DIFFSTB |IO_L04N_2/VS0 |UNUSED | |2 | | | | | | | | |
|P32 | |DIFFMTB |IO_L05P_2 |UNUSED | |2 | | | | | | | | |
|P33 | |DIFFSTB |IO_L05N_2 |UNUSED | |2 | | | | | | | | |
|P34 | |DIFFMTB |IO_L06P_2/D7 |UNUSED | |2 | | | | | | | | |
|P35 |pmod_ncs |IOB |IO_L06N_2/D6 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P36 |pmod_sclk |IOB |IO_L07P_2/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P37 |pmod_sdata2 |IBUF |IO_L07N_2/D4 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE |
|P38 | | |VCCINT | | | | | | | |1.2 | | | |
|P39 |pmod_sdata1 |IBUF |IP_2/VREF_2 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE |
|P40 |slow_clock |IBUF |IO_L08P_2/GCLK14 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE |
|P41 | |DIFFSTB |IO_L08N_2/GCLK15 |UNUSED | |2 | | | | | | | | |
|P42 | | |GND | | | | | | | | | | | |
|P43 |clock |IBUF |IO_L09P_2/GCLK0 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE |
|P44 | |DIFFSTB |IO_L09N_2/GCLK1 |UNUSED | |2 | | | | | | | | |
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P46 | |DIFFSTB |IO_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | |
|P47 | | |GND | | | | | | | | | | | |
|P48 | |DIFFMTB |IO_L10P_2/INIT_B |UNUSED | |2 | | | | | | | | |
|P49 | |DIFFSTB |IO_L10N_2/D3 |UNUSED | |2 | | | | | | | | |
|P50 | |DIFFMTB |IO_L11P_2/D2 |UNUSED | |2 | | | | | | | | |
|P51 | |DIFFMTB |IO_L12P_2/D0/DIN/MISO |UNUSED | |2 | | | | | | | | |
|P52 | |DIFFSTB |IO_L11N_2/D1 |UNUSED | |2 | | | | | | | | |
|P53 | |DIFFSTB |IO_L12N_2/CCLK |UNUSED | |2 | | | | | | | | |
|P54 | | |DONE | | | | | | | | | | | |
|P55 | | |VCCAUX | | | | | | | |2.5 | | | |
|P56 | |DIFFMLR |IO_L01P_1 |UNUSED | |1 | | | | | | | | |
|P57 |display_char<2>|IOB |IO_L01N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P58 | | |GND | | | | | | | | | | | |
|P59 |display_char<3>|IOB |IO_L02P_1/RHCLK0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P60 |display_char<0>|IOB |IO_L02N_1/RHCLK1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P61 |display_char<1>|IOB |IO_L03P_1/RHCLK2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P62 |display_seg<1> |IOB |IO_L03N_1/TRDY1/RHCLK3|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P63 | | |GND | | | | | | | | | | | |
|P64 |display_seg<5> |IOB |IO_L04P_1/IRDY1/RHCLK6|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P65 |display_seg<6> |IOB |IO_L04N_1/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P66 | | |VCCINT | | | | | | | |1.2 | | | |
|P67 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|P68 | |DIFFMI_NDT|IP_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|P69 | | |GND | | | | | | | | | | | |
|P70 |display_seg<3> |IOB |IO_L05P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P71 | |DIFFSLR |IO_L05N_1 |UNUSED | |1 | | | | | | | | |
|P72 |display_seg<4> |IOB |IO_L06P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P73 |display_seg<0> |IOB |IO_L06N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P74 | | |GND | | | | | | | | | | | |
|P75 | | |TDO | | | | | | | | | | | |
|P76 | | |TCK | | | | | | | | | | | |
|P77 |reset |IBUF |IO_L01P_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE |
|P78 | |DIFFSTB |IO_L01N_0 |UNUSED | |0 | | | | | | | | |
|P79 | | |VCCO_0 | | |0 | | | | |any******| | | |
|P80 | | |GND | | | | | | | | | | | |
|P81 | | |VCCINT | | | | | | | |1.2 | | | |
|P82 | |IBUF |IP_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|P83 |convert_button |IBUF |IO_L02P_0/GCLK4 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE |
|P84 | |DIFFSTB |IO_L02N_0/GCLK5 |UNUSED | |0 | | | | | | | | |
|P85 | |DIFFMTB |IO_L03P_0/GCLK6 |UNUSED | |0 | | | | | | | | |
|P86 | |DIFFSTB |IO_L03N_0/GCLK7 |UNUSED | |0 | | | | | | | | |
|P87 | | |GND | | | | | | | | | | | |
|P88 | |DIFFMTB |IO_L04P_0/GCLK8 |UNUSED | |0 | | | | | | | | |
|P89 | |DIFFSTB |IO_L04N_0/GCLK9 |UNUSED | |0 | | | | | | | | |
|P90 | |DIFFSTB |IO_0/GCLK11 |UNUSED | |0 | | | | | | | | |
|P91 | | |GND | | | | | | | | | | | |
|P92 | | |VCCAUX | | | | | | | |2.5 | | | |
|P93 | |DIFFMTB |IO_L05P_0 |UNUSED | |0 | | | | | | | | |
|P94 | |DIFFSTB |IO_L05N_0 |UNUSED | |0 | | | | | | | | |
|P95 | | |GND | | | | | | | | | | | |
|P96 | | |VCCO_0 | | |0 | | | | |any******| | | |
|P97 | |IBUF |IP_0 |UNUSED | |0 | | | | | | | | |
|P98 | |DIFFMTB |IO_L06P_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|P99 | |DIFFSTB |IO_L06N_0/PUDC_B |UNUSED | |0 | | | | | | | | |
|P100 | | |PROG_B | | | | | | | | | | | |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
 
 
/phr/trunk/codigo/implementaciones/adc/pmod/adcontroller.vhd
0,0 → 1,258
-------------------------------------------------------------------------
-- AD1RefComp.VHD
-------------------------------------------------------------------------
-- Author : Ioana Dabacan
-- CopyRight 2008 Digilent Ro.
-------------------------------------------------------------------------
-- Description : This file is the VHDL code for a PMOD-AD1 controller.
--
-------------------------------------------------------------------------
-- Revision History:
-- Feb/29/2008 Created (Ioana Dabacan)
-------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------
--Title : AD1 Reference Component
--
-- Inputs : 5
-- Outputs : 5
--
-- Description: This is the AD1 Reference Component entity. The input
-- ports are a 50 MHz clock and an asynchronous reset
-- button along with the data from the ADC7476 that
-- is serially shifted in on each clock cycle(SDATA1 and
-- SDATA2). The outputs are the SCLK signal which clocks
-- the PMOD-AD1 board at 12.5 MHz and a chip select
-- signal (nCS) that enables the ADC7476 chips on the
-- PMOD-AD1 board as well as two 12-bit output
-- vectors labeled DATA1 and DATA2 which can be used by
-- any external components. The START is used to tell
-- the component when to start a conversion. After a
-- conversion is done the component activates the DONE
-- signal.
--
--------------------------------------------------------------------------
 
entity AD1RefComp is
Port (
--General usage
CLK : in std_logic;
RST : in std_logic;
--Pmod interface signals
SDATA1 : in std_logic;
SDATA2 : in std_logic;
SCLK : out std_logic;
nCS : out std_logic;
--User interface signals
DATA1 : out std_logic_vector(11 downto 0);
DATA2 : out std_logic_vector(11 downto 0);
START : in std_logic;
DONE : out std_logic
);
 
end AD1RefComp ;
 
architecture AD1 of AD1RefComp is
 
--------------------------------------------------------------------------------
-- Title : Local signal assignments
--
-- Description : The following signals will be used to drive the
-- processes of this VHDL file.
--
-- current_state : This signal will be the pointer that will point at the
-- current state of the Finite State Machine of the
-- controller.
-- next_state : This signal will be the pointer that will point at the
-- current state of the Finite State Machine of the
-- controller.
-- temp1 : This is a 16-bit vector that will store the 16-bits of data
-- that are serially shifted-in form the first ADC7476 chip
-- inside the PMOD-AD1 board.
-- temp2 : This is a 16-bit vector that will store the 16-bits of data
-- that are serially shifted-in form the second ADC7476 chip
-- inside the PMOD-AD1 board.
-- clk_div : This will be the divided 12.5 MHz clock signal that will
-- clock the PMOD-AD1 board
-- clk_counter : This counter will be used to create a divided clock signal.
--
-- shiftCounter : This counter will be used to count the shifted data from
-- the ADC7476 chip inside the PMOD-AD1 board.
-- enShiftCounter: This signal will be used to enable the counter for the
-- shifted data from the ADC7476 chip inside the PMOD-AD1.
-- enParalelLoad : This signal will be used to enable the load the shifted
-- data in a register.
--------------------------------------------------------------------------------
 
type states is (Idle,
ShiftIn,
SyncData);
signal current_state : states;
signal next_state : states;
signal temp1 : std_logic_vector(15 downto 0);
signal temp2 : std_logic_vector(15 downto 0);
signal clk_div : std_logic;
signal clk_counter : std_logic_vector(1 downto 0);
signal shiftCounter : std_logic_vector(3 downto 0) := x"0";
signal enShiftCounter: std_logic;
signal enParalelLoad : std_logic;
 
 
begin
 
--------------------------------------------------------------------------------
-- Title : clock divider process
--
-- Description : This is the process that will divide the 50 MHz clock
-- down to a clock speed of 12.5 MHz to drive the ADC7476 chip.
--------------------------------------------------------------------------------
clock_divide : process(rst,clk)
begin
if rst = '1' then
clk_counter <= "00";
elsif (clk = '1' and clk'event) then
clk_counter <= clk_counter + '1';
end if;
end process;
 
clk_div <= clk_counter(1);
SCLK <= not clk_counter(1);
 
-----------------------------------------------------------------------------------
--
-- Title : counter
--
-- Description: This is the process were the converted data will be colected and
-- output.When the enShiftCounter is activated, the 16-bits of data
-- from the ADC7476 chips will be shifted inside the temporary
-- registers. A 4-bit counter is used to keep shifting the data
-- inside temp1 and temp2 for 16 clock cycles. When the enParalelLoad
-- signal is generated inside the SyncData state, the converted data
-- in the temporary shift registers will be placed on the outputs
-- DATA1 and DATA2.
--
-----------------------------------------------------------------------------------
 
counter : process(clk_div, enParalelLoad, enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then
if (enShiftCounter = '1') then
temp1 <= temp1(14 downto 0) & SDATA1;
temp2 <= temp2(14 downto 0) & SDATA2;
shiftCounter <= shiftCounter + '1';
elsif (enParalelLoad = '1') then
shiftCounter <= "0000";
DATA1 <= temp1(11 downto 0);
DATA2 <= temp2(11 downto 0);
end if;
end if;
end process;
---------------------------------------------------------------------------------
--
-- Title : Finite State Machine
--
-- Description: This 3 processes represent the FSM that contains three states.
-- The first state is the Idle state in which a temporary registers
-- are assigned the updated value of the input "DATA1" and "DATA2".
-- The next state is the ShiftIn state where the 16-bits of data
-- from each of the ADCS7476 chips are left shifted in the temp1
-- and temp2 shift registers. The third state, SyncData drives the
-- output signal nCS high for 1 clock period maintainig nCS high
-- also in the Idle state telling the ADCS7476 to mark the end of
-- the conversion.
-- Notes: The data will change on the lower edge of the clock signal. There
-- is also an asynchronous reset that will reset all signals to
-- their original state.
--
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--
-- Title : SYNC_PROC
--
-- Description: This is the process were the states are changed synchronously. At
-- reset the current state becomes Idle state.
--
-----------------------------------------------------------------------------------
SYNC_PROC: process (clk_div, rst)
begin
if (clk_div'event and clk_div = '1') then
if (rst = '1') then
current_state <= Idle;
else
current_state <= next_state;
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--
-- Title : OUTPUT_DECODE
--
-- Description: This is the process were the output signals are generated
-- unsynchronously based on the state only (Moore State Machine).
--
-----------------------------------------------------------------------------------
OUTPUT_DECODE: process (current_state)
begin
if current_state = Idle then
enShiftCounter <='0';
DONE <='1';
nCS <='1';
enParalelLoad <= '0';
elsif current_state = ShiftIn then
enShiftCounter <='1';
DONE <='0';
nCS <='0';
enParalelLoad <= '0';
else --if current_state = SyncData then
enShiftCounter <='0';
DONE <='0';
nCS <='1';
enParalelLoad <= '1';
end if;
end process;
----------------------------------------------------------------------------------
--
-- Title : NEXT_STATE_DECODE
--
-- Description: This is the process were the next state logic is generated
-- depending on the current state and the input signals.
--
-----------------------------------------------------------------------------------
NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
begin
next_state <= current_state; -- default is to stay in current state
case (current_state) is
when Idle =>
if START = '1' then
next_state <= ShiftIn;
end if;
when ShiftIn =>
if shiftCounter = x"F" then
next_state <= SyncData;
end if;
when SyncData =>
if START = '0' then
next_state <= Idle;
end if;
when others =>
next_state <= Idle;
end case;
end process;
 
 
end AD1;
/phr/trunk/codigo/implementaciones/adc/pmod/sevenseg_display_tb.vhd
0,0 → 1,74
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sevenseg_display_tb IS
END sevenseg_display_tb;
ARCHITECTURE behavior OF sevenseg_display_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sevseg_display
PORT(
clock : IN std_logic;
reset : IN std_logic;
data : IN std_logic_vector(15 downto 0);
segments : OUT std_logic_vector(6 downto 0);
char_sel : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
 
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal data : std_logic_vector(15 downto 0) := "0000000100100011";
--signal data : std_logic_vector(15 downto 0) := (others => '0');
 
--Outputs
signal segments : std_logic_vector(6 downto 0);
signal char_sel : std_logic_vector(3 downto 0);
 
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sevseg_display PORT MAP (
clock => clock,
reset => reset,
data => data,
segments => segments,
char_sel => char_sel
);
 
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
 
-- -- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for clock_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
 
END;
/phr/trunk/codigo/implementaciones/adc/pmod/pines.ucf
0,0 → 1,26
 
#NET "SW7" LOC = "K13";
 
net "clock" loc="P43"; # 50 MHz clock
net "slow_clock" loc="P40"; #
net "reset" loc="P77"; # Button 1
net "convert_button" loc="P83"; # Button 4
 
net "pmod_sdata1" loc="P39"; # change
net "pmod_sdata2" loc="P37"; # change
net "pmod_sclk" loc="P36"; # change
net "pmod_ncs" loc="P35"; # change
 
net "display_char<3>" loc="P59";
net "display_char<2>" loc="P57";
net "display_char<1>" loc="P61";
net "display_char<0>" loc="P60";
 
net "display_seg<6>" loc="P65";
net "display_seg<5>" loc="P64";
net "display_seg<4>" loc="P72";
net "display_seg<3>" loc="P70";
net "display_seg<2>" loc="P28";
net "display_seg<1>" loc="P62";
net "display_seg<0>" loc="P73";
 
/phr/trunk/codigo/implementaciones/adc/pmod/.lso
0,0 → 1,26
work
/phr/trunk/codigo/implementaciones/adc/pmod2nexys2/sevseg_display.vhd
0,0 → 1,94
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
 
 
entity sevseg_display is
Port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (15 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0);
char_sel : out STD_LOGIC_VECTOR (3 downto 0));
end sevseg_display;
 
architecture Behavioral of sevseg_display is
signal count : unsigned (1 downto 0);
signal char : std_logic_vector (3 downto 0);
begin
 
counter: process (clock, reset)
variable count_var : unsigned (1 downto 0) := "00";
begin
if reset='1' then
count_var := (others => '0');
elsif falling_edge(clock) then
count_var := count + 1;
end if;
count <= count_var;
end process;
 
char_selector: process (clock, count)
begin
if rising_edge(clock) then
case count is
when "00" => char_sel <= "1110";
when "01" => char_sel <= "1101";
when "10" => char_sel <= "1011";
when "11" => char_sel <= "0111";
when others => char_sel <= "1111";
end case;
end if;
end process;
 
data_selector: process (clock, count)
begin
if rising_edge (clock) then
case count is
when "00" => char <= data(3 downto 0);
when "01" => char <= data(7 downto 4);
when "10" => char <= data(11 downto 8);
when "11" => char <= data(15 downto 12);
when others => char <= "0000";
end case;
end if;
end process;
 
 
bin2seven: process (char, reset)
variable segments_var : STD_LOGIC_VECTOR (6 downto 0);
begin
 
if reset = '1' then
segments_var := "1111111";
else
case char is
when "0000" => segments_var := "0000001"; -- 0
when "0001" => segments_var := "1001111"; -- 1
when "0010" => segments_var := "0010010"; -- 2
when "0011" => segments_var := "0000110"; -- 3
when "0100" => segments_var := "1001100"; -- 4
when "0101" => segments_var := "0100100"; -- 5
when "0110" => segments_var := "0100000"; -- 6
when "0111" => segments_var := "0001111"; -- 7
when "1000" => segments_var := "0000000"; -- 8
when "1001" => segments_var := "0000100"; -- 9
when "1010" => segments_var := "0001000"; -- a
when "1011" => segments_var := "1100000"; -- b
when "1100" => segments_var := "0110001"; -- c
when "1101" => segments_var := "1000010"; -- d
when "1110" => segments_var := "0110000"; -- e
when "1111" => segments_var := "0111000"; -- f
when others => segments_var := "1111110";
end case;
end if;
segments <= segments_var;
end process;
 
 
end Behavioral;
 
/phr/trunk/codigo/implementaciones/adc/pmod2nexys2/Nexys2_1200General.ucf
0,0 → 1,250
## This file is a general .ucf for Nexys2 rev A board
## To use it in a project:
## - remove or comment the lines corresponding to unused pins
## - rename the used signals according to the project
 
 
## Both versions are provided in this file.
## Keep only the appropriate one, and remove or comment the other one.
 
 
## Clock pin for Nexys 2 Board
#NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
 
## onBoard USB controller
## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
 
## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
 
## If using the DEPP interface uncomment lines 29-32
#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
 
## If using the DSTM interface uncomment lines 35-44
#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
 
#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
 
## onBoard Cellular RAM and StrataFlash
#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
 
#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
 
#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
 
#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
 
#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
 
## 7 segment display
#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
 
#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
 
## Leds
#NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
#NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
#NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
#NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
#NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
#NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
#NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
#NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
 
## Switches
#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
 
## Buttons
#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
 
## VGA Connector
#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
 
#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
 
## PS/2 connector
#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
 
## FX2 connector
#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
 
## 12 pin connectors
 
##JA
#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
 
##JB
#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
 
##JC
#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
 
##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
 
## RS232 connector
#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
/phr/trunk/codigo/implementaciones/adc/pmod2nexys2/displayPmod.vhd
0,0 → 1,109
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
 
entity displayPmod is
Port (
clock : in STD_LOGIC;
--slow_clock : in STD_LOGIC;
reset : in STD_LOGIC;
-- convert_button : in std_logic;
pmod_sdata1 : in std_logic;
pmod_sdata2 : in std_logic;
pmod_sclk : out std_logic;
pmod_ncs : out std_logic;
display_char : out STD_LOGIC_VECTOR (3 downto 0);
display_seg : out STD_LOGIC_VECTOR (6 downto 0));
end displayPmod;
 
architecture Behavioral of displayPmod is
 
COMPONENT AD1RefComp
PORT(
CLK : IN std_logic;
RST : IN std_logic;
SDATA1 : IN std_logic;
SDATA2 : IN std_logic;
START : IN std_logic;
SCLK : OUT std_logic;
nCS : OUT std_logic;
DATA1 : OUT std_logic_vector(11 downto 0);
DATA2 : OUT std_logic_vector(11 downto 0);
DONE : OUT std_logic
);
END COMPONENT;
COMPONENT sevseg_display
PORT(
clock : IN std_logic;
reset : IN std_logic;
data : IN std_logic_vector(15 downto 0);
segments : OUT std_logic_vector(6 downto 0);
char_sel : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal data1 : std_logic_vector (15 downto 0) := (others => '0');
signal data2 : std_logic_vector (15 downto 0) := (others => '0');
signal done : std_logic;
signal Sstart_conv : std_logic_vector (9 downto 0) := (others => '0');
signal Sslow_clock : std_logic := '0';
begin
 
Inst_AD1RefComp: AD1RefComp PORT MAP(
CLK => clock,
RST => reset,
SDATA1 => pmod_sdata1,
SDATA2 => pmod_sdata2,
SCLK => pmod_sclk,
nCS => pmod_ncs,
DATA1 => data1 (11 downto 0),
DATA2 => data2 (11 downto 0),
--START => convert_button,
START => Sstart_conv(9),
DONE => done
);
process(clock)
begin
if(falling_edge(clock)) then
Sstart_conv <= Sstart_conv(8 downto 0) & done;
end if;
end process;
data1(15 downto 12) <= "0000";
 
process(clock)
variable cuenta: integer:=0;
begin
if (falling_edge(clock)) then
if (cuenta<50) then
cuenta:=cuenta + 1;
else
Sslow_clock <=not Sslow_clock;
cuenta:=0;
end if;
end if;
end process;
 
Inst_sevseg_display: sevseg_display PORT MAP(
clock => Sslow_clock,
reset => reset,
data => data1,
--data => "0000000000011111",
segments => display_seg (6 downto 0),
char_sel => display_char (3 downto 0)
);
 
end Behavioral;
 
/phr/trunk/codigo/implementaciones/adc/pmod2nexys2/adcontroller.vhd
0,0 → 1,258
-------------------------------------------------------------------------
-- AD1RefComp.VHD
-------------------------------------------------------------------------
-- Author : Ioana Dabacan
-- CopyRight 2008 Digilent Ro.
-------------------------------------------------------------------------
-- Description : This file is the VHDL code for a PMOD-AD1 controller.
--
-------------------------------------------------------------------------
-- Revision History:
-- Feb/29/2008 Created (Ioana Dabacan)
-------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------
--Title : AD1 Reference Component
--
-- Inputs : 5
-- Outputs : 5
--
-- Description: This is the AD1 Reference Component entity. The input
-- ports are a 50 MHz clock and an asynchronous reset
-- button along with the data from the ADC7476 that
-- is serially shifted in on each clock cycle(SDATA1 and
-- SDATA2). The outputs are the SCLK signal which clocks
-- the PMOD-AD1 board at 12.5 MHz and a chip select
-- signal (nCS) that enables the ADC7476 chips on the
-- PMOD-AD1 board as well as two 12-bit output
-- vectors labeled DATA1 and DATA2 which can be used by
-- any external components. The START is used to tell
-- the component when to start a conversion. After a
-- conversion is done the component activates the DONE
-- signal.
--
--------------------------------------------------------------------------
 
entity AD1RefComp is
Port (
--General usage
CLK : in std_logic;
RST : in std_logic;
--Pmod interface signals
SDATA1 : in std_logic;
SDATA2 : in std_logic;
SCLK : out std_logic;
nCS : out std_logic;
--User interface signals
DATA1 : out std_logic_vector(11 downto 0);
DATA2 : out std_logic_vector(11 downto 0);
START : in std_logic;
DONE : out std_logic
);
 
end AD1RefComp ;
 
architecture AD1 of AD1RefComp is
 
--------------------------------------------------------------------------------
-- Title : Local signal assignments
--
-- Description : The following signals will be used to drive the
-- processes of this VHDL file.
--
-- current_state : This signal will be the pointer that will point at the
-- current state of the Finite State Machine of the
-- controller.
-- next_state : This signal will be the pointer that will point at the
-- current state of the Finite State Machine of the
-- controller.
-- temp1 : This is a 16-bit vector that will store the 16-bits of data
-- that are serially shifted-in form the first ADC7476 chip
-- inside the PMOD-AD1 board.
-- temp2 : This is a 16-bit vector that will store the 16-bits of data
-- that are serially shifted-in form the second ADC7476 chip
-- inside the PMOD-AD1 board.
-- clk_div : This will be the divided 12.5 MHz clock signal that will
-- clock the PMOD-AD1 board
-- clk_counter : This counter will be used to create a divided clock signal.
--
-- shiftCounter : This counter will be used to count the shifted data from
-- the ADC7476 chip inside the PMOD-AD1 board.
-- enShiftCounter: This signal will be used to enable the counter for the
-- shifted data from the ADC7476 chip inside the PMOD-AD1.
-- enParalelLoad : This signal will be used to enable the load the shifted
-- data in a register.
--------------------------------------------------------------------------------
 
type states is (Idle,
ShiftIn,
SyncData);
signal current_state : states;
signal next_state : states;
signal temp1 : std_logic_vector(15 downto 0);
signal temp2 : std_logic_vector(15 downto 0);
signal clk_div : std_logic;
signal clk_counter : std_logic_vector(1 downto 0);
signal shiftCounter : std_logic_vector(3 downto 0) := x"0";
signal enShiftCounter: std_logic;
signal enParalelLoad : std_logic;
 
 
begin
 
--------------------------------------------------------------------------------
-- Title : clock divider process
--
-- Description : This is the process that will divide the 50 MHz clock
-- down to a clock speed of 12.5 MHz to drive the ADC7476 chip.
--------------------------------------------------------------------------------
clock_divide : process(rst,clk)
begin
if rst = '1' then
clk_counter <= "00";
elsif (clk = '1' and clk'event) then
clk_counter <= clk_counter + '1';
end if;
end process;
 
clk_div <= clk_counter(1);
SCLK <= not clk_counter(1);
 
-----------------------------------------------------------------------------------
--
-- Title : counter
--
-- Description: This is the process were the converted data will be colected and
-- output.When the enShiftCounter is activated, the 16-bits of data
-- from the ADC7476 chips will be shifted inside the temporary
-- registers. A 4-bit counter is used to keep shifting the data
-- inside temp1 and temp2 for 16 clock cycles. When the enParalelLoad
-- signal is generated inside the SyncData state, the converted data
-- in the temporary shift registers will be placed on the outputs
-- DATA1 and DATA2.
--
-----------------------------------------------------------------------------------
 
counter : process(clk_div, enParalelLoad, enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then
if (enShiftCounter = '1') then
temp1 <= temp1(14 downto 0) & SDATA1;
temp2 <= temp2(14 downto 0) & SDATA2;
shiftCounter <= shiftCounter + '1';
elsif (enParalelLoad = '1') then
shiftCounter <= "0000";
DATA1 <= temp1(11 downto 0);
DATA2 <= temp2(11 downto 0);
end if;
end if;
end process;
---------------------------------------------------------------------------------
--
-- Title : Finite State Machine
--
-- Description: This 3 processes represent the FSM that contains three states.
-- The first state is the Idle state in which a temporary registers
-- are assigned the updated value of the input "DATA1" and "DATA2".
-- The next state is the ShiftIn state where the 16-bits of data
-- from each of the ADCS7476 chips are left shifted in the temp1
-- and temp2 shift registers. The third state, SyncData drives the
-- output signal nCS high for 1 clock period maintainig nCS high
-- also in the Idle state telling the ADCS7476 to mark the end of
-- the conversion.
-- Notes: The data will change on the lower edge of the clock signal. There
-- is also an asynchronous reset that will reset all signals to
-- their original state.
--
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--
-- Title : SYNC_PROC
--
-- Description: This is the process were the states are changed synchronously. At
-- reset the current state becomes Idle state.
--
-----------------------------------------------------------------------------------
SYNC_PROC: process (clk_div, rst)
begin
if (clk_div'event and clk_div = '1') then
if (rst = '1') then
current_state <= Idle;
else
current_state <= next_state;
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--
-- Title : OUTPUT_DECODE
--
-- Description: This is the process were the output signals are generated
-- unsynchronously based on the state only (Moore State Machine).
--
-----------------------------------------------------------------------------------
OUTPUT_DECODE: process (current_state)
begin
if current_state = Idle then
enShiftCounter <='0';
DONE <='1';
nCS <='1';
enParalelLoad <= '0';
elsif current_state = ShiftIn then
enShiftCounter <='1';
DONE <='0';
nCS <='0';
enParalelLoad <= '0';
else --if current_state = SyncData then
enShiftCounter <='0';
DONE <='0';
nCS <='1';
enParalelLoad <= '1';
end if;
end process;
----------------------------------------------------------------------------------
--
-- Title : NEXT_STATE_DECODE
--
-- Description: This is the process were the next state logic is generated
-- depending on the current state and the input signals.
--
-----------------------------------------------------------------------------------
NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
begin
next_state <= current_state; -- default is to stay in current state
case (current_state) is
when Idle =>
if START = '1' then
next_state <= ShiftIn;
end if;
when ShiftIn =>
if shiftCounter = x"F" then
next_state <= SyncData;
end if;
when SyncData =>
if START = '0' then
next_state <= Idle;
end if;
when others =>
next_state <= Idle;
end case;
end process;
 
 
end AD1;
/phr/trunk/codigo/implementaciones/adc/pmod2nexys2/pines.ucf
0,0 → 1,21
net "clock" loc="B8"; # 50 MHz clock
net "reset" loc="B18"; # Button 1
 
net "pmod_sdata1" loc="M18"; # change
net "pmod_sdata2" loc="N18"; # change
net "pmod_sclk" loc="P36"; # change
net "pmod_ncs" loc="P18"; # change
 
net "display_char<3>" loc="F17";
net "display_char<2>" loc="H17";
net "display_char<1>" loc="C18";
net "display_char<0>" loc="F15";
 
net "display_seg<6>" loc="L18";
net "display_seg<5>" loc="F18";
net "display_seg<4>" loc="D17";
net "display_seg<3>" loc="D16";
net "display_seg<2>" loc="G14";
net "display_seg<1>" loc="J17";
net "display_seg<0>" loc="H14";
 
/phr/trunk/codigo/implementaciones/adc/pmod2nexys2/.lso
0,0 → 1,21
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