URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 39 to Rev 40
- ↔ Reverse comparison
Rev 39 → Rev 40
/opencpu32/trunk/hdl/opencpu32/opencpu32.xise
119,7 → 119,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
/opencpu32/trunk/hdl/opencpu32/testOpenCpu.vhd
81,13 → 81,13
-- Stimulus process |
stim_proc: process |
file cmdfile: TEXT; -- Define the file 'handle' |
variable line_in,line_out: Line; -- Line buffer |
variable line_in: Line; -- Line buffer |
variable good: boolean; -- Flag to detect a good line read |
variable instructionCode : std_logic_vector(n downto 0); |
begin |
-- Reset operation |
REPORT "RESET" SEVERITY NOTE; |
-- Open source file |
-- Open source file for reading... |
FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",READ_MODE); |
|
-- Check end of file |
/opencpu32/trunk/hdl/opencpu32/testControlUnit.vhd
9,6 → 9,12
|
--! Use CPU Definitions package |
use work.pkgOpenCPU32.all; |
|
--! Adding library for File I/O |
-- More information on this site: |
-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm |
use std.textio.ALL; |
use ieee.std_logic_textio.all; |
|
ENTITY testControlUnit IS |
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package) |
114,9 → 120,13
|
-- Stimulus process |
stim_proc: process |
variable line_out: Line; -- Line that will be written to a file |
file cmdfile: TEXT; -- Define the file 'handle' |
begin |
-- Reset operation |
REPORT "RESET" SEVERITY NOTE; |
-- Open source file for write... |
FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE); |
reset <= '1'; |
wait for 2 ns; |
reset <= '0'; |
124,11 → 134,15
|
-- MOV r0,10d (Compare control unit outputs with Datapath)-------------------------------------- |
REPORT "MOV r0,10" SEVERITY NOTE; |
MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22); |
MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22); |
wait for CLK_period; -- Fetch |
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Write the command to a file (This will be usefull for the top Testing later) |
WRITE (line_out, MemoryDataInput); |
WRITELINE (cmdfile, line_out); |
|
-- Verify if signals for the datapath are valid |
assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE; |
assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE; |
157,6 → 171,10
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Write the command to a file (This will be usefull for the top Testing later) |
WRITE (line_out, MemoryDataInput); |
WRITELINE (cmdfile, line_out); |
|
-- Verify if signals for the datapath are valid |
assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE; |
assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE; |
185,6 → 203,10
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Write the command to a file (This will be usefull for the top Testing later) |
WRITE (line_out, MemoryDataInput); |
WRITELINE (cmdfile, line_out); |
|
-- Verify if signals for the datapath are valid |
assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE; |
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE; |
212,6 → 234,10
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Write the command to a file (This will be usefull for the top Testing later) |
WRITE (line_out, MemoryDataInput); |
WRITELINE (cmdfile, line_out); |
|
-- Verify if signals for the datapath are valid |
assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE; |
assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE; |
243,6 → 269,10
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Write the command to a file (This will be usefull for the top Testing later) |
WRITE (line_out, MemoryDataInput); |
WRITELINE (cmdfile, line_out); |
|
-- Verify if signals for the datapath are valid |
assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE; |
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE; |
267,7 → 297,9
assert outEnDp = disable report "Invalid value" severity FAILURE; |
------------------------------------------------------------------------------------------------- |
|
-- Finish simulation |
-- Close file |
file_close(cmdfile); |
-- Finish simulation |
assert false report "NONE. End of simulation." severity failure; |
wait; |
end process; |
/opencpu32/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/opencpu32/hdl/opencpu32/testOpenCpu.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/opencpu32/hdl/opencpu32/testControlUnit.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
224,7 → 224,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334586393" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334586393"> |
<transform xil_pn:end_ts="1334614496" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334614496"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="Alu.vhd"/> |
244,11 → 244,11
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334583326" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334583326"> |
<transform xil_pn:end_ts="1334614520" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334614520"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334583326" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334583326"> |
<transform xil_pn:end_ts="1334614520" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334614520"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
256,7 → 256,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334586393" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334586393"> |
<transform xil_pn:end_ts="1334614496" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334614496"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="Alu.vhd"/> |
276,11 → 276,9
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334586395" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334586393"> |
<transform xil_pn:end_ts="1334614522" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334614520"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
288,7 → 286,7
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1334586614" xil_pn:in_ck="140931753749638428" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334586614"> |
<transform xil_pn:end_ts="1334614523" xil_pn:in_ck="-7416607345915100494" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334614522"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="isim.cmd"/> |
/opencpu32/trunk/hdl/opencpu32/testCode/testCodeBin.dat
1,9 → 1,5
00000000000000000000000000000000 |
00000000000000000000000000000001 |
00000000000000000000000000000010 |
00000000000000000000000000000011 |
00000000000000000000000000000100 |
00000000000000000000000000000101 |
00000000000000000000000000000110 |
00000000000000000000000000000111 |
00000000000000000000000000001000 |
00000100000000000000000000001010 |
00000100010000000000000000010100 |
00000000100001000000000000000000 |
01101100100000000000000000000000 |
01110000100000000000000000000010 |