URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 39 to Rev 40
- ↔ Reverse comparison
Rev 39 → Rev 40
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run
Property changes :
Modified: svn:ignore
## -1,4 +1,4 ##
-rom.*
+pmem.*
simv
stimulus.v
*.vcd
Index: openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v
===================================================================
--- openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v (revision 39)
+++ openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v (revision 40)
@@ -50,17 +50,17 @@
//=============================================================================
`include "../../../rtl/verilog/openmsp430/openMSP430.v"
-`include "../../../rtl/verilog/openmsp430/frontend.v"
-`include "../../../rtl/verilog/openmsp430/execution_unit.v"
-`include "../../../rtl/verilog/openmsp430/register_file.v"
-`include "../../../rtl/verilog/openmsp430/alu.v"
-`include "../../../rtl/verilog/openmsp430/mem_backbone.v"
-`include "../../../rtl/verilog/openmsp430/clock_module.v"
-`include "../../../rtl/verilog/openmsp430/dbg.v"
-`include "../../../rtl/verilog/openmsp430/dbg_hwbrk.v"
-`include "../../../rtl/verilog/openmsp430/dbg_uart.v"
-`include "../../../rtl/verilog/openmsp430/sfr.v"
-`include "../../../rtl/verilog/openmsp430/watchdog.v"
-`include "../../../rtl/verilog/openmsp430/periph/gpio.v"
-`include "../../../rtl/verilog/openmsp430/periph/timerA.v"
+`include "../../../rtl/verilog/openmsp430/omsp_frontend.v"
+`include "../../../rtl/verilog/openmsp430/omsp_execution_unit.v"
+`include "../../../rtl/verilog/openmsp430/omsp_register_file.v"
+`include "../../../rtl/verilog/openmsp430/omsp_alu.v"
+`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
+`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
+`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
+`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
+`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
+`include "../../../rtl/verilog/openmsp430/omsp_sfr.v"
+`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
+`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v"
+`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"