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URL https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk

Subversion Repositories simple_fm_receiver

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  • This comparison shows the changes necessary to convert path
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    from Rev 39 to Rev 40
    Reverse comparison

Rev 39 → Rev 40

/simple_fm_receiver/trunk/bench/xilinx_fpga.vhdl
13,11 → 13,8
-------------------------------------------------------------------------------
-- Description : Xilinx Connector to ILA, ICON, VIO
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- Copyright (C) 2004 Arif Endro Nugroho
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
/simple_fm_receiver/trunk/bench/bench.vhdl
13,11 → 13,8
-------------------------------------------------------------------------------
-- Description : Test bench for FM receiver
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- Copyright (C) 2004 Arif Endro Nugroho
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
/simple_fm_receiver/trunk/bench/input_fm.vhdl
13,11 → 13,8
-------------------------------------------------------------------------------
-- Description : Input signal FM 1000 signal
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- Copyright (C) 2004 Arif Endro Nugroho
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT

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