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URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 39 to Rev 40
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  •

Rev 39 → Rev 40

/tinycpu/trunk/testbench/top_tb.vhd
75,6 → 75,25
wait for 10 ns;
Reset <= '1';
wait for 200 ns;
Reset <= '0';
wait for 50 ns;
Port0(1) <= '1';
wait for 100 ns;
assert(Port0(0)='1') report "Toggle app not working" severity error;
wait for 10 ns;
Port0(0) <= '0';
wait for 100 ns;
assert(Port0(0)='0') report "Toggle app not working 2" severity error;
 
 
 
 
 
 
 
Reset <= '1';
wait for 100 ns;
wait for 10 ns;
Hold <= '1';
wait for 10 ns;
assert (HoldAck ='1') report "HoldAck not becoming high" severity error;
/tinycpu/trunk/src/bootrom.vhd
12,8 → 12,8
 
architecture syn of bootrom is
constant ROMSIZE: integer := 64;
type ROM_TYPE is array(ROMSIZE/2-1 downto 0) of std_logic_vector(15 downto 0);
signal ROM: ROM_TYPE := (x"0801", x"0a01", x"58a3", x"0600", x"0402", x"5063", x"4040", x"3007", x"1701", x"3006", x"1700", x"0e16",
type ROM_TYPE is array(0 to ROMSIZE/2-1) of std_logic_vector(15 downto 0);
signal ROM: ROM_TYPE := (x"0801", x"0a01", x"5853", x"0600", x"0402", x"5033", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e16",
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
signal rdata : std_logic_vector(15 downto 0);
begin
/tinycpu/trunk/src/top.vhd
88,9 → 88,11
signal MemDataOut: std_logic_vector(15 downto 0);
 
signal BootAddress: std_logic_vector(4 downto 0);
signal BootMemAddress: std_logic_vector(15 downto 0);
signal BootDataIn: std_logic_vector(15 downto 0);
signal BootDataOut: std_logic_vector(15 downto 0);
signal BootDone: std_logic;
signal BootFirst: std_logic;
constant ROMSIZE: integer := 64;
signal counter: std_logic_vector(4 downto 0);
begin
125,13 → 127,12
Addr => BootAddress,
Data => BootDataOut
);
MemAddress <= cpuaddr when (DMA='0' and Reset='0') else "00000001000" & BootAddress when (Reset='1' and DMA='0') else Address;
MemAddress <= cpuaddr when (DMA='0' and Reset='0') else BootMemAddress when (Reset='1' and DMA='0') else Address;
MemWriteWord <= cpuww when DMA='0' and Reset='0' else '1' when Reset='1' and DMA='0' else '1';
MemWriteEnable <= cpuwe when DMA='0' and Reset='0' else'1' when Reset='1' and DMA='0' else WriteEnable;
MemDataIn <= cpumemout when DMA='0' and Reset='0' else Data when WriteEnable='1' else BootDataIn when Reset='1' and DMA='0' else "ZZZZZZZZZZZZZZZZ";
cpumemin <= MemDataOut;
Data <= MemDataOut when DMA='1' and Reset='0' and WriteEnable='0' else "ZZZZZZZZZZZZZZZZ";
bootload: process(Clock, Reset)
begin
if rising_edge(clock) then
138,11 → 139,21
if Reset='0' then
counter <= "00000";
BootDone <= '0';
BootAddress <= "00000";
BootDataIn <= BootDataOut;
BootFirst <= '1';
elsif Reset='1' and BootFirst='1' then
BootMemAddress <= "00000001000" & "00000";
BootAddress <= "00001";
--BootDataIn <= BootDataOut;
counter <= "00001";
BootFirst <= '0';
elsif Reset='1' and BootDone='0' then
BootAddress <= counter;
BootMemAddress <= "0000000100" & std_logic_vector(unsigned(counter)-1) & "0";
BootAddress <= std_logic_vector(unsigned(counter) + 1);
BootDataIn <= BootDataOut;
counter <= std_logic_vector(unsigned(counter) + 1);
if to_integer(unsigned(counter))>=(ROMSIZE/2-1) then
if to_integer(unsigned(counter))>=(ROMSIZE/2-2) then
BootDone <= '1';
end if;
else
/tinycpu/trunk/assembler/asm.rb
21,7 → 21,7
class OpcodeByte2
attr_accessor :cond, :reg2, :useextra, :reg3;
def to_hex
s=(cond << 8 | reg2.number << 5 | useextra << 4 | reg3.number).to_s(16);
s=(cond << 7 | reg2.number << 4 | useextra << 3 | reg3.number).to_s(16);
if s.length == 1
"0"+s;
elsif s.length==0

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