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Rev 4 → Rev 5

/aes_decry_ip_128bit/trunk/testbench/misc_tb/tb_one_round_key.vhd
0,0 → 1,36
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_one_round_key is
end tb_one_round_key;
 
architecture beh_tb_one_round_key of tb_one_round_key is
component one_round_key
port(
in_key: in std_logic_vector(127 downto 0);
out_key: out std_logic_vector(127 downto 0);
rcon: in std_logic_vector(7 downto 0)
);
end component;
component Sbox
port (
data_in: in std_logic_vector(7 downto 0);
data_out:out std_logic_vector(7 downto 0)
);
end component;
 
signal key_in,key_out:std_logic_vector(127 downto 0);
signal rcon,in_data,out_data:std_logic_vector(7 downto 0);
begin
uut:one_round_key
port map(in_key=>key_in,out_key=>key_out,rcon=>rcon);
process
begin
wait for 100 ns;
key_in<=x"000102030405060708090a0b0c0d0e0f";
rcon<=x"01";
wait for 100 ns;
end process;
end beh_tb_one_round_key;
/aes_decry_ip_128bit/trunk/testbench/misc_tb/tb_AES_decrypt.vhd
0,0 → 1,146
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
 
entity tb_AES_decrypt is
end tb_AES_decrypt;
 
architecture beh_tb_AES_decrypt of tb_AES_decrypt is
component AES_decrypter
port (
cipher: in std_logic_vector(127 downto 0);
text_out: out std_logic_vector(127 downto 0);
key: in std_logic_vector(127 downto 0);
k_valid,c_valid: in std_logic;--Asserted when either key, cipher is valid
ready:out std_logic;--Asserted high when IP is ready to accept the data(key or Cipher)
out_valid: out std_logic;--out_valid:Asserted high when decrypted cipher is on the bus
clk,reset: in std_logic
);
end component;
constant clk_period: time := 10 ns;
signal reset,clk:std_logic;
signal cipher,text_out: std_logic_vector(127 downto 0);
signal key:std_logic_vector(127 downto 0);
signal k_valid,c_valid,out_valid:std_logic;
signal ready:std_logic;
begin
uut:AES_decrypter
port map(cipher=>cipher,text_out=>text_out,key=>key,k_valid=>k_valid,c_valid=>c_valid,out_valid=>out_valid,clk=>clk,reset=>reset,ready=>ready);
clk_process:process
begin
clk<='1';
wait for clk_period/2;
clk<='0';
wait for clk_period/2;
end process;
tb_process:process
variable LW : line;
variable error: integer:=0;
begin
reset<='1';
k_valid<='0';
c_valid<='0';
wait for 5*clk_period;
reset<='0';
wait for clk_period;
if(ready/='1') then
wait until ready='1';
end if;
k_valid<='1';
key<=x"1234567890abcdef1234567890abcdef";
wait for clk_period;
k_valid<='0';
--Test 1
wait until ready='1';
--Plain text : 0xAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
cipher<=x"220dfcbbe717ae16ebcf69615a996adb";
c_valid<='1';
wait for clk_period;
c_valid<='0';
wait until out_valid='1';
wait for 1 ns;
if(x"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA" /= text_out) then
write(LW,string'("Decryption Error!!!"));
write(LW,string'(" Expected : 0xAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Received : 0x"));
hwrite(LW,text_out);
writeline(output,LW);
error:=1;
end if;
 
--Test 2
wait until ready='1';
--Plain Text : 0xBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB
cipher<=x"e9f386223ce53e52891c113d048145ec";
c_valid<='1';
wait for clk_period;
c_valid<='0';
wait until out_valid='1';
wait for 1 ns; --Delta delay
if(x"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB" /= text_out) then
write(LW,string'("Decryption Error!!!"));
write(LW,string'(" Expected : 0xBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB Received : 0x"));
hwrite(LW,text_out);
writeline(output,LW);
error:=1;
end if;
--Test 3
wait until ready='1';
--Plain Text : 0xCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
cipher<=x"5426f624ac8c7c9eea54f55103a6e3ab";
c_valid<='1';
wait for clk_period;
c_valid<='0';
 
wait until out_valid='1';
wait for 1 ns;
if(x"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC" /= text_out) then
write(LW,string'("Decryption Error!!!"));
write(LW,string'(" Expected : 0xCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC Received : 0x"));
hwrite(LW,text_out);
writeline(output,LW);
error:=1;
end if;
if(error = 0) then
write(LW,string'("********************************************"));
writeline(output,LW);
write(LW, string'(" All test case passed!!! "));
writeline(output,LW);
write(LW,string'("********************************************"));
writeline(output,LW);
else
write(LW,string'("********************************************"));
writeline(output,LW);
write(LW, string'(" Some test case failed!!!! "));
writeline(output,LW);
write(LW,string'("********************************************"));
writeline(output,LW);
end if;
assert false report"This is end of simulation not test failure!!!" severity failure; --End simulation
wait;
end process;
 
end beh_tb_AES_decrypt;
/aes_decry_ip_128bit/trunk/testbench/misc_tb/tb_one_round_decrypt.vhd
0,0 → 1,33
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_one_round_decrypt is
end tb_one_round_decrypt;
 
architecture beh_tb_one_round_decrypt of tb_one_round_decrypt is
component one_round_decrypt
port(
cipher : in std_logic_vector(127 downto 0);
text_out: out std_logic_vector(127 downto 0);
round_key: in std_logic_vector(127 downto 0)
);
end component;
signal cipher,text_out: std_logic_vector(127 downto 0);
signal round_key:std_logic_vector(127 downto 0);
begin
uut:one_round_decrypt
port map(cipher=>cipher,text_out=>text_out,round_key=>round_key);
process
begin
wait for 50 ns;
cipher<=x"7ad5fda789ef4e272bca100b3d9ff59f";
round_key<=x"549932d1f08557681093ed9cbe2c974e";
wait for 10 ns;
cipher<=x"b458124c68b68a014b99f82e5f15554c";
round_key<=x"5e390f7df7a69296a7553dc10aa31f6b";
wait;
end process;
 
end beh_tb_one_round_decrypt;
/aes_decry_ip_128bit/trunk/testbench/misc_tb/tb_key_scheduler.vhd
0,0 → 1,91
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_key_schedular is
end tb_key_schedular;
 
architecture beh_tb_key_schedular of tb_key_schedular is
 
component key_scheduler
port(
key_in : in std_logic_vector(127 downto 0);
key_out : out std_logic_vector(127 downto 0);
valid_in : in std_logic;--Input key is valid
key_ready : out std_logic;
round: in std_logic_vector(3 downto 0);
clk,reset: in std_logic
);
end component;
constant clk_period: time := 10 ns;
signal key_in,key_out:std_logic_vector(127 downto 0);
signal valid_in,key_ready,reset,clk : std_logic;
signal round : std_logic_vector(3 downto 0);
begin
 
uut:key_scheduler
port map(key_in=>key_in,key_out=>key_out,valid_in=>valid_in,key_ready=>key_ready,round=>round,reset=>reset,clk=>clk);
clk_process:process
begin
clk<='1';
wait for clk_period/2;
clk<='0';
wait for clk_period/2;
end process;
stimulus:process
begin
reset<='1';
valid_in<='0';
round <=(others =>'0');
wait for 5*clk_period;
reset<='0';
wait for 2 ns;
valid_in <= '1';
key_in<=x"000102030405060708090a0b0c0d0e0f";
wait until key_ready <= '1';
wait for clk_period;
round <= "0000";
wait for clk_period;
round <= "0001";
wait for clk_period;
round <= "0010";
wait for clk_period;
round <= "0011";
wait for clk_period;
round <= "0100";
wait for clk_period;
round <= "0101";
wait for clk_period;
round <= "0110";
wait for clk_period;
round <= "0111";
wait for clk_period;
round <= "1000";
wait for clk_period;
round <= "1001";
wait for clk_period;
round <= "1010";
wait for 20*clk_period;
round <= "1000";
wait;
end process;
 
end beh_tb_key_schedular;
/aes_decry_ip_128bit/trunk/testbench/simulate.do
0,0 → 1,21
vlib work
vcom ../key_schd/*.vhd
vcom ../*.vhd
vcom ./*.vhd
vsim -novopt tb_AES_decrypt
 
add wave -noupdate -format Logic -radix unsigned /tb_AES_decrypt/clk
add wave -noupdate -format Logic -radix unsigned /tb_AES_decrypt/reset
 
add wave -noupdate -divider input
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/cipher
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/key
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/k_valid
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/c_valid
 
add wave -noupdate -divider output
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/text_out
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/ready
add wave -noupdate -format Logic -radix hex /tb_AES_decrypt/out_valid
 
run -all
/aes_decry_ip_128bit/trunk/testbench/Reame.txt
0,0 → 1,11
This folder has the test-bench for AES decryption IP and ModelSim script file to run the simulation.
 
Simulation Option 1(Using this scripts):
Launch ModelSim from the same folder where simulate.do is saved and run this script in ModelSim terminal.
Modelsim> do simulate.do
 
Simulation Option 2:
Open ModelSim GUI and add source code interactively and run simulation.
 
 
Note : There are few more test bench VHDL files to test individual components of this IP.Please check misc_tb folder
/aes_decry_ip_128bit/trunk/testbench/tb_AES_decrypt.vhd
0,0 → 1,168
--************************************************************
--Copyright 2015, Ganesh Hegde < ghegde@opencores.org >
--
--This source file may be used and distributed without
--restriction provided that this copyright statement is not
--removed from the file and that any derivative work contains
--the original copyright notice and the associated disclaimer.
--
--This source is distributed in the hope that it will be
--useful, but WITHOUT ANY WARRANTY; without even the implied
--warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--PURPOSE. See the GNU Lesser General Public License for more
--details.
--
--You should have received a copy of the GNU Lesser General
--Public License along with this source; if not, download it
--from http://www.opencores.org/lgpl.shtml
--
--*************************************************************
--This file is a test bench for AES decryption IP.
--*************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
 
entity tb_AES_decrypt is
end tb_AES_decrypt;
 
architecture beh_tb_AES_decrypt of tb_AES_decrypt is
component AES_decrypter
port (
cipher: in std_logic_vector(127 downto 0);
text_out: out std_logic_vector(127 downto 0);
key: in std_logic_vector(127 downto 0);
k_valid,c_valid: in std_logic;--Asserted when either key, cipher is valid
ready:out std_logic;--Asserted high when IP is ready to accept the data(key or Cipher)
out_valid: out std_logic;--out_valid:Asserted high when decrypted cipher is on the bus
clk,reset: in std_logic
);
end component;
constant clk_period: time := 10 ns;
signal reset,clk:std_logic;
signal cipher,text_out: std_logic_vector(127 downto 0);
signal key:std_logic_vector(127 downto 0);
signal k_valid,c_valid,out_valid:std_logic;
signal ready:std_logic;
begin
uut:AES_decrypter
port map(cipher=>cipher,text_out=>text_out,key=>key,k_valid=>k_valid,c_valid=>c_valid,out_valid=>out_valid,clk=>clk,reset=>reset,ready=>ready);
clk_process:process
begin
clk<='1';
wait for clk_period/2;
clk<='0';
wait for clk_period/2;
end process;
tb_process:process
variable LW : line;
variable error: integer:=0;
begin
reset<='1';
k_valid<='0';
c_valid<='0';
wait for 5*clk_period;
reset<='0';
wait for clk_period;
if(ready/='1') then
wait until ready='1';
end if;
k_valid<='1';
key<=x"1234567890abcdef1234567890abcdef";
wait for clk_period;
k_valid<='0';
--Test 1
wait until ready='1';
--Plain text : 0xAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
cipher<=x"220dfcbbe717ae16ebcf69615a996adb";
c_valid<='1';
wait for clk_period;
c_valid<='0';
wait until out_valid='1';
wait for 1 ns;
if(x"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA" /= text_out) then
write(LW,string'("Decryption Error!!!"));
write(LW,string'(" Expected : 0xAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Received : 0x"));
hwrite(LW,text_out);
writeline(output,LW);
error:=1;
end if;
 
--Test 2
wait until ready='1';
--Plain Text : 0xBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB
cipher<=x"e9f386223ce53e52891c113d048145ec";
c_valid<='1';
wait for clk_period;
c_valid<='0';
wait until out_valid='1';
wait for 1 ns; --Delta delay
if(x"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB" /= text_out) then
write(LW,string'("Decryption Error!!!"));
write(LW,string'(" Expected : 0xBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB Received : 0x"));
hwrite(LW,text_out);
writeline(output,LW);
error:=1;
end if;
--Test 3
wait until ready='1';
--Plain Text : 0xCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
cipher<=x"5426f624ac8c7c9eea54f55103a6e3ab";
c_valid<='1';
wait for clk_period;
c_valid<='0';
 
wait until out_valid='1';
wait for 1 ns;
if(x"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC" /= text_out) then
write(LW,string'("Decryption Error!!!"));
write(LW,string'(" Expected : 0xCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC Received : 0x"));
hwrite(LW,text_out);
writeline(output,LW);
error:=1;
end if;
if(error = 0) then
write(LW,string'("********************************************"));
writeline(output,LW);
write(LW, string'(" All test case passed!!! "));
writeline(output,LW);
write(LW,string'("********************************************"));
writeline(output,LW);
else
write(LW,string'("********************************************"));
writeline(output,LW);
write(LW, string'(" Some test case failed!!!! "));
writeline(output,LW);
write(LW,string'("********************************************"));
writeline(output,LW);
end if;
assert false report"This is end of simulation not test failure!!!" severity failure; --End simulation
wait;
end process;
 
end beh_tb_AES_decrypt;

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