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spacewiresystemc/trunk/doc/SPACE_WIRE_TEST_SUIT_TUTORIAL.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/pdf \ No newline at end of property Index: spacewiresystemc/trunk/doc/SPW_ULTRA_LIGHT.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/pdf Index: spacewiresystemc/trunk/doc/SPW_ULTRA_LIGHT.pdf =================================================================== --- spacewiresystemc/trunk/doc/SPW_ULTRA_LIGHT.pdf (nonexistent) +++ spacewiresystemc/trunk/doc/SPW_ULTRA_LIGHT.pdf (revision 5)

spacewiresystemc/trunk/doc/SPW_ULTRA_LIGHT.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/pdf \ No newline at end of property Index: spacewiresystemc/trunk/rtl/RTL_VA/SPW_TOP.sv =================================================================== --- spacewiresystemc/trunk/rtl/RTL_VA/SPW_TOP.sv (nonexistent) +++ spacewiresystemc/trunk/rtl/RTL_VA/SPW_TOP.sv (revision 5) @@ -0,0 +1,29 @@ +module SpwTCR( + input CLOCK, + input RESETn, + input LINK_START, + input LINK_DISABLE, + input AUTOSTART, + output logic [2:0] CURRENTSTATE, + output logic [10:0] FLAGS, + input [8:0] DATA_I, + input WR_DATA, + output logic TX_FULL, + output logic [8:0] DATA_O, + input RD_DATA, + output logic RX_EMPTY, + output logic TICK_OUT, + output logic [7:0] TIME_OUT, + input TICK_IN, + input [7:0] TIME_IN, + input [6:0] TX_CLK_DIV, + input SPILL_ENABLE, + input Din, + input Sin, + output logic Dout, + output logic Sout +); + + + +endmodule Index: spacewiresystemc/trunk/rtl/RTL_VB/fsm_spw.v =================================================================== --- spacewiresystemc/trunk/rtl/RTL_VB/fsm_spw.v (nonexistent) +++ spacewiresystemc/trunk/rtl/RTL_VB/fsm_spw.v (revision 5) @@ -0,0 +1,279 @@ +//+FHDR------------------------------------------------------------------------ +//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved +//GLADIC Open Source RTL +//----------------------------------------------------------------------------- +//FILE NAME : +//DEPARTMENT : IC Design / Verification +//AUTHOR : Felipe Fernandes da Costa +//AUTHOR’S EMAIL : +//----------------------------------------------------------------------------- +//RELEASE HISTORY +//VERSION DATE AUTHOR DESCRIPTION +//1.0 YYYY-MM-DD name +//----------------------------------------------------------------------------- +//KEYWORDS : General file searching keywords, leave blank if none. +//----------------------------------------------------------------------------- +//PURPOSE : ECSS_E_ST_50_12C_31_july_2008 +//----------------------------------------------------------------------------- +//PARAMETERS +//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS +//e.g.DATA_WIDTH [32,16] : width of the data : 32: +//----------------------------------------------------------------------------- +//REUSE ISSUES +//Reset Strategy : +//Clock Domains : +//Critical Timing : +//Test Features : +//Asynchronous I/F : +//Scan Methodology : +//Instantiations : +//Synthesizable (y/n) : +//Other : +//-FHDR------------------------------------------------------------------------ + +`timescale 1ns/1ns + +module FSM_SPW ( + input pclk, + input resetn, + + //fsm status control + input auto_start, + input link_start, + input link_disable, + + //rx status input control + input rx_error, + input rx_credit_error, + input rx_got_bit, + input rx_got_null, + input rx_got_nchar, + input rx_got_time_code, + input rx_got_fct, + output rx_resetn, + + //tx status control + output enable_tx, + output send_null_tx, + output send_fct_tx, + + output [5:0] fsm_state + + ); + +localparam [5:0] error_reset = 6'b00_0000, + error_wait = 6'b00_0001, + ready = 6'b00_0010, + started = 6'b00_0100, + connecting = 6'b00_1000, + run = 6'b01_0000; + + reg [5:0] state_fsm; + reg [5:0] next_state_fsm; + + reg [11:0] after128us; + reg [11:0] after64us; + reg [11:0] after850ns; + +// +assign enable_tx = (!resetn | state_fsm == error_reset | state_fsm == error_wait)?1'b0:1'b1; + +// +assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1; + +// +assign send_null_tx = (next_state_fsm == started | next_state_fsm == connecting | next_state_fsm == run)?1'b1:1'b0; + +// +assign send_fct_tx = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0; + +// +assign fsm_state = state_fsm; + +always@(*) +begin + + next_state_fsm = state_fsm; + + case(state_fsm) + error_reset: + begin + + if(after64us == 12'd639) + begin + next_state_fsm = error_wait; + end + else + begin + next_state_fsm = error_reset; + end + + end + error_wait: + begin + + if(after128us == 12'd1279) + begin + next_state_fsm = ready; + end + else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code) + begin + next_state_fsm = error_reset; + end + + end + ready: + begin + + if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code) + begin + next_state_fsm = error_reset; + end + else if((!link_disable) && (link_start |(auto_start && rx_got_null))) + begin + next_state_fsm = started; + end + + end + started: + begin + + if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 ) + begin + next_state_fsm = error_reset; + end + else if(rx_got_null && rx_got_bit) + begin + next_state_fsm = connecting; + end + + end + connecting: + begin + + if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 ) + begin + next_state_fsm = error_reset; + end + else if(rx_got_fct) + begin + next_state_fsm = run; + end + + end + run: + begin + + if(rx_error | rx_credit_error | link_disable | after850ns == 12'd85) + begin + next_state_fsm = error_reset; + end + else + begin + next_state_fsm = run; + end + + end + endcase +end + +always@(posedge pclk) +begin + if(!resetn) + begin + state_fsm <= error_reset; + end + else + begin + + state_fsm <= next_state_fsm; + + case(state_fsm) + error_reset: + begin + end + error_wait: + begin + end + ready: + begin + end + started: + begin + end + connecting: + begin + end + run: + begin + end + endcase + end +end + +always@(posedge pclk) +begin + + if(!resetn) + begin + after128us <= 12'd0; + end + else + begin + if(state_fsm == error_wait | state_fsm == started | state_fsm == connecting) + begin + if(after128us < 12'd1279) + after128us <= after128us + 12'd1; + else + after128us <= 12'd0; + end + else + begin + after128us <= 12'd0; + end + end + +end + +always@(posedge pclk) +begin + + if(!resetn) + begin + after64us <= 12'd0; + end + else + begin + if(state_fsm == error_reset && (auto_start | link_start)) + begin + if(after64us < 12'd639) + after64us <= after64us + 12'd1; + else + after64us <= 12'd0; + end + else + begin + after64us <= 12'd0; + end + end + +end + +always@(posedge pclk) +begin + + if(!resetn | rx_got_bit) + begin + after850ns <= 12'd0; + end + else + begin + if(after850ns < 12'd85 && (auto_start | link_start)) + after850ns <= after850ns + 12'd1; + else + after850ns <= 12'd0; + end + +end + +endmodule Index: spacewiresystemc/trunk/rtl/RTL_VB/rx_spw.v =================================================================== --- spacewiresystemc/trunk/rtl/RTL_VB/rx_spw.v (nonexistent) +++ spacewiresystemc/trunk/rtl/RTL_VB/rx_spw.v (revision 5) @@ -0,0 +1,338 @@ +//+FHDR------------------------------------------------------------------------ +//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved +//GLADIC Open Source RTL +//----------------------------------------------------------------------------- +//FILE NAME : +//DEPARTMENT : IC Design / Verification +//AUTHOR : Felipe Fernandes da Costa +//AUTHOR’S EMAIL : +//----------------------------------------------------------------------------- +//RELEASE HISTORY +//VERSION DATE AUTHOR DESCRIPTION +//1.0 YYYY-MM-DD name +//----------------------------------------------------------------------------- +//KEYWORDS : General file searching keywords, leave blank if none. +//----------------------------------------------------------------------------- +//PURPOSE : ECSS_E_ST_50_12C_31_july_2008 +//----------------------------------------------------------------------------- +//PARAMETERS +//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS +//e.g.DATA_WIDTH [32,16] : width of the data : 32: +//----------------------------------------------------------------------------- +//REUSE ISSUES +//Reset Strategy : +//Clock Domains : +//Critical Timing : +//Test Features : +//Asynchronous I/F : +//Scan Methodology : +//Instantiations : +//Synthesizable (y/n) : +//Other : +//-FHDR------------------------------------------------------------------------ + +`timescale 1ns/1ns + +module RX_SPW ( + input rx_din, + input rx_sin, + + input rx_resetn, + + output rx_error, + + output rx_got_bit, + output rx_got_null, + output rx_got_nchar, + output rx_got_time_code, + output rx_got_fct, + + output [8:0] rx_data_flag, + output rx_buffer_write, + + output [7:0] rx_time_out, + output rx_tick_out + ); + + wire [4:0] counter; + + reg [4:0] counter_pos; + reg [4:0] counter_neg; + + wire posedge_clk; + wire negedge_clk; + + wire [3:0] control; + wire [9:0] data; + wire [9:0] timecode; + + reg [3:0] control_l_a; + reg [9:0] data_l_a; + reg [9:0] timecode_l_a; + + reg [2:0] control_l_r; + reg [9:0] data_l_r; + reg [9:0] timecode_l_r; + + reg parity_error; + + reg control_found; + reg data_found; + reg time_code_found; + + reg last_was_control; + reg last_was_data; + reg last_was_time_code; + + wire data_control_up; + + assign data_control_up = (counter == 5'd3 & control[2:2])?1'b1: + (counter == 5'd9 & !control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1: + (counter == 5'd9 & control_l_a[2:0] == 3'd7)?1'b1:1'b0; + + assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0; + assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0; + + assign counter = counter_pos + counter_neg; + + assign data[9:9] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:data[9:9]; + assign data[8:8] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:data[8:8]; + assign data[0:0] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:data[0:0]; + assign data[1:1] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:data[1:1]; + assign data[2:2] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:data[2:2]; + assign data[3:3] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:data[3:3]; + assign data[4:4] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:data[4:4]; + assign data[5:5] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:data[5:5]; + assign data[6:6] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:data[6:6]; + assign data[7:7] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:data[7:7]; + + assign timecode[0:0] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:timecode[0:0]; + assign timecode[1:1] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:timecode[1:1]; + assign timecode[2:2] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:timecode[2:2]; + assign timecode[3:3] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:timecode[3:3]; + assign timecode[4:4] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:timecode[4:4]; + assign timecode[5:5] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:timecode[5:5]; + assign timecode[6:6] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:timecode[6:6]; + assign timecode[7:7] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:timecode[7:7]; + assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8]; + assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9]; + + assign control[0:0] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:control[0:0]; + assign control[1:1] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:control[1:1]; + assign control[2:2] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:control[2:2]; + assign control[3:3] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:control[3:3]; + + assign rx_got_fct = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0; + assign rx_got_nchar = (!rx_resetn)?1'b0:(!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0; + assign rx_got_time_code = (!rx_resetn)?1'b0:(counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0; + assign rx_got_null = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0; + assign rx_got_bit = (posedge_clk)?1'b1:1'b0; + + assign rx_error = (parity_error)?1'b1: + ((counter == 5'd9 | counter == 5'd4) & !rx_got_fct & !rx_got_nchar & !rx_got_time_code & !rx_got_null & !last_was_control)?1'b1:1'b0; + + assign rx_data_flag = (rx_got_nchar)?data[8:0]:data_l_a[8:0]; + assign rx_buffer_write = (rx_got_nchar & data_control_up)?1'b1:1'b0; + + assign rx_time_out = (rx_got_time_code)?timecode[7:0]:timecode_l_a[7:0]; + assign rx_tick_out = (rx_got_time_code & data_control_up)?1'b1:1'b0; + + +always@(posedge posedge_clk or negedge rx_resetn or posedge last_was_control) +begin + if(!rx_resetn | last_was_control) + begin + counter_pos <= 5'd0; + end + else + begin + if(counter == 5'd4 & control[2:2]) + begin + counter_pos <= 5'd0; + end + else if(counter == 5'd9) + begin + counter_pos <= 5'd0; + end + else + begin + counter_pos <= counter_pos + 5'd1; + end + end +end + +// +always@(posedge negedge_clk or negedge rx_resetn or posedge last_was_control) +begin + if(!rx_resetn | last_was_control ) + begin + counter_neg <= 5'd0; + end + else + begin + if(counter == 5'd4 & control[2:2]) + begin + counter_neg <= 5'd0; + end + else if(counter == 5'd9) + begin + counter_neg <= 5'd0; + end + else + begin + counter_neg <= counter_neg + 5'd1; + end + end +end + +//parity error +always@(*) +begin + + parity_error = 1'b0; + + if(control_found && last_was_control) + begin + if(!(control_l_a[2]^control_l_r[0]^control_l_r[1]) != control_l_a[3]) + begin + parity_error = 1'b1; + end + end + else if(control_found && last_was_data) + begin + if(!(data_l_a[8]^control_l_r[0]^control_l_r[1]) != data_l_a[9]) + begin + parity_error = 1'b1; + end + end + else if(control_found && last_was_time_code) + begin + if(!(timecode_l_a[8]^control_l_r[0]^control_l_r[1]) != timecode_l_a[9]) + begin + parity_error = 1'b1; + end + end + else if(data_found && last_was_control) + begin + if(!(control_l_a[2]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != control_l_a[3]) + begin + parity_error = 1'b1; + end + end + else if(data_found && last_was_data) + begin + if(!(data_l_a[8]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != data_l_a[9]) + begin + parity_error = 1'b1; + end + end + else if(data_found && last_was_time_code) + begin + if(!(data_l_r[8]^timecode_l_a[0]^timecode_l_a[1]^timecode_l_a[2]^timecode_l_a[3]^timecode_l_a[4]^timecode_l_a[5]^timecode_l_a[6]^timecode_l_a[7]) != data_l_r[9]) + begin + parity_error = 1'b1; + end + end + else if(time_code_found && last_was_data) + begin + if(!(timecode_l_r[8]^data_l_a[0]^data_l_a[1]^data_l_a[2]^data_l_a[3]^data_l_a[4])^data_l_a[5]^data_l_a[6]^data_l_a[7] != timecode_l_r[9]) + begin + parity_error = 1'b1; + end + end + else if(time_code_found && last_was_control) + begin + if(!(control_l_a[2]^timecode_l_r[0]^timecode_l_r[1]^timecode_l_r[2]^timecode_l_r[3]^timecode_l_r[4]^timecode_l_r[5]^timecode_l_r[6]^timecode_l_r[7]) != control_l_a[3]) + begin + parity_error = 1'b1; + end + end +end + +// +always@(*) +begin + + last_was_control = 1'b0; + last_was_data = 1'b0; + last_was_time_code= 1'b0; + + if(counter == 5'd4 & control[2:2]) + begin + last_was_control = 1'b1; + end + else if(counter == 5'd9 && !control_l_a[2:2] && data_l_a[2:0] != 3'd7) + begin + last_was_data = 1'b1; + end + else if(counter == 5'd9 && control_l_a[2:0] == 3'd7) + begin + last_was_time_code= 1'b1; + end + +end + +// +always@(posedge data_control_up or negedge rx_resetn) +begin + + if(!rx_resetn) + begin + control_found <= 1'b0; + data_found <= 1'b0; + time_code_found <= 1'b0; + end + else + begin + control_found <= last_was_control; + data_found <= last_was_data; + time_code_found <= last_was_time_code; + end + +end + +// +always@(posedge last_was_control or negedge rx_resetn) +begin + if(!rx_resetn) + begin + control_l_a <= 4'd4; + control_l_r <= 3'd4; + end + else + begin + control_l_a <= control; + control_l_r <= control_l_a[2:0]; + end +end + +always@(posedge last_was_data or negedge rx_resetn) +begin + if(!rx_resetn) + begin + data_l_a <= 10'd0; + data_l_r <= 10'd0; + end + else + begin + data_l_a <= data; + data_l_r <= data_l_a; + end +end + +always@(posedge last_was_time_code or negedge rx_resetn) +begin + if(!rx_resetn) + begin + timecode_l_a <= 10'd0; + timecode_l_r <= 10'd0; + end + else + begin + timecode_l_a <= timecode; + timecode_l_r <= timecode_l_a; + end +end + + +endmodule Index: spacewiresystemc/trunk/rtl/RTL_VB/top_spw_ultra_light.v =================================================================== --- spacewiresystemc/trunk/rtl/RTL_VB/top_spw_ultra_light.v (nonexistent) +++ spacewiresystemc/trunk/rtl/RTL_VB/top_spw_ultra_light.v (revision 5) @@ -0,0 +1,158 @@ +//+FHDR------------------------------------------------------------------------ +//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved +//GLADIC Open Source RTL +//----------------------------------------------------------------------------- +//FILE NAME : +//DEPARTMENT : IC Design / Verification +//AUTHOR : Felipe Fernandes da Costa +//AUTHOR’S EMAIL : +//----------------------------------------------------------------------------- +//RELEASE HISTORY +//VERSION DATE AUTHOR DESCRIPTION +//1.0 YYYY-MM-DD name +//----------------------------------------------------------------------------- +//KEYWORDS : General file searching keywords, leave blank if none. +//----------------------------------------------------------------------------- +//PURPOSE : ECSS_E_ST_50_12C_31_july_2008 +//----------------------------------------------------------------------------- +//PARAMETERS +//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS +//e.g.DATA_WIDTH [32,16] : width of the data : 32: +//----------------------------------------------------------------------------- +//REUSE ISSUES +//Reset Strategy : +//Clock Domains : +//Critical Timing : +//Test Features : +//Asynchronous I/F : +//Scan Methodology : +//Instantiations : +//Synthesizable (y/n) : +//Other : +//-FHDR------------------------------------------------------------------------ + +`timescale 1ns/1ns + +module top_spw_ultra_light( + + input pclk, + input ppllclk, + input resetn, + + input top_sin, + input top_din, + + input top_auto_start, + input top_link_start, + input top_link_disable, + + input top_tx_write, + input [8:0] top_tx_data, + + input top_tx_tick, + input [7:0] top_tx_time, + + input credit_error_rx, + input top_send_fct_now, + + output [8:0] datarx_flag, + output buffer_write, + + output [7:0] time_out, + output tick_out, + + output top_dout, + output top_sout, + + output top_tx_ready, + output top_tx_ready_tick, + + output [5:0] top_fsm + + ); + + wire resetn_rx; + wire error_rx; + + wire got_bit_rx; + wire got_null_rx; + wire got_nchar_rx; + wire got_time_code_rx; + wire got_fct_rx; + + wire enable_tx; + wire send_null_tx; + wire send_fct_tx; + + + FSM_SPW FSM( + .pclk(pclk), + .resetn(resetn), + + .auto_start(top_auto_start), + .link_start(top_link_start), + .link_disable(top_link_disable), + + .rx_error(error_rx), + .rx_credit_error(credit_error_rx), + .rx_got_bit(got_bit_rx), + .rx_got_null(got_null_rx), + .rx_got_nchar(got_nchar_rx), + .rx_got_time_code(got_time_code_rx), + .rx_got_fct(got_fct_rx), + .rx_resetn(resetn_rx), + + .enable_tx(enable_tx), + .send_null_tx(send_null_tx), + .send_fct_tx(send_fct_tx), + + .fsm_state(top_fsm) + + ); + + + RX_SPW RX( + .rx_din(top_din), + .rx_sin(top_sin), + + .rx_resetn(resetn_rx), + + .rx_error(error_rx), + .rx_got_bit(got_bit_rx), + .rx_got_null(got_null_rx), + .rx_got_nchar(got_nchar_rx), + .rx_got_time_code(got_time_code_rx), + .rx_got_fct(got_fct_rx), + + .rx_data_flag(datarx_flag), + .rx_buffer_write(buffer_write), + + .rx_time_out(time_out), + .rx_tick_out(tick_out) + + ); + + TX_SPW TX( + .pclk_tx(ppllclk), + + .data_tx_i(top_tx_data), + .txwrite_tx(top_tx_write), + + .timecode_tx_i(top_tx_time), + .tickin_tx(top_tx_tick), + + .enable_tx(enable_tx), + .send_null_tx(send_null_tx), + .send_fct_tx(send_fct_tx), + + .gotfct_tx(got_fct_rx), + .send_fct_now(top_send_fct_now), + + .tx_dout(top_dout), + .tx_sout(top_sout), + + .ready_tx_data(top_tx_ready), + .ready_tx_timecode(top_tx_ready_tick) + ); + +endmodule Index: spacewiresystemc/trunk/rtl/RTL_VB/tx_spw.v =================================================================== --- spacewiresystemc/trunk/rtl/RTL_VB/tx_spw.v (nonexistent) +++ spacewiresystemc/trunk/rtl/RTL_VB/tx_spw.v (revision 5) @@ -0,0 +1,610 @@ +//+FHDR------------------------------------------------------------------------ +//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved +//GLADIC Open Source RTL +//----------------------------------------------------------------------------- +//FILE NAME : +//DEPARTMENT : IC Design / Verification +//AUTHOR : Felipe Fernandes da Costa +//AUTHOR’S EMAIL : +//----------------------------------------------------------------------------- +//RELEASE HISTORY +//VERSION DATE AUTHOR DESCRIPTION +//1.0 YYYY-MM-DD name +//----------------------------------------------------------------------------- +//KEYWORDS : General file searching keywords, leave blank if none. +//----------------------------------------------------------------------------- +//PURPOSE : ECSS_E_ST_50_12C_31_july_2008 +//----------------------------------------------------------------------------- +//PARAMETERS +//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS +//e.g.DATA_WIDTH [32,16] : width of the DATA : 32: +//----------------------------------------------------------------------------- +//REUSE ISSUES +//Reset Strategy : +//Clock Domains : +//Critical Timing : +//Test Features : +//Asynchronous I/F : +//Scan Methodology : +//Instantiations : +//Synthesizable (y/n) : +//Other : +//-FHDR------------------------------------------------------------------------ + +`timescale 1ns/1ns + +module TX_SPW ( + input pclk_tx, + // + input [8:0] data_tx_i, + input txwrite_tx, + // + input [7:0] timecode_tx_i, + input tickin_tx, + // + input enable_tx, + input send_null_tx, + input send_fct_tx, + + // + input gotfct_tx, + input send_fct_now, + // + output reg tx_dout, + output reg tx_sout, + // + output ready_tx_data, + output ready_tx_timecode + + ); + +localparam [2:0] tx_spw_start = 3'b000, + tx_spw_null = 3'b001, + tx_spw_null_fct = 3'b010, + tx_spw_full = 3'b100; + +localparam [5:0] NULL = 6'b000001, + FCT = 6'b000010, + EOP = 6'b000100, + EEP = 6'b001000, + DATA = 6'b010000, + TIMEC = 6'b100000; + + reg [2:0] state_tx; + reg [2:0] next_state_tx; + + reg [7:0] null_s; + reg [3:0] fct_s; + reg [3:0] eop_s; + reg [3:0] eep_s; + reg [13:0] timecode_s; + + reg [5:0] last_type; + reg [8:0] txdata_flagctrl_tx_last; + reg [7:0] last_timein_control_flag_tx; + + reg first_time; + + reg enable_null; + reg enable_fct; + reg enable_n_char; + reg enable_time_code; + + reg [2:0] fct_send; + reg [2:0] fct_flag; + reg [5:0] fct_counter; + reg last_tx_dout; + reg last_tx_sout; + //reg first_counter_ctr; + + reg [3:0] global_counter_transfer; + +assign ready_tx_timecode = (enable_time_code & global_counter_transfer == 14)?1'b1:1'b0; + +assign ready_tx_data = (enable_n_char & global_counter_transfer == 4'd10 & !data_tx_i[8])?1'b1: + (enable_n_char & global_counter_transfer == 4'd4 & data_tx_i[8])?1'b1:1'b0; + +always@(*) +begin + tx_dout = 1'b0; + + if(!enable_tx) + begin + tx_dout = 1'b0; + end + else if( enable_null & first_time & global_counter_transfer == 4'd0) + begin + tx_dout = null_s[7]; + end + else if( enable_null & !first_time & last_type == NULL & global_counter_transfer == 4'd0) + begin + tx_dout = !(null_s[6]^null_s[0]^null_s[1]); + end + else if( enable_null & !first_time & last_type == FCT & global_counter_transfer == 4'd0) + begin + tx_dout = !(null_s[6]^fct_s[0]^fct_s[1]); + end + else if( enable_null & !first_time & last_type == EOP & global_counter_transfer == 4'd0) + begin + tx_dout = !(null_s[6]^eop_s[0]^eop_s[1]); + end + else if( enable_null & !first_time & last_type == EEP & global_counter_transfer == 4'd0) + begin + tx_dout = !(null_s[6]^eep_s[0]^eep_s[1]); + end + else if( enable_null & !first_time & last_type == DATA & global_counter_transfer == 4'd0) + begin + tx_dout = !(null_s[6]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]); + end + else if( enable_null & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0) + begin + tx_dout = !(null_s[6]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]); + end + else if( enable_null & !first_time & global_counter_transfer == 4'd1) + begin + tx_dout = null_s[6]; + end + else if( enable_null & !first_time & global_counter_transfer == 4'd2) + begin + tx_dout = null_s[5]; + end + else if( enable_null & !first_time & global_counter_transfer == 4'd3) + begin + tx_dout = null_s[4]; + end + else if( enable_null & !first_time & global_counter_transfer == 4'd4) + begin + tx_dout = null_s[3]; + end + else if( enable_null & !first_time & global_counter_transfer == 4'd5) + begin + tx_dout = null_s[2]; + end + else if( enable_null & !first_time & global_counter_transfer == 4'd6) + begin + tx_dout = null_s[1]; + end + else if( enable_null & !first_time & global_counter_transfer == 4'd7) + begin + tx_dout = null_s[0]; + end + else if( enable_fct & !first_time & last_type == NULL & global_counter_transfer == 4'd0) + begin + tx_dout = !(fct_s[2]^null_s[0]^null_s[1]); + end + else if( enable_fct & !first_time & last_type == FCT & global_counter_transfer == 4'd0) + begin + tx_dout = !(fct_s[2]^fct_s[0]^fct_s[1]); + end + else if( enable_fct & !first_time & last_type == EOP & global_counter_transfer == 4'd0) + begin + tx_dout = !(fct_s[2]^eop_s[0]^eop_s[1]); + end + else if( enable_fct & !first_time & last_type == EEP & global_counter_transfer == 4'd0) + begin + tx_dout = !(fct_s[2]^eep_s[0]^eep_s[1]); + end + else if ( enable_fct & !first_time & last_type == DATA & global_counter_transfer == 4'd0) + begin + tx_dout = !(fct_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]); + end + else if( enable_fct & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0) + begin + tx_dout = !(fct_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]); + end + else if( enable_fct & !first_time & global_counter_transfer == 4'd1) + begin + tx_dout = fct_s[2]; + end + else if( enable_fct & !first_time & global_counter_transfer == 4'd2) + begin + tx_dout = fct_s[1]; + end + else if( enable_fct & !first_time & global_counter_transfer == 4'd3) + begin + tx_dout = fct_s[0]; + end + else if( enable_time_code & !first_time & last_type == NULL & global_counter_transfer == 4'd0) + begin + tx_dout = !(timecode_s[12]^null_s[0]^null_s[1]); + end + else if( enable_time_code & !first_time & last_type == FCT & global_counter_transfer == 4'd0) + begin + tx_dout = !(timecode_s[12]^fct_s[0]^fct_s[1]); + end + else if ( enable_time_code & !first_time & last_type == EOP & global_counter_transfer == 4'd0) + begin + tx_dout = !(timecode_s[12]^eop_s[0]^eop_s[1]); + end + else if( enable_time_code & !first_time & last_type == EEP & global_counter_transfer == 4'd0) + begin + tx_dout = !(timecode_s[12]^eep_s[0]^eep_s[1]); + end + else if( enable_time_code & !first_time & last_type == DATA & global_counter_transfer == 4'd0) + begin + tx_dout = !(timecode_s[12]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]); + end + else if( enable_time_code & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0) + begin + tx_dout = !(timecode_s[12]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]); + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd1) + begin + tx_dout = timecode_s[12]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd2) + begin + tx_dout = timecode_s[11]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd3) + begin + tx_dout = timecode_s[10]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd4) + begin + tx_dout = timecode_s[9]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd5) + begin + tx_dout = timecode_s[8]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd6) + begin + tx_dout = timecode_s[7]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd7) + begin + tx_dout = timecode_s[6]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd8) + begin + tx_dout = timecode_s[5]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd9) + begin + tx_dout = timecode_s[4]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd10) + begin + tx_dout = timecode_s[3]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd11) + begin + tx_dout = timecode_s[2]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd12) + begin + tx_dout = timecode_s[1]; + end + else if( enable_time_code & !first_time & global_counter_transfer == 4'd13) + begin + tx_dout = timecode_s[0]; + end + else if( enable_n_char & !first_time & last_type == NULL & global_counter_transfer == 4'd0) + begin + tx_dout = !(data_tx_i[8]^null_s[0]^null_s[1]); + end + else if( enable_n_char & !first_time & last_type == FCT & global_counter_transfer == 4'd0) + begin + tx_dout = !(data_tx_i[8]^fct_s[0]^fct_s[1]); + end + else if( enable_n_char & !first_time & last_type == EOP & global_counter_transfer == 4'd0) + begin + tx_dout = !(data_tx_i[8]^eop_s[0]^eop_s[1]); + end + else if( enable_n_char & !first_time & last_type == EEP & global_counter_transfer == 4'd0) + begin + tx_dout = !(data_tx_i[8]^eep_s[0]^eep_s[1]); + end + else if( enable_n_char & !first_time & last_type == DATA & global_counter_transfer == 4'd0) + begin + tx_dout = !(data_tx_i[8]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]); + end + else if( enable_n_char & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0) + begin + tx_dout = !(data_tx_i[8]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]); + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd1) + begin + tx_dout = data_tx_i[8]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd2) + begin + tx_dout = data_tx_i[0]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd3) + begin + tx_dout = data_tx_i[1]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd4) + begin + tx_dout = data_tx_i[2]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd5) + begin + tx_dout = data_tx_i[3]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd6) + begin + tx_dout = data_tx_i[4]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd7) + begin + tx_dout = data_tx_i[5]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd8) + begin + tx_dout = data_tx_i[6]; + end + else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd9) + begin + tx_dout = data_tx_i[7]; + end + else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & global_counter_transfer == 4'd1) + begin + tx_dout = eop_s[2]; + end + else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & global_counter_transfer == 4'd2) + begin + tx_dout = eop_s[1]; + end + else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & global_counter_transfer == 4'd3) + begin + tx_dout = eop_s[0]; + end + else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & global_counter_transfer == 4'd1) + begin + tx_dout = eep_s[2]; + end + else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & global_counter_transfer == 4'd2) + begin + tx_dout = eep_s[1]; + end + else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & global_counter_transfer == 4'd3) + begin + tx_dout = eep_s[0]; + end +end + +//strobe +always@(*) +begin + tx_sout = 1'b0; + + if(!enable_tx) + begin + tx_sout = 1'b0; + end + else if((enable_null | enable_fct) && tx_dout == last_tx_dout) + begin + tx_sout = !last_tx_sout; + end + else if((enable_null | enable_fct) && tx_dout != last_tx_dout) + begin + tx_sout = last_tx_sout; + end +end + +//slots open in another side +always@(posedge send_fct_tx or negedge enable_tx) +begin + + if(!enable_tx) + begin + fct_counter <= {6{1'b0}}; + end + else if(gotfct_tx) + begin + fct_counter <= fct_counter + 6'd8; + end + else if(enable_n_char) + begin + fct_counter <= fct_counter - 6'd1; + end + +end + + +//slots open in our side +always@(posedge send_fct_now or negedge enable_tx) +begin + + if(!enable_tx) + begin + fct_send <= {3{1'b1}}; + end + else + begin + fct_send <= fct_send + 6'd1; + end + +end + + +always@(*) +begin + + next_state_tx = state_tx; + + enable_null = 1'b0; + enable_fct = 1'b0; + enable_n_char = 1'b0; + enable_time_code = 1'b0; + + case(state_tx) + tx_spw_start: + begin + if(send_null_tx && enable_tx) + begin + if(global_counter_transfer == 4'd7) + next_state_tx = tx_spw_null; + + enable_null = 1'b1; + end + else + begin + next_state_tx = tx_spw_start; + end + end + tx_spw_null: + begin + enable_null = 1'b1; + + if(global_counter_transfer == 4'd7) + begin + if(send_null_tx && send_fct_tx && enable_tx) + next_state_tx = tx_spw_null_fct; + else + next_state_tx = tx_spw_null; + end + + end + tx_spw_null_fct: + begin + + enable_null = 1'b1; + next_state_tx = tx_spw_null_fct; + + if(send_fct_tx && fct_flag != 3'd7) + begin + enable_null = 1'b0; + enable_fct = 1'b1; + end + else + begin + enable_fct = 1'b0; + + if(send_fct_tx && gotfct_tx) + begin + if(global_counter_transfer == 4'd7) + next_state_tx = tx_spw_full; + end + + end + end + tx_spw_full: + begin + + enable_null = 1'b1; + + if(tickin_tx) + begin + if(global_counter_transfer == 4'd7 || global_counter_transfer == 4'd9 || global_counter_transfer == 4'd13 || global_counter_transfer == 4'd3) + enable_time_code = 1'b1; + + enable_null = 1'b0; + end + else if(fct_send > 3'd0) + begin + if(global_counter_transfer == 4'd7 || global_counter_transfer == 4'd9 || global_counter_transfer == 4'd13 || global_counter_transfer == 4'd3) + enable_fct = 1'b1; + + enable_null = 1'b0; + end + else if(txwrite_tx && fct_counter > 6'd0) + begin + if(global_counter_transfer == 4'd7 || global_counter_transfer == 4'd9 || global_counter_transfer == 4'd13 || global_counter_transfer == 4'd3) + enable_n_char = 1'b1; + + enable_null = 1'b0; + end + + end + endcase + +end + +always@(posedge pclk_tx) +begin + if(!enable_tx) + begin + null_s <= 8'h74; + fct_s <= 4'h4; + eop_s <= 4'h5; + eep_s <= 4'h6; + timecode_s <= 14'h1e00; + + fct_flag <= 3'd0; + first_time <= 1'b1; + last_type <= NULL; + + global_counter_transfer <= 4'd0; + txdata_flagctrl_tx_last <= 9'd0; + last_timein_control_flag_tx <= 8'd0; + last_tx_dout <= 1'b0; + last_tx_sout <= 1'b0; + state_tx <= tx_spw_start; + end + else + begin + + state_tx <= next_state_tx; + last_tx_dout <= tx_dout; + last_tx_sout <= tx_sout; + + if(enable_null) + begin + fct_flag<= fct_flag; + if(first_time) + begin + first_time <= 1'b0; + + global_counter_transfer <= global_counter_transfer + 4'd1; + end + else if(global_counter_transfer != 4'd7) + begin + global_counter_transfer <= global_counter_transfer + 4'd1; + end + else + begin + global_counter_transfer <= 4'd0; + end + end + else if(enable_fct) + begin + if(global_counter_transfer != 4'd3) + begin + global_counter_transfer <= global_counter_transfer + 4'd1; + end + else + begin + global_counter_transfer <= 4'd0; + fct_flag <= fct_flag + 3'd1; + end + end + else if(enable_time_code) + begin + fct_flag<= fct_flag; + if(global_counter_transfer < 4'd13) + begin + global_counter_transfer <= global_counter_transfer + 4'd1; + last_timein_control_flag_tx <= timecode_tx_i; + end + else + begin + global_counter_transfer <= 4'd0; + end + end + else if(enable_n_char) + begin + fct_flag<= fct_flag; + if(global_counter_transfer < 4'd9 && !data_tx_i[8]) + begin + global_counter_transfer <= global_counter_transfer + 4'd1; + txdata_flagctrl_tx_last <= data_tx_i; + end + else if(global_counter_transfer < 4'd3 && data_tx_i[8]) + begin + global_counter_transfer <= global_counter_transfer + 4'd1; + txdata_flagctrl_tx_last <= data_tx_i; + end + else + begin + global_counter_transfer <= 4'd0; + end + end + + end +end + +endmodule Index: spacewiresystemc/trunk/systemC/link_sc.h =================================================================== --- spacewiresystemc/trunk/systemC/link_sc.h (nonexistent) +++ spacewiresystemc/trunk/systemC/link_sc.h (revision 5) @@ -0,0 +1,54 @@ +#ifndef CONTROL_SC_H +#define CONTROL_SC_H + +class Control_SC +{ + public: + /*Constructor*/ + Control_SC(); + + /*initialize systemC model*/ + virtual void init(); + + /*Reset the model*/ + virtual bool reset_set(); + + /*Run the Env for ammount off time*/ + virtual void run_sim(); + + /*Tell to SystemC to finish*/ + virtual void stop_sim(); + + /*get dout */ + virtual unsigned int get_value_dout(); + /*get sout*/ + virtual unsigned int get_value_sout(); + + /*set sin*/ + virtual void set_rx_sin(unsigned int strobe); + /*set din*/ + virtual void set_rx_din(unsigned int data); + + virtual unsigned int get_spw_fsm(); + + virtual unsigned int finish_simulation(); + + //verilog variables + virtual bool verilog_linkenable(); + virtual bool verilog_autostart(); + virtual bool verilog_linkdisable(); + + //tests + virtual bool start_tx_test(); + virtual bool enable_time_code_tx_test(); + virtual void end_tx_test(); + virtual unsigned int take_data(unsigned int a); + virtual int size_data_test(); + + virtual void data_o(unsigned int data, unsigned int pos); + + virtual unsigned int clock_tx(); + + +}; +#endif Index: spacewiresystemc/trunk/testbench/module_tb.v =================================================================== --- spacewiresystemc/trunk/testbench/module_tb.v (nonexistent) +++ spacewiresystemc/trunk/testbench/module_tb.v (revision 5) @@ -0,0 +1,230 @@ +`timescale 1ns/1ns +`default_nettype none + +module module_tb; + + reg CLK_SIM; + + `ifdef VERILOG_A + + /*SPWTCR*/ + wire CLOCK; + reg CLK; + wire RESETn; + wire LINK_START; + wire LINK_DISABLE; + wire AUTOSTART; + wire [2:0] CURRENTSTATE; + wire [10:0] FLAGS; + wire [8:0] DATA_I; + wire WR_DATA; + wire TX_FULL; + wire [8:0] DATA_O; + wire RD_DATA; + wire RX_EMPTY; + wire TICK_OUT; + wire [7:0] TIME_OUT; + wire TICK_IN; + wire [7:0] TIME_IN; + wire [6:0] TX_CLK_DIV; + wire SPILL_ENABLE; + wire Din; + wire Sin; + wire Dout; + wire Sout; + + wire [3:0] SPW_SC_FSM; + wire [3:0] SPW_SC_FSM_OUT; + wire RX_CLOCK_RECOVERY_SC; + wire TX_CLOCK_RECOVERY_VLOG; + wire TX_CLOCK_OUT; + wire TX_CLOCK_OUT_SC; + + assign RX_CLOCK_RECOVERY_SC = Din ^ Sin; + assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT; + assign SPW_SC_FSM_OUT = SPW_SC_FSM; + + assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout; + + assign CLOCK = CLK; + + initial CLK = 1'b0; + always #(10) CLK = ~CLK; + + SpwTCR DUT_TCR ( + .CLOCK(CLOCK), + .RESETn(RESETn), + .LINK_START(LINK_START), + .LINK_DISABLE(LINK_DISABLE), + .AUTOSTART(AUTOSTART), + .CURRENTSTATE(CURRENTSTATE), + .FLAGS(FLAGS), + .DATA_I(DATA_I), + .WR_DATA(WR_DATA), + .TX_FULL(TX_FULL), + .DATA_O(DATA_O), + .RD_DATA(RD_DATA), + .RX_EMPTY(RX_EMPTY), + .TICK_OUT(TICK_OUT), + .TIME_OUT(TIME_OUT), + .TICK_IN(TICK_IN), + .TIME_IN(TIME_IN), + .TX_CLK_DIV(TX_CLK_DIV), + .SPILL_ENABLE(SPILL_ENABLE), + .Din(Din), + .Sin(Sin), + .Dout(Dout), + .Sout(Sout) + ); + + + always@(posedge CLK , negedge CLK) + $global_reset; + + always@(posedge CLK) + $write_tx_spw; + + always@(posedge CLK) + $receive_rx_spw; + + //FLAG USED TO FINISH SIMULATION PROGRAM + always@(posedge CLK) + begin + wait(i == 1); + $finish(); + end + `endif + + `ifdef VERILOG_B + `endif + + integer time_clk_ns; + + reg PCLK; + reg PPLLCLK; + + wire RESETN; + + wire TOP_SIN; + wire TOP_DIN; + + wire AUTO_START; + wire LINK_START; + wire LINK_DISABLE; + + wire TOP_TX_WRITE; + wire [8:0] TOP_TX_DATA; + + wire TOP_TX_TICK; + wire [7:0] TOP_TX_TIME; + + wire CREDIT_ERROR_RX; + wire TOP_SEND_FCT_NOW; + + wire [8:0] DATARX_FLAG; + wire BUFFER_WRITE; + + wire [7:0] TIME_OUT; + wire TICK_OUT; + + wire TOP_DOUT; + wire TOP_SOUT; + + wire TOP_TX_READY; + wire TOP_TX_READY_TICK; + + wire [5:0] TOP_FSM; + + integer i; + + initial + begin + $dumpfile("module_tb.vcd"); + $dumpvars(0,module_tb); + $global_init; + i=0; + end + + initial PCLK = 1'b0; + always #(5) PCLK = ~PCLK; + + initial PPLLCLK = 1'b0; + always #(100) PPLLCLK = ~PPLLCLK; + + initial CLK_SIM = 1'b0; + always #(1) CLK_SIM = ~CLK_SIM; + + + top_spw_ultra_light DUT_ULIGHT( + .pclk(PCLK), + .ppllclk(PPLLCLK), + .resetn(RESETN), + + .top_sin(TOP_SIN), + .top_din(TOP_DIN), + + .top_auto_start(AUTO_START), + .top_link_start(LINK_START), + .top_link_disable(LINK_DISABLE), + + .top_tx_write(TOP_TX_WRITE), + .top_tx_data(TOP_TX_DATA), + + .top_tx_tick(TOP_TX_TICK), + .top_tx_time(TOP_TX_TIME), + + .credit_error_rx(CREDIT_ERROR_RX), + .top_send_fct_now(TOP_SEND_FCT_NOW), + + .datarx_flag(DATARX_FLAG), + .buffer_write(BUFFER_WRITE), + + .time_out(TIME_OUT), + .tick_out(TICK_OUT), + + .top_dout(TOP_DOUT), + .top_sout(TOP_SOUT), + + .top_tx_ready(TOP_TX_READY), + .top_tx_ready_tick(TOP_TX_READY_TICK), + + .top_fsm(TOP_FSM) + ); + + + + + // + always@(posedge PCLK) + $write_tx_fsm_spw_ultra_light; + + // + always@(posedge PCLK) + $write_tx_data_spw_ultra_light; + + always@(posedge PCLK) + $write_tx_time_code_spw_ultra_light; + + // + always@(posedge PCLK) + $receive_rx_data_spw_ultra_light; + + always@(posedge PCLK) + $receive_rx_time_code_spw_ultra_light; + + // + always@(posedge PCLK , negedge PCLK) + $global_reset; + // + always@(posedge CLK_SIM) + $run_sim; + + //FLAG USED TO FINISH SIMULATION PROGRAM + always@(posedge CLK_SIM) + begin + wait(i == 1); + $finish(); + end + + +endmodule Index: spacewiresystemc/trunk/vpi/vpi_test_stress/env_global_spw.cpp =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/env_global_spw.cpp (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/env_global_spw.cpp (revision 5) @@ -0,0 +1,152 @@ +#include + +#include "../../systemC/link_sc.h" + +int counter; +int data_iteration_vlog=0; +int position; + +#include +#include +#include +#include +#include + +using namespace std; + +void* lib_handle; + +Control_SC* (*create)(); +void (*destroy)(Control_SC*); + +Control_SC* SC_TOP; + +s_vpi_value v_generate; + +s_vpi_value reset; +s_vpi_value dout_value; +s_vpi_value sout_value; +s_vpi_value din_value; +s_vpi_value sin_value; +s_vpi_value fsm_value; +s_vpi_value value_to_tx; +s_vpi_value value_to_rx; + +s_vpi_value value_to_fsm; + +s_vpi_value message_value; + +s_vpi_value link_enable_value; +s_vpi_value auto_start_value; +s_vpi_value link_disable_value; + +#define SEND_DATA 0 +#define WAIT_DATA 1 + +#define SEND_TIME_CODE 0 +#define WAIT_500_CYCLES 1 + +unsigned int state_test; + +unsigned int state_test_rx; + +unsigned int counter_null; + +#include "run_sim.h" +#include "global_init.h" +#include "global_reset.h" + +#include "write_fsm_spw_ultra_light.h" + +#include "write_tx_data_spw_ultra_light.h" +#include "write_tx_time_code_spw_ultra_light.h" + +#include "receive_rx_data_spw_ultra_light.h" +#include "receive_rx_time_code_spw_ultra_light.h" + +void interaction_register() +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$run_sim"; + tf_data.calltf = run_sim_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + // + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$write_tx_fsm_spw_ultra_light"; + tf_data.calltf = write_tx_fsm_spw_ultra_light_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + // + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$write_tx_data_spw_ultra_light"; + tf_data.calltf = write_tx_data_spw_ultra_light_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$write_tx_time_code_spw_ultra_light"; + tf_data.calltf = write_tx_time_code_spw_ultra_light_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + // + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$receive_rx_data_spw_ultra_light"; + tf_data.calltf = receive_rx_data_spw_ultra_light_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$receive_rx_time_code_spw_ultra_light"; + tf_data.calltf = receive_rx_time_code_spw_ultra_light_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + // + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$global_reset"; + tf_data.calltf = global_reset_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$global_init"; + tf_data.calltf = global_init_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])() = { + interaction_register, + 0 +}; + Index: spacewiresystemc/trunk/vpi/vpi_test_stress/global_init.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/global_init.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/global_init.h (revision 5) @@ -0,0 +1,67 @@ +static int global_init_calltf(char*user_data) +{ + + vpiHandle TX_DATA = vpi_handle_by_name("module_tb.TOP_TX_DATA",NULL); + vpiHandle TX_WRITE = vpi_handle_by_name("module_tb.TOP_TX_WRITE",NULL); + vpiHandle TX_TICK = vpi_handle_by_name("module_tb.TOP_TX_TICK",NULL); + vpiHandle TX_TIME = vpi_handle_by_name("module_tb.TOP_TX_TIME",NULL); + + vpiHandle CREDITERRORRX = vpi_handle_by_name("module_tb.CREDIT_ERROR_RX",NULL); + vpiHandle TOPSENDFCTNOW = vpi_handle_by_name("module_tb.TOP_SEND_FCT_NOW",NULL); + + vpiHandle LINKSTART = vpi_handle_by_name("module_tb.LINK_START",NULL); + vpiHandle LINKDISABLE = vpi_handle_by_name("module_tb.LINK_DISABLE",NULL); + vpiHandle AUTOSTART = vpi_handle_by_name("module_tb.AUTO_START",NULL); + vpiHandle RESETn = vpi_handle_by_name("module_tb.RESETN",NULL); + + vpiHandle DOUT = vpi_handle_by_name("module_tb.TOP_DOUT", NULL); + vpiHandle SOUT = vpi_handle_by_name("module_tb.TOP_SOUT", NULL); + + dout_value.format = vpiIntVal; + sout_value.format = vpiIntVal; + + counter = 0; + position = 0; + counter_null = 0; + state_test_rx=0; + + lib_handle = dlopen("./final_spw.so", RTLD_LAZY); + + if(!lib_handle) + { + fprintf(stderr, "%s\n", dlerror()); + } + + create = (Control_SC* (*)())dlsym(lib_handle, "create_object"); + destroy = (void (*)(Control_SC*))dlsym(lib_handle, "destroy_object"); + + SC_TOP = (Control_SC*)create(); + SC_TOP->init(); + + //SC_TOP->reset_set_low(); + + sout_value.value.integer = SC_TOP->get_value_sout(); + dout_value.value.integer = SC_TOP->get_value_dout(); + + vpi_put_value(DOUT, &dout_value, NULL, vpiNoDelay); + vpi_put_value(SOUT, &sout_value, NULL, vpiNoDelay); + + dout_value.value.integer = 0; + vpi_put_value(LINKSTART, &dout_value, NULL , vpiNoDelay); + vpi_put_value(LINKDISABLE, &dout_value, NULL, vpiNoDelay); + vpi_put_value(AUTOSTART, &dout_value, NULL ,vpiNoDelay); + + vpi_put_value(CREDITERRORRX, &dout_value, NULL , vpiNoDelay); + vpi_put_value(TOPSENDFCTNOW, &dout_value, NULL , vpiNoDelay); + + vpi_put_value(TX_DATA, &dout_value, NULL , vpiNoDelay); + vpi_put_value(TX_WRITE, &dout_value, NULL, vpiNoDelay); + + vpi_put_value(TX_TICK, &dout_value, NULL , vpiNoDelay); + vpi_put_value(TX_TIME, &dout_value, NULL , vpiNoDelay); + + dout_value.value.integer = 1; + vpi_put_value(RESETn, &dout_value, NULL , vpiNoDelay); + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/global_reset.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/global_reset.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/global_reset.h (revision 5) @@ -0,0 +1,22 @@ +static int global_reset_calltf(char*user_data) +{ + + vpiHandle RESETnSPWUL = vpi_handle_by_name("module_tb.RESETN", NULL); + reset.format = vpiIntVal; + + if(!SC_TOP->reset_set()) + { + reset.value.integer = 0; + vpi_put_value(RESETnSPWUL, &reset, NULL, vpiNoDelay); + state_test = 0; + state_test_rx=1; + position = counter = 0; + SC_TOP->end_tx_test(); + }else + { + reset.value.integer = 1; + vpi_put_value(RESETnSPWUL, &reset, NULL, vpiNoDelay); + } + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/receive_rx_data_spw_ultra_light.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/receive_rx_data_spw_ultra_light.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/receive_rx_data_spw_ultra_light.h (revision 5) @@ -0,0 +1,14 @@ +static int receive_rx_data_spw_ultra_light_calltf(char*user_data) +{ + vpiHandle CREDIT_ERROR_RX = vpi_handle_by_name("module_tb.CREDIT_ERROR_RX",NULL); + vpiHandle SEND_FCT_NOW = vpi_handle_by_name("module_tb.TOP_SEND_FCT_NOW",NULL); + + vpiHandle DATARX_FLAG = vpi_handle_by_name("module_tb.DATARX_FLAG",NULL); + vpiHandle BUFFER_WRITE = vpi_handle_by_name("module_tb.BUFFER_WRITE",NULL); + + vpiHandle TIME_OUT = vpi_handle_by_name("module_tb.TIME_OUT",NULL); + vpiHandle TICK_OUT = vpi_handle_by_name("module_tb.TICK_OUT",NULL); + + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/receive_rx_time_code_spw_ultra_light.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/receive_rx_time_code_spw_ultra_light.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/receive_rx_time_code_spw_ultra_light.h (revision 5) @@ -0,0 +1,13 @@ +static int receive_rx_time_code_spw_ultra_light_calltf(char*user_data) +{ + vpiHandle CREDIT_ERROR_RX = vpi_handle_by_name("module_tb.CREDIT_ERROR_RX",NULL); + vpiHandle SEND_FCT_NOW = vpi_handle_by_name("module_tb.TOP_SEND_FCT_NOW",NULL); + + vpiHandle DATARX_FLAG = vpi_handle_by_name("module_tb.DATARX_FLAG",NULL); + vpiHandle BUFFER_WRITE = vpi_handle_by_name("module_tb.BUFFER_WRITE",NULL); + + vpiHandle TIME_OUT = vpi_handle_by_name("module_tb.TIME_OUT",NULL); + vpiHandle TICK_OUT = vpi_handle_by_name("module_tb.TICK_OUT",NULL); + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/run_sim.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/run_sim.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/run_sim.h (revision 5) @@ -0,0 +1,56 @@ +static int run_sim_calltf(char*user_data) +{ + vpiHandle DOUT = vpi_handle_by_name("module_tb.TOP_DOUT", NULL); + vpiHandle SOUT = vpi_handle_by_name("module_tb.TOP_SOUT", NULL); + vpiHandle DIN = vpi_handle_by_name("module_tb.TOP_DIN", NULL); + vpiHandle SIN = vpi_handle_by_name("module_tb.TOP_SIN", NULL); + + //vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL); + //vpiHandle TX_CLOCK_OUT = vpi_handle_by_name("module_tb.TX_CLOCK_OUT", NULL); + + vpiHandle i = vpi_handle_by_name("module_tb.i", NULL); + + dout_value.format = vpiIntVal; + sout_value.format = vpiIntVal; + + din_value.format = vpiIntVal; + sin_value.format = vpiIntVal; + + fsm_value.format = vpiIntVal; + + v_generate.format=vpiIntVal; + //fsm_value.format = vpiIntVal; + //message_value.format = vpiIntVal; + + if(SC_TOP->finish_simulation() == 1) + { + v_generate.value.integer = 1; + vpi_put_value(i, &v_generate, NULL, vpiNoDelay); + SC_TOP->stop_sim(); + destroy(SC_TOP); + } + else + { + SC_TOP->run_sim(); + + sin_value.value.integer = SC_TOP->get_value_sout(); + din_value.value.integer = SC_TOP->get_value_dout(); + vpi_put_value(DIN, &din_value, NULL, vpiNoDelay); + vpi_put_value(SIN, &sin_value, NULL, vpiNoDelay); + + vpi_get_value(SOUT, &sout_value); + vpi_get_value(DOUT, &dout_value); + SC_TOP->set_rx_sin(sout_value.value.integer); + SC_TOP->set_rx_din(dout_value.value.integer); + + //fsm_value.value.integer = SC_TOP->get_spw_fsm(); + //vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay); + + //fsm_value.value.integer = SC_TOP->clock_tx(); + //vpi_put_value(TX_CLOCK_OUT, &fsm_value, NULL, vpiNoDelay); + + } + + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/write_fsm_spw_ultra_light.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/write_fsm_spw_ultra_light.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/write_fsm_spw_ultra_light.h (revision 5) @@ -0,0 +1,24 @@ +static int write_tx_fsm_spw_ultra_light_calltf(char*user_data) +{ + vpiHandle LINKSTART = vpi_handle_by_name("module_tb.LINK_START",NULL); + vpiHandle LINKDISABLE = vpi_handle_by_name("module_tb.LINK_DISABLE",NULL); + vpiHandle AUTOSTART = vpi_handle_by_name("module_tb.AUTO_START",NULL); + + link_enable_value.format = vpiIntVal; + auto_start_value.format = vpiIntVal; + link_disable_value.format = vpiIntVal; + + link_enable_value.value.integer = SC_TOP->verilog_linkenable(); + vpi_put_value(LINKSTART, &link_enable_value, NULL, vpiNoDelay); + + //if(SC_TOP->verilog_linkenable()) + // printf("TESTE\n"); + + auto_start_value.value.integer = SC_TOP->verilog_autostart(); + vpi_put_value(AUTOSTART, &auto_start_value, NULL, vpiNoDelay); + + link_disable_value.value.integer = SC_TOP->verilog_linkdisable(); + vpi_put_value(LINKDISABLE, &link_disable_value, NULL, vpiNoDelay); + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/write_tx_data_spw_ultra_light.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/write_tx_data_spw_ultra_light.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/write_tx_data_spw_ultra_light.h (revision 5) @@ -0,0 +1,8 @@ +static int write_tx_data_spw_ultra_light_calltf(char*user_data) +{ + vpiHandle TX_DATA = vpi_handle_by_name("module_tb.TOP_TX_DATA",NULL); + vpiHandle TX_WRITE = vpi_handle_by_name("module_tb.TOP_TX_WRITE",NULL); + + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_stress/write_tx_time_code_spw_ultra_light.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_stress/write_tx_time_code_spw_ultra_light.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_stress/write_tx_time_code_spw_ultra_light.h (revision 5) @@ -0,0 +1,7 @@ +static int write_tx_time_code_spw_ultra_light_calltf(char*user_data) +{ + vpiHandle TX_DATA = vpi_handle_by_name("module_tb.TOP_TX_DATA",NULL); + vpiHandle TX_WRITE = vpi_handle_by_name("module_tb.TOP_TX_WRITE",NULL); + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_suit/env_global_spw.cpp =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_suit/env_global_spw.cpp (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_suit/env_global_spw.cpp (revision 5) @@ -0,0 +1,114 @@ +#include + +#include "../../systemC/link_sc.h" + +int counter; +int data_iteration_vlog=0; +int position; + +#include +#include +#include +#include +#include + +using namespace std; + +void* lib_handle; + +Control_SC* (*create)(); +void (*destroy)(Control_SC*); + +Control_SC* SC_TOP; + +s_vpi_value v_generate; + +s_vpi_value reset; +s_vpi_value dout_value; +s_vpi_value sout_value; +s_vpi_value din_value; +s_vpi_value sin_value; +s_vpi_value fsm_value; +s_vpi_value value_to_tx; +s_vpi_value value_to_rx; + +s_vpi_value message_value; + +s_vpi_value link_enable_value; +s_vpi_value auto_start_value; +s_vpi_value link_disable_value; + +#define SEND_DATA 0 +#define WAIT_DATA 1 + +#define SEND_TIME_CODE 0 +#define WAIT_500_CYCLES 1 + +unsigned int state_test; + +unsigned int state_test_rx; + +unsigned int counter_null; + +#include "run_sim.h" +#include "global_init.h" +#include "global_reset.h" + +#include "write_tx_spw.h" +#include "receive_rx_spw.h" + +void interaction_register() +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$run_sim"; + tf_data.calltf = run_sim_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$write_tx_spw"; + tf_data.calltf = write_tx_spw_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$receive_rx_spw"; + tf_data.calltf = receive_rx_spw_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$global_reset"; + tf_data.calltf = global_reset_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$global_init"; + tf_data.calltf = global_init_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])() = { + interaction_register, + 0 +}; + Index: spacewiresystemc/trunk/vpi/vpi_test_suit/global_init.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_suit/global_init.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_suit/global_init.h (revision 5) @@ -0,0 +1,64 @@ +static int global_init_calltf(char*user_data) +{ + + vpiHandle DATA_I = vpi_handle_by_name("module_tb.DATA_I",NULL); + vpiHandle WR_DATA = vpi_handle_by_name("module_tb.WR_DATA",NULL); + vpiHandle RD_DATA = vpi_handle_by_name("module_tb.RD_DATA",NULL); + vpiHandle TICK_IN = vpi_handle_by_name("module_tb.TICK_IN",NULL); + vpiHandle TIME_IN = vpi_handle_by_name("module_tb.TIME_IN",NULL); + vpiHandle TX_CLK_DIV = vpi_handle_by_name("module_tb.TX_CLK_DIV",NULL); + + vpiHandle LINKSTART = vpi_handle_by_name("module_tb.LINK_START",NULL); + vpiHandle LINKDISABLE= vpi_handle_by_name("module_tb.LINK_DISABLE",NULL); + vpiHandle AUTOSTART = vpi_handle_by_name("module_tb.AUTOSTART",NULL); + vpiHandle RESETn = vpi_handle_by_name("module_tb.RESETn",NULL); + + vpiHandle DIN = vpi_handle_by_name("module_tb.Din", NULL); + vpiHandle SIN = vpi_handle_by_name("module_tb.Sin", NULL); + + dout_value.format = vpiIntVal; + sout_value.format = vpiIntVal; + + counter = 0; + position = 0; + counter_null = 0; + state_test_rx=0; + + lib_handle = dlopen("./final_spw.so", RTLD_LAZY); + + if(!lib_handle) + { + fprintf(stderr, "%s\n", dlerror()); + } + + create = (Control_SC* (*)())dlsym(lib_handle, "create_object"); + destroy = (void (*)(Control_SC*))dlsym(lib_handle, "destroy_object"); + + SC_TOP = (Control_SC*)create(); + SC_TOP->init(); + + //SC_TOP->reset_set_low(); + + sout_value.value.integer = SC_TOP->get_value_sout(); + dout_value.value.integer = SC_TOP->get_value_dout(); + + vpi_put_value(DIN, &dout_value, NULL, vpiNoDelay); + vpi_put_value(SIN, &sout_value, NULL, vpiNoDelay); + + dout_value.value.integer = 0; + vpi_put_value(LINKSTART, &dout_value, NULL, vpiNoDelay); + vpi_put_value(LINKDISABLE, &dout_value, NULL, vpiNoDelay); + vpi_put_value(AUTOSTART, &dout_value, NULL, vpiNoDelay); + + vpi_put_value(DATA_I, &dout_value, NULL, vpiNoDelay); + vpi_put_value(WR_DATA, &dout_value, NULL, vpiNoDelay); + vpi_put_value(RD_DATA, &dout_value, NULL, vpiNoDelay); + vpi_put_value(TICK_IN, &dout_value, NULL, vpiNoDelay); + vpi_put_value(TIME_IN, &dout_value, NULL, vpiNoDelay); + vpi_put_value(TX_CLK_DIV, &dout_value, NULL, vpiNoDelay); + + dout_value.value.integer = 1; + vpi_put_value(RESETn, &dout_value, NULL, vpiNoDelay); + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_suit/global_reset.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_suit/global_reset.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_suit/global_reset.h (revision 5) @@ -0,0 +1,22 @@ +static int global_reset_calltf(char*user_data) +{ + + vpiHandle RESETnSPWTCR = vpi_handle_by_name("module_tb.RESETn", NULL); + reset.format = vpiIntVal; + + if(!SC_TOP->reset_set()) + { + reset.value.integer = 0; + vpi_put_value(RESETnSPWTCR, &reset, NULL, vpiNoDelay); + state_test = 0; + state_test_rx=1; + position = counter = 0; + SC_TOP->end_tx_test(); + }else + { + reset.value.integer = 1; + vpi_put_value(RESETnSPWTCR, &reset, NULL, vpiNoDelay); + } + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_suit/receive_rx_spw.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_suit/receive_rx_spw.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_suit/receive_rx_spw.h (revision 5) @@ -0,0 +1,62 @@ +static int receive_rx_spw_calltf(char*user_data) +{ + vpiHandle DATA_O = vpi_handle_by_name("module_tb.DATA_O",NULL); + vpiHandle RD_DATA = vpi_handle_by_name("module_tb.RD_DATA",NULL); + vpiHandle RX_EMPTY = vpi_handle_by_name("module_tb.RX_EMPTY",NULL); + + value_to_rx.format = vpiIntVal; + + if(SC_TOP->reset_set()) + { + switch(state_test_rx) + { + case WAIT_DATA: + vpi_get_value(RX_EMPTY, &value_to_rx); + if(value_to_rx.value.integer == 1) + { + value_to_rx.value.integer = 0; + vpi_put_value(RD_DATA, &value_to_rx, NULL, vpiNoDelay); + }else + { + value_to_rx.value.integer = 1; + vpi_put_value(RD_DATA, &value_to_rx, NULL, vpiNoDelay); + state_test_rx =59; + } + break; + case 59: + state_test_rx =70; + break; + case 70: + state_test_rx =71; + break; + case 71: + state_test_rx =72; + break; + case 72: + state_test_rx =73; + break; + case 73: + state_test_rx =74; + break; + case 74: + state_test_rx =60; + break; + case 60: + vpi_get_value(DATA_O, &value_to_rx); + SC_TOP->data_o(value_to_rx.value.integer,data_iteration_vlog); + data_iteration_vlog++; + state_test_rx =61; + break; + case 61: + state_test_rx =WAIT_DATA; + value_to_rx.value.integer = 0; + vpi_put_value(RD_DATA, &value_to_rx, NULL, vpiNoDelay); + + if(data_iteration_vlog > SC_TOP->size_data_test()) + data_iteration_vlog = 0; + break; + } + } + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_suit/run_sim.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_suit/run_sim.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_suit/run_sim.h (revision 5) @@ -0,0 +1,74 @@ +static int run_sim_calltf(char*user_data) +{ + + vpiHandle LINKSTART = vpi_handle_by_name("module_tb.LINK_START",NULL); + vpiHandle LINKDISABLE= vpi_handle_by_name("module_tb.LINK_DISABLE",NULL); + vpiHandle AUTOSTART = vpi_handle_by_name("module_tb.AUTOSTART",NULL); + + vpiHandle DOUT = vpi_handle_by_name("module_tb.Dout", NULL); + vpiHandle SOUT = vpi_handle_by_name("module_tb.Sout", NULL); + vpiHandle DIN = vpi_handle_by_name("module_tb.Din", NULL); + vpiHandle SIN = vpi_handle_by_name("module_tb.Sin", NULL); + + vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL); + vpiHandle TX_CLOCK_OUT = vpi_handle_by_name("module_tb.TX_CLOCK_OUT", NULL); + + vpiHandle i = vpi_handle_by_name("module_tb.i", NULL); + + dout_value.format = vpiIntVal; + sout_value.format = vpiIntVal; + + din_value.format = vpiIntVal; + sin_value.format = vpiIntVal; + + fsm_value.format = vpiIntVal; + + link_enable_value.format = vpiIntVal; + auto_start_value.format = vpiIntVal; + link_disable_value.format = vpiIntVal; + + v_generate.format=vpiIntVal; + //fsm_value.format = vpiIntVal; + //message_value.format = vpiIntVal; + + if(SC_TOP->finish_simulation() == 1) + { + v_generate.value.integer = 1; + vpi_put_value(i, &v_generate, NULL, vpiNoDelay); + SC_TOP->stop_sim(); + destroy(SC_TOP); + } + else + { + SC_TOP->run_sim(); + + link_enable_value.value.integer = SC_TOP->verilog_linkenable(); + vpi_put_value(LINKSTART, &link_enable_value, NULL, vpiNoDelay); + + auto_start_value.value.integer = SC_TOP->verilog_autostart(); + vpi_put_value(AUTOSTART, &auto_start_value, NULL, vpiNoDelay); + + link_disable_value.value.integer = SC_TOP->verilog_linkdisable(); + vpi_put_value(LINKDISABLE, &link_disable_value, NULL, vpiNoDelay); + + sin_value.value.integer = SC_TOP->get_value_sout(); + din_value.value.integer = SC_TOP->get_value_dout(); + vpi_put_value(DIN, &din_value, NULL, vpiNoDelay); + vpi_put_value(SIN, &sin_value, NULL, vpiNoDelay); + + vpi_get_value(SOUT, &sout_value); + vpi_get_value(DOUT, &dout_value); + SC_TOP->set_rx_sin(sout_value.value.integer); + SC_TOP->set_rx_din(dout_value.value.integer); + + //fsm_value.value.integer = SC_TOP->get_spw_fsm(); + //vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay); + + //fsm_value.value.integer = SC_TOP->clock_tx(); + //vpi_put_value(TX_CLOCK_OUT, &fsm_value, NULL, vpiNoDelay); + + } + + + return 0; +} Index: spacewiresystemc/trunk/vpi/vpi_test_suit/write_tx_spw.h =================================================================== --- spacewiresystemc/trunk/vpi/vpi_test_suit/write_tx_spw.h (nonexistent) +++ spacewiresystemc/trunk/vpi/vpi_test_suit/write_tx_spw.h (revision 5) @@ -0,0 +1,61 @@ +static int write_tx_spw_calltf(char*user_data) +{ + vpiHandle DATA_I = vpi_handle_by_name("module_tb.DATA_I",NULL); + vpiHandle WR_DATA = vpi_handle_by_name("module_tb.WR_DATA",NULL); + vpiHandle TX_FULL = vpi_handle_by_name("module_tb.TX_FULL",NULL); + + value_to_tx.format = vpiIntVal; + + if(SC_TOP->reset_set()) + { + if(SC_TOP->start_tx_test()) + { + switch(state_test) + { + case SEND_DATA: + value_to_tx.value.integer = SC_TOP->take_data(position); + vpi_put_value(DATA_I, &value_to_tx, NULL, vpiNoDelay); + state_test = 59; + break; + case 59: + value_to_tx.value.integer = 1; + vpi_put_value(WR_DATA, &value_to_tx, NULL, vpiNoDelay); + state_test = WAIT_DATA; + break; + case WAIT_DATA: + value_to_tx.value.integer = 0; + vpi_put_value(WR_DATA, &value_to_tx, NULL, vpiNoDelay); + + if(position <= SC_TOP->size_data_test()) + { + vpi_get_value(TX_FULL, &value_to_tx); + if(value_to_tx.value.integer == 1) + { + } + else + { + state_test = SEND_DATA; + //counter = counter + 1; + position = position + 1; + } + } + if(position > SC_TOP->size_data_test()) + { + state_test = 60; + } + break; + case 60: + SC_TOP->end_tx_test(); + counter = position = state_test = 0; + break; + } + } + + if(SC_TOP->enable_time_code_tx_test()) + { + + } + } + + return 0; +} Index: spacewiresystemc/trunk/work/SpaceWrireTestSuit.glade =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/xml Index: spacewiresystemc/trunk/work/SpaceWrireTestSuit.glade =================================================================== --- spacewiresystemc/trunk/work/SpaceWrireTestSuit.glade (nonexistent) +++ spacewiresystemc/trunk/work/SpaceWrireTestSuit.glade (revision 5)

spacewiresystemc/trunk/work/SpaceWrireTestSuit.glade Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/xml \ No newline at end of property Index: spacewiresystemc/trunk/work/run.sh =================================================================== --- spacewiresystemc/trunk/work/run.sh (nonexistent) +++ spacewiresystemc/trunk/work/run.sh (revision 5) @@ -0,0 +1,7 @@ +g++ -c -ldl -fpic ../vpi/vpi_test_suit/env_global_spw.cpp -std=c++11 -Wwrite-strings -fpermissive + +g++ -shared -oenv_global_spw.vpi env_global_spw.o -lvpi -std=c++11 -Wwrite-strings -fpermissive + +iverilog -oenv_global_spw.vvp -g2012 ../rtl/RTL_VA/*.sv ../testbench/module_tb.v + +vvp -M. -menv_global_spw env_global_spw.vvp Index: spacewiresystemc/trunk/work/run_stress_test.sh =================================================================== --- spacewiresystemc/trunk/work/run_stress_test.sh (nonexistent) +++ spacewiresystemc/trunk/work/run_stress_test.sh (revision 5) @@ -0,0 +1,8 @@ + +g++ -c -ldl -fpic ../vpi/vpi_test_stress/env_global_spw.cpp -std=c++11 -Wwrite-strings -fpermissive + +g++ -shared -oenv_global_spw.vpi env_global_spw.o -lvpi -std=c++11 -Wwrite-strings -fpermissive + +iverilog -oenv_global_spw.vvp ../rtl/RTL_VB/*.v ../testbench/module_tb.v + +vvp -M. -menv_global_spw env_global_spw.vvp

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