Subversion Repositories all_digital_fm_receiver

/tags/ver-1/loop_filter.vhd File deleted

/tags/ver-1/fmTri.txt File deleted

/tags/ver-1/nco.vhd File deleted

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/tags/ver-1/fm.txt File deleted

/tags/ver-1/cos.txt File deleted

/tags/ver-1/circuit.vhd File deleted

/tags/ver-1/multiplier.vhd File deleted

/tags/ver-1/circuit_tb.vhd File deleted

/trunk/fmTri.txt File deleted

/trunk/nco.vhd File deleted

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/trunk/adfmreceiver.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/adfmreceiver.pdf

trunk/adfmreceiver.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/multiplier.vhd =================================================================== --- trunk/multiplier.vhd (revision 4) +++ trunk/multiplier.vhd (nonexistent) @@ -1,142 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - - -ENTITY multiplier IS --- Declarations -port (CLK : in std_logic; - RESET : in std_logic; - input1 : in std_logic_vector(7 downto 0); - input2 : in signed(7 downto 0); - output : out signed(7 downto 0) - ); -END multiplier ; - - -ARCHITECTURE behavior OF multiplier IS - -signal out_temp : signed(15 downto 0); -signal input1_buf : signed(15 downto 0); -signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0); - -begin - -process(CLK, RESET) -begin - if (RESET='1') then - out_temp <= (others => '0'); - output <= (others => '0'); - input1_buf <= (others => '0'); - part0 <= (others => '0'); - part1 <= (others => '0'); - part2 <= (others => '0'); - part3 <= (others => '0'); - part4 <= (others => '0'); - part5 <= (others => '0'); - part6 <= (others => '0'); - part7 <= (others => '0'); - elsif rising_edge(CLK) then - input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1); - if (input2(0)='1') then - part0 <= -(input1_buf); - else - part0 <= (others => '0'); - end if; - if (input2(1)='1') then - if (input2(0)='1') then - part1 <= (others => '0'); - else - part1 <= -(input1_buf); - end if; - else - if (input2(0)='1') then - part1 <= input1_buf; - else - part1 <= (others => '0'); - end if; - end if; - if (input2(2)='1') then - if (input2(1)='1') then - part2 <= (others => '0'); - else - part2 <= -(input1_buf); - end if; - else - if (input2(1)='1') then - part2 <= input1_buf; - else - part2 <= (others => '0'); - end if; - end if; - if (input2(3)='1') then - if (input2(2)='1') then - part3 <= (others => '0'); - else - part3 <= -(input1_buf); - end if; - else - if (input2(2)='1') then - part3 <= input1_buf; - else - part3 <= (others => '0'); - end if; - end if; - if (input2(4)='1') then - if (input2(3)='1') then - part4 <= (others => '0'); - else - part4 <= -(input1_buf); - end if; - else - if (input2(3)='1') then - part4 <= input1_buf; - else - part4 <= (others => '0'); - end if; - end if; - if (input2(5)='1') then - if (input2(4)='1') then - part5 <= (others => '0'); - else - part5 <= -(input1_buf); - end if; - else - if (input2(4)='1') then - part5 <= input1_buf; - else - part5 <= (others => '0'); - end if; - end if; - if (input2(6)='1') then - if (input2(5)='1') then - part6 <= (others => '0'); - else - part6 <= -(input1_buf); - end if; - else - if (input2(5)='1') then - part6 <= input1_buf; - else - part6 <= (others => '0'); - end if; - end if; - if (input2(7)='1') then - if (input2(6)='1') then - part7 <= (others => '0'); - else - part7 <= -(input1_buf); - end if; - else - if (input2(6)='1') then - part7 <= input1_buf; - else - part7 <= (others => '0'); - end if; - end if; - out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000"); - output <= out_temp(15 downto 8); -end if; -end process; -END behavior; - Index: trunk/circuit_tb.vhd =================================================================== --- trunk/circuit_tb.vhd (revision 4) +++ trunk/circuit_tb.vhd (nonexistent) @@ -1,64 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE std.textio.ALL; - -ENTITY circuit_tb IS -END circuit_tb; - -ARCHITECTURE behavior OF circuit_tb IS - -file vectors: text open read_mode is "fm.txt"; - - - COMPONENT circuit - PORT( - clk : IN std_logic; - reset : IN std_logic; - fmin : IN std_logic_vector(7 downto 0); - dmout : OUT std_logic_vector(11 downto 0) - ); - END COMPONENT; - - SIGNAL clk : std_logic := '0' ; - SIGNAL reset : std_logic := '1'; - SIGNAL fmin : std_logic_vector(7 downto 0); - SIGNAL dmout : std_logic_vector(11 downto 0); - constant clkperiod : time := 62.5 ns; -- 16 MHz of frequency - -BEGIN - - uut: circuit PORT MAP( - clk => clk, - reset => reset, - fmin => fmin, - dmout => dmout - ); - - RESET_GEN: process - begin - LOOP1: for N in 0 to 3 loop - wait until falling_edge(CLK); - end loop LOOP1; - RESET <= '0' ; - end process RESET_GEN; - -clk <= not clk after clkperiod / 2; - -process -variable vectorline : line; -variable fmin_var : bit_vector(7 downto 0); -begin -while not endfile(vectors) loop - if (reset = '1') then - fmin <= (others => '0'); - else - readline(vectors, vectorline); - read(vectorline, fmin_var); - fmin <= to_stdlogicvector(fmin_var); - end if; - wait for clkperiod; -end loop; -end process; - -END; Index: trunk/loop_filter.vhd =================================================================== --- trunk/loop_filter.vhd (revision 4) +++ trunk/loop_filter.vhd (nonexistent) @@ -1,38 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - - - -ENTITY loop_filter IS --- Declarations - port ( CLK : in std_logic; - RESET : in std_logic; - C : in signed(7 downto 0); - D1 : out signed(11 downto 0); - D2 : out signed(11 downto 0) - ); -END loop_filter ; - - -ARCHITECTURE behavior OF loop_filter IS - -signal E : signed(11 downto 0); -signal dtemp : signed(11 downto 0); - -begin -process(CLK, RESET) -begin - if (RESET='1') then - D1 <= (others => '0'); - D2 <= (others => '0'); - E <= (others => '0'); - dtemp <= (others => '0'); - elsif rising_edge(CLK) then - dtemp <= (C(7)&C(7)&C(7)&C&'0') + dtemp - E; - E <= dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11 downto 4); - D1 <= dtemp; - D2 <= dtemp(11 downto 4)&"0000"; - end if; -end process; -END behavior; Index: all_digital_fm_receiver/trunk/adfmreceiver.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: all_digital_fm_receiver/trunk/adfmreceiver.pdf =================================================================== --- all_digital_fm_receiver/trunk/adfmreceiver.pdf (nonexistent) +++ all_digital_fm_receiver/trunk/adfmreceiver.pdf (revision 5)

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downto 0); +-- ROM cosrom +constant cosrom : vectype := ( +0 => "01111111", +1 => "01111111", +2 => "01111111", +3 => "01111111", +4 => "01111111", +5 => "01111111", +6 => "01111111", +7 => "01111111", +8 => "01111111", +9 => "01111111", +10 => "01111111", +11 => "01111111", +12 => "01111111", +13 => "01111111", +14 => "01111111", +15 => "01111111", +16 => "01111111", +17 => "01111111", +18 => "01111111", +19 => "01111111", +20 => "01111111", +21 => "01111111", +22 => "01111111", +23 => "01111111", +24 => "01111111", +25 => "01111110", +26 => "01111110", +27 => "01111110", +28 => "01111110", +29 => "01111110", +30 => "01111110", +31 => "01111110", +32 => "01111110", +33 => "01111101", +34 => "01111101", +35 => "01111101", +36 => "01111101", +37 => "01111101", +38 => "01111101", +39 => "01111100", +40 => "01111100", +41 => "01111100", +42 => "01111100", +43 => "01111100", +44 => "01111011", +45 => "01111011", +46 => "01111011", +47 => "01111011", +48 => "01111010", +49 => "01111010", +50 => "01111010", +51 => "01111010", +52 => "01111010", +53 => "01111001", +54 => "01111001", +55 => "01111001", +56 => "01111001", +57 => "01111000", +58 => "01111000", +59 => "01111000", +60 => "01110111", +61 => "01110111", +62 => "01110111", +63 => "01110111", +64 => "01110110", +65 => "01110110", +66 => "01110110", +67 => "01110101", +68 => "01110101", +69 => "01110101", +70 => "01110100", +71 => "01110100", +72 => "01110100", +73 => "01110011", +74 => "01110011", +75 => "01110011", +76 => "01110010", +77 => "01110010", +78 => "01110010", +79 => "01110001", +80 => "01110001", +81 => "01110001", +82 => "01110000", +83 => "01110000", +84 => "01101111", +85 => "01101111", +86 => "01101111", +87 => "01101110", +88 => "01101110", +89 => "01101101", +90 => "01101101", +91 => "01101101", +92 => "01101100", +93 => "01101100", +94 => "01101011", +95 => "01101011", +96 => "01101010", +97 => "01101010", +98 => "01101010", +99 => "01101001", +100 => "01101001", +101 => "01101000", +102 => "01101000", +103 => "01100111", +104 => "01100111", +105 => "01100110", +106 => "01100110", +107 => "01100101", +108 => "01100101", +109 => "01100100", +110 => "01100100", +111 => "01100011", +112 => "01100011", +113 => "01100010", +114 => "01100010", +115 => "01100001", +116 => "01100001", +117 => "01100000", +118 => "01100000", +119 => "01011111", +120 => "01011111", +121 => "01011110", +122 => "01011110", +123 => "01011101", +124 => "01011101", +125 => "01011100", +126 => "01011100", +127 => "01011011", +128 => "01011011", +129 => "01011010", +130 => "01011001", +131 => "01011001", +132 => "01011000", +133 => "01011000", +134 => "01010111", +135 => "01010111", +136 => "01010110", +137 => "01010101", +138 => "01010101", +139 => "01010100", +140 => "01010100", +141 => "01010011", +142 => "01010010", +143 => "01010010", +144 => "01010001", +145 => "01010001", +146 => "01010000", +147 => "01001111", +148 => "01001111", +149 => "01001110", +150 => "01001110", +151 => "01001101", +152 => "01001100", +153 => "01001100", +154 => "01001011", +155 => "01001010", +156 => "01001010", +157 => "01001001", +158 => "01001000", +159 => "01001000", +160 => "01000111", +161 => "01000111", +162 => "01000110", +163 => "01000101", +164 => "01000101", +165 => "01000100", +166 => "01000011", +167 => "01000011", +168 => "01000010", +169 => "01000001", +170 => "01000001", +171 => "01000000", +172 => "00111111", +173 => "00111110", +174 => "00111110", +175 => "00111101", +176 => "00111100", +177 => "00111100", +178 => "00111011", +179 => "00111010", +180 => "00111010", +181 => "00111001", +182 => "00111000", +183 => "00111000", +184 => "00110111", +185 => "00110110", +186 => "00110101", +187 => "00110101", +188 => "00110100", +189 => "00110011", +190 => "00110011", +191 => "00110010", +192 => "00110001", +193 => "00110000", +194 => "00110000", +195 => "00101111", +196 => "00101110", +197 => "00101101", +198 => "00101101", +199 => "00101100", +200 => "00101011", +201 => "00101010", +202 => "00101010", +203 => "00101001", +204 => "00101000", +205 => "00100111", +206 => "00100111", +207 => "00100110", +208 => "00100101", +209 => "00100100", +210 => "00100100", +211 => "00100011", +212 => "00100010", +213 => "00100001", +214 => "00100001", +215 => "00100000", +216 => "00011111", +217 => "00011110", +218 => "00011110", +219 => "00011101", +220 => "00011100", +221 => "00011011", +222 => "00011011", +223 => "00011010", +224 => "00011001", +225 => "00011000", +226 => "00011000", +227 => "00010111", +228 => "00010110", +229 => "00010101", +230 => "00010100", +231 => "00010100", +232 => "00010011", +233 => "00010010", +234 => "00010001", +235 => "00010001", +236 => "00010000", +237 => "00001111", +238 => "00001110", +239 => "00001101", +240 => "00001101", +241 => "00001100", +242 => "00001011", +243 => "00001010", +244 => "00001010", +245 => "00001001", +246 => "00001000", +247 => "00000111", +248 => "00000110", +249 => "00000110", +250 => "00000101", +251 => "00000100", +252 => "00000011", +253 => "00000010", +254 => "00000010", +255 => "00000001", +256 => "00000000"); + +signal dtemp : unsigned(17 downto 0); +signal din_buf : signed(17 downto 0); +signal dtemp1 : integer; +constant offset : unsigned(17 downto 0) := "000100000000000000"; + +begin + +process(CLK, RESET) +begin + if (RESET='1') then + dout <= (others => '0'); + din_buf <= (others => '0'); + dtemp <= (others => '0'); + dtemp1 <= 0; + elsif rising_edge(CLK) then + din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din; + dtemp <= dtemp + unsigned(din_buf) + offset; + dtemp1 <= to_integer(dtemp(17 downto 8)); + if (dtemp1 >= 0) and (dtemp1 < 257) then + dout <= cosrom(dtemp1); + elsif (dtemp1 >= 257) and (dtemp1 < 513) then + dout <= -cosrom(512-dtemp1); + elsif (dtemp1 >= 513) and (dtemp1 < 769) then + dout <= -cosrom(dtemp1-512); + else + dout <= cosrom(1024-dtemp1); + end if; + end if; +end process; +END behavior; Index: all_digital_fm_receiver/trunk/fir.vhd =================================================================== --- all_digital_fm_receiver/trunk/fir.vhd (nonexistent) +++ all_digital_fm_receiver/trunk/fir.vhd (revision 5) @@ -0,0 +1,64 @@ +LIBRARY ieee; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + + +entity FIR is +port( + clock : in std_logic; + reset : in std_logic; + data_in : in signed(11 downto 0); + data_out : out std_logic_vector(11 downto 0) +); +end FIR; + +architecture behavior of FIR is + +signal d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15 : signed(15 downto 0); +signal sum : signed(15 downto 0); + +begin + +process(clock,reset) +begin + if (reset = '1') then + d0 <= (others => '0'); + d1 <= (others => '0'); + d2 <= (others => '0'); + d3 <= (others => '0'); + d4 <= (others => '0'); + d5 <= (others => '0'); + d6 <= (others => '0'); + d7 <= (others => '0'); + d8 <= (others => '0'); + d9 <= (others => '0'); + d10 <= (others => '0'); + d11 <= (others => '0'); + d12 <= (others => '0'); + d13 <= (others => '0'); + d14 <= (others => '0'); + d15 <= (others => '0'); + sum <= (others => '0'); + data_out <= (others => '0'); + ELSIF rising_edge(clock) THEN + d0 <= data_in(11)&data_in(11)&data_in(11)&data_in(11)&data_in; + d1 <= d0; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + d7 <= d6; + d8 <= d7; + d9 <= d8; + d10 <= d9; + d11 <= d10; + d12 <= d11; + d13 <= d12; + d14 <= d13; + d15 <= d14; + sum <= (d0+d1+d2+d3+d4+d5+d6+d7+d8+d9+d10+d11+d12+d13+d14+d15) srl 4; + data_out <= std_logic_vector(sum(11 downto 0)); + end if; +end process; +end behavior; \ No newline at end of file Index: all_digital_fm_receiver/trunk/fm.txt =================================================================== --- all_digital_fm_receiver/trunk/fm.txt (nonexistent) +++ all_digital_fm_receiver/trunk/fm.txt (revision 5) @@ -0,0 +1,1000 @@ +01111111 +01110110 +01011010 +00110000 +11111110 +11001101 +10100011 +10001000 +10000000 +10001100 +10101001 +11010100 +00000110 +00110111 +01011111 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all_digital_fm_receiver/trunk/circuit.vhd (nonexistent) +++ all_digital_fm_receiver/trunk/circuit.vhd (revision 5) @@ -0,0 +1,101 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + + + +ENTITY circuit IS +-- Declarations + PORT( + clk : IN std_logic; + reset : IN std_logic; + fmin : IN std_logic_vector(7 downto 0); + dmout : OUT std_logic_vector (11 DOWNTO 0) + ); +END circuit ; + + +ARCHITECTURE behavior OF circuit IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL d1 : signed(11 DOWNTO 0); + SIGNAL d2 : signed(11 DOWNTO 0); + SIGNAL dout : signed(7 DOWNTO 0); + SIGNAL output : signed(7 DOWNTO 0); + + + + -- Component Declarations + COMPONENT multiplier + PORT ( + clk : IN std_logic ; + reset : IN std_logic ; + input1 : IN std_logic_vector (7 DOWNTO 0); + input2 : IN signed (7 DOWNTO 0); + output : OUT signed (7 DOWNTO 0) + ); + END COMPONENT; + COMPONENT fir + PORT ( + clock : IN std_logic ; + reset : IN std_logic ; + data_in : IN signed (11 DOWNTO 0); + data_out : OUT std_logic_vector (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT loop_filter + PORT ( + clk : IN std_logic ; + reset : IN std_logic ; + c : IN signed (7 DOWNTO 0); + d1 : OUT signed (11 DOWNTO 0); + d2 : OUT signed (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT nco + PORT ( + clk : IN std_logic ; + reset : IN std_logic ; + din : IN signed (11 DOWNTO 0); + dout : OUT signed (7 DOWNTO 0) + ); + END COMPONENT; + + +BEGIN + -- Instance port mappings. + I1 : multiplier + PORT MAP ( + clk => clk, + reset => reset, + input1 => fmin, + input2 => dout, + output => output + ); + I4 : fir + PORT MAP ( + clock => clk, + reset => reset, + data_in => d1, + data_out => dmout + ); + I3 : loop_filter + PORT MAP ( + clk => clk, + reset => reset, + c => output, + d1 => d1, + d2 => d2 + ); + I2 : nco + PORT MAP ( + clk => clk, + reset => reset, + din => d2, + dout => dout + ); + + + END behavior; Index: all_digital_fm_receiver/trunk/cos.txt =================================================================== --- all_digital_fm_receiver/trunk/cos.txt (nonexistent) +++ all_digital_fm_receiver/trunk/cos.txt (revision 5) @@ -0,0 +1,1024 @@ +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111111 +01111110 +01111110 +01111110 +01111110 +01111110 +01111110 +01111110 +01111110 +01111101 +01111101 +01111101 +01111101 +01111101 +01111101 +01111100 +01111100 +01111100 +01111100 +01111100 +01111011 +01111011 +01111011 +01111011 +01111010 +01111010 +01111010 +01111010 +01111010 +01111001 +01111001 +01111001 +01111001 +01111000 +01111000 +01111000 +01110111 +01110111 +01110111 +01110111 +01110110 +01110110 +01110110 +01110101 +01110101 +01110101 +01110100 +01110100 +01110100 +01110011 +01110011 +01110011 +01110010 +01110010 +01110010 +01110001 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multiplier ; + + +ARCHITECTURE behavior OF multiplier IS + +signal out_temp : signed(15 downto 0); +signal input1_buf : signed(15 downto 0); +signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0); + +begin + +process(CLK, RESET) +begin + if (RESET='1') then + out_temp <= (others => '0'); + output <= (others => '0'); + input1_buf <= (others => '0'); + part0 <= (others => '0'); + part1 <= (others => '0'); + part2 <= (others => '0'); + part3 <= (others => '0'); + part4 <= (others => '0'); + part5 <= (others => '0'); + part6 <= (others => '0'); + part7 <= (others => '0'); + elsif rising_edge(CLK) then + input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1); + if (input2(0)='1') then + part0 <= -(input1_buf); + else + part0 <= (others => '0'); + end if; + if (input2(1)='1') then + if (input2(0)='1') then + part1 <= (others => '0'); + else + part1 <= -(input1_buf); + end if; + else + if (input2(0)='1') then + part1 <= input1_buf; + else + part1 <= (others => '0'); + end if; + end if; + if (input2(2)='1') then + if (input2(1)='1') then + part2 <= (others => '0'); + else + part2 <= -(input1_buf); + end if; + else + if (input2(1)='1') then + part2 <= input1_buf; + else + part2 <= (others => '0'); + end if; + end if; + if (input2(3)='1') then + if (input2(2)='1') then + part3 <= (others => '0'); + else + part3 <= -(input1_buf); + end if; + else + if (input2(2)='1') then + part3 <= input1_buf; + else + part3 <= (others => '0'); + end if; + end if; + if (input2(4)='1') then + if (input2(3)='1') then + part4 <= (others => '0'); + else + part4 <= -(input1_buf); + end if; + else + if (input2(3)='1') then + part4 <= input1_buf; + else + part4 <= (others => '0'); + end if; + end if; + if (input2(5)='1') then + if (input2(4)='1') then + part5 <= (others => '0'); + else + part5 <= -(input1_buf); + end if; + else + if (input2(4)='1') then + part5 <= input1_buf; + else + part5 <= (others => '0'); + end if; + end if; + if (input2(6)='1') then + if (input2(5)='1') then + part6 <= (others => '0'); + else + part6 <= -(input1_buf); + end if; + else + if (input2(5)='1') then + part6 <= input1_buf; + else + part6 <= (others => '0'); + end if; + end if; + if (input2(7)='1') then + if (input2(6)='1') then + part7 <= (others => '0'); + else + part7 <= -(input1_buf); + end if; + else + if (input2(6)='1') then + part7 <= input1_buf; + else + part7 <= (others => '0'); + end if; + end if; + out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000"); + output <= out_temp(15 downto 8); +end if; +end process; +END behavior; + Index: all_digital_fm_receiver/trunk/circuit_tb.vhd =================================================================== --- all_digital_fm_receiver/trunk/circuit_tb.vhd (nonexistent) +++ all_digital_fm_receiver/trunk/circuit_tb.vhd (revision 5) @@ -0,0 +1,64 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE std.textio.ALL; + +ENTITY circuit_tb IS +END circuit_tb; + +ARCHITECTURE behavior OF circuit_tb IS + +file vectors: text open read_mode is "fm.txt"; + + + COMPONENT circuit + PORT( + clk : IN std_logic; + reset : IN std_logic; + fmin : IN std_logic_vector(7 downto 0); + dmout : OUT std_logic_vector(11 downto 0) + ); + END COMPONENT; + + SIGNAL clk : std_logic := '0' ; + SIGNAL reset : std_logic := '1'; + SIGNAL fmin : std_logic_vector(7 downto 0); + SIGNAL dmout : std_logic_vector(11 downto 0); + constant clkperiod : time := 62.5 ns; -- 16 MHz of frequency + +BEGIN + + uut: circuit PORT MAP( + clk => clk, + reset => reset, + fmin => fmin, + dmout => dmout + ); + + RESET_GEN: process + begin + LOOP1: for N in 0 to 3 loop + wait until falling_edge(CLK); + end loop LOOP1; + RESET <= '0' ; + end process RESET_GEN; + +clk <= not clk after clkperiod / 2; + +process +variable vectorline : line; +variable fmin_var : bit_vector(7 downto 0); +begin +while not endfile(vectors) loop + if (reset = '1') then + fmin <= (others => '0'); + else + readline(vectors, vectorline); + read(vectorline, fmin_var); + fmin <= to_stdlogicvector(fmin_var); + end if; + wait for clkperiod; +end loop; +end process; + +END; Index: all_digital_fm_receiver/trunk/loop_filter.vhd =================================================================== --- all_digital_fm_receiver/trunk/loop_filter.vhd (nonexistent) +++ all_digital_fm_receiver/trunk/loop_filter.vhd (revision 5) @@ -0,0 +1,38 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + + + +ENTITY loop_filter IS +-- Declarations + port ( CLK : in std_logic; + RESET : in std_logic; + C : in signed(7 downto 0); + D1 : out signed(11 downto 0); + D2 : out signed(11 downto 0) + ); +END loop_filter ; + + +ARCHITECTURE behavior OF loop_filter IS + +signal E : signed(11 downto 0); +signal dtemp : signed(11 downto 0); + +begin +process(CLK, RESET) +begin + if (RESET='1') then + D1 <= (others => '0'); + D2 <= (others => '0'); + E <= (others => '0'); + dtemp <= (others => '0'); + elsif rising_edge(CLK) then + dtemp <= (C(7)&C(7)&C(7)&C&'0') + dtemp - E; + E <= dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11 downto 4); + D1 <= dtemp; + D2 <= dtemp(11 downto 4)&"0000"; + end if; +end process; +END behavior; Index: all_digital_fm_receiver/trunk =================================================================== --- all_digital_fm_receiver/trunk (nonexistent) +++ all_digital_fm_receiver/trunk (revision 5)

all_digital_fm_receiver/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: all_digital_fm_receiver/web_uploads =================================================================== --- all_digital_fm_receiver/web_uploads (nonexistent) +++ all_digital_fm_receiver/web_uploads (revision 5)

all_digital_fm_receiver/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: all_digital_fm_receiver/branches =================================================================== --- all_digital_fm_receiver/branches (nonexistent) +++ all_digital_fm_receiver/branches (revision 5)

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cosrom : vectype := ( +0 => "01111111", +1 => "01111111", +2 => "01111111", +3 => "01111111", +4 => "01111111", +5 => "01111111", +6 => "01111111", +7 => "01111111", +8 => "01111111", +9 => "01111111", +10 => "01111111", +11 => "01111111", +12 => "01111111", +13 => "01111111", +14 => "01111111", +15 => "01111111", +16 => "01111111", +17 => "01111111", +18 => "01111111", +19 => "01111111", +20 => "01111111", +21 => "01111111", +22 => "01111111", +23 => "01111111", +24 => "01111111", +25 => "01111110", +26 => "01111110", +27 => "01111110", +28 => "01111110", +29 => "01111110", +30 => "01111110", +31 => "01111110", +32 => "01111110", +33 => "01111101", +34 => "01111101", +35 => "01111101", +36 => "01111101", +37 => "01111101", +38 => "01111101", +39 => "01111100", +40 => "01111100", +41 => "01111100", +42 => "01111100", +43 => "01111100", +44 => "01111011", +45 => "01111011", +46 => "01111011", +47 => "01111011", +48 => "01111010", +49 => "01111010", +50 => "01111010", +51 => "01111010", +52 => "01111010", +53 => "01111001", +54 => "01111001", +55 => "01111001", +56 => "01111001", +57 => "01111000", +58 => "01111000", +59 => "01111000", +60 => "01110111", +61 => "01110111", +62 => "01110111", +63 => "01110111", +64 => "01110110", +65 => "01110110", +66 => "01110110", +67 => "01110101", +68 => "01110101", +69 => "01110101", +70 => "01110100", +71 => "01110100", +72 => "01110100", +73 => "01110011", +74 => "01110011", +75 => "01110011", +76 => "01110010", +77 => "01110010", +78 => "01110010", +79 => "01110001", +80 => "01110001", +81 => "01110001", +82 => "01110000", +83 => "01110000", +84 => "01101111", +85 => "01101111", +86 => "01101111", +87 => "01101110", +88 => "01101110", +89 => "01101101", +90 => "01101101", +91 => "01101101", +92 => "01101100", +93 => "01101100", +94 => "01101011", +95 => "01101011", +96 => "01101010", +97 => "01101010", +98 => "01101010", +99 => "01101001", +100 => "01101001", +101 => "01101000", +102 => "01101000", +103 => "01100111", +104 => "01100111", +105 => "01100110", +106 => "01100110", +107 => "01100101", +108 => "01100101", +109 => "01100100", +110 => "01100100", +111 => "01100011", +112 => "01100011", +113 => "01100010", +114 => "01100010", +115 => "01100001", +116 => "01100001", +117 => "01100000", +118 => "01100000", +119 => "01011111", +120 => "01011111", +121 => "01011110", +122 => "01011110", +123 => "01011101", +124 => "01011101", +125 => "01011100", +126 => "01011100", +127 => "01011011", +128 => "01011011", +129 => "01011010", +130 => "01011001", +131 => "01011001", +132 => "01011000", +133 => "01011000", +134 => "01010111", +135 => "01010111", +136 => "01010110", +137 => "01010101", +138 => "01010101", +139 => "01010100", +140 => "01010100", +141 => "01010011", +142 => "01010010", +143 => "01010010", +144 => "01010001", +145 => "01010001", +146 => "01010000", +147 => "01001111", +148 => "01001111", +149 => "01001110", +150 => "01001110", +151 => "01001101", +152 => "01001100", +153 => "01001100", +154 => "01001011", +155 => "01001010", +156 => "01001010", +157 => "01001001", +158 => "01001000", +159 => "01001000", +160 => "01000111", +161 => "01000111", +162 => "01000110", +163 => "01000101", +164 => "01000101", +165 => "01000100", +166 => "01000011", +167 => "01000011", +168 => "01000010", +169 => "01000001", +170 => "01000001", +171 => "01000000", +172 => "00111111", +173 => "00111110", +174 => "00111110", +175 => "00111101", +176 => "00111100", +177 => "00111100", +178 => "00111011", +179 => "00111010", +180 => "00111010", +181 => "00111001", +182 => "00111000", +183 => "00111000", +184 => "00110111", +185 => "00110110", +186 => "00110101", +187 => "00110101", +188 => "00110100", +189 => "00110011", +190 => "00110011", +191 => "00110010", +192 => "00110001", +193 => "00110000", +194 => "00110000", +195 => "00101111", +196 => "00101110", +197 => "00101101", +198 => "00101101", +199 => "00101100", +200 => "00101011", +201 => "00101010", +202 => "00101010", +203 => "00101001", +204 => "00101000", +205 => "00100111", +206 => "00100111", +207 => "00100110", +208 => "00100101", +209 => "00100100", +210 => "00100100", +211 => "00100011", +212 => "00100010", +213 => "00100001", +214 => "00100001", +215 => "00100000", +216 => "00011111", +217 => "00011110", +218 => "00011110", +219 => "00011101", +220 => "00011100", +221 => "00011011", +222 => "00011011", +223 => "00011010", +224 => "00011001", +225 => "00011000", +226 => "00011000", +227 => "00010111", +228 => "00010110", +229 => "00010101", +230 => "00010100", +231 => "00010100", +232 => "00010011", +233 => "00010010", +234 => "00010001", +235 => "00010001", +236 => "00010000", +237 => "00001111", +238 => "00001110", +239 => "00001101", +240 => "00001101", +241 => "00001100", +242 => "00001011", +243 => "00001010", +244 => "00001010", +245 => "00001001", +246 => "00001000", +247 => "00000111", +248 => "00000110", +249 => "00000110", +250 => "00000101", +251 => "00000100", +252 => "00000011", +253 => "00000010", +254 => "00000010", +255 => "00000001", +256 => "00000000"); + +signal dtemp : unsigned(17 downto 0); +signal din_buf : signed(17 downto 0); +signal dtemp1 : integer; +constant offset : unsigned(17 downto 0) := "000100000000000000"; + +begin + +process(CLK, RESET) +begin + if (RESET='1') then + dout <= (others => '0'); + din_buf <= (others => '0'); + dtemp <= (others => '0'); + dtemp1 <= 0; + elsif rising_edge(CLK) then + din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&din; + dtemp <= dtemp + unsigned(din_buf) + offset; + dtemp1 <= to_integer(dtemp(17 downto 8)); + if (dtemp1 >= 0) and (dtemp1 < 257) then + dout <= cosrom(dtemp1); + elsif (dtemp1 >= 257) and (dtemp1 < 513) then + dout <= -cosrom(512-dtemp1); + elsif (dtemp1 >= 513) and (dtemp1 < 769) then + dout <= -cosrom(dtemp1-512); + else + dout <= cosrom(1024-dtemp1); + end if; + end if; +end process; +END behavior; Index: all_digital_fm_receiver/tags/ver-1/fir.vhd =================================================================== --- all_digital_fm_receiver/tags/ver-1/fir.vhd (nonexistent) +++ all_digital_fm_receiver/tags/ver-1/fir.vhd (revision 5) @@ -0,0 +1,64 @@ +LIBRARY ieee; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + + +entity FIR is +port( + clock : in std_logic; + reset : in std_logic; + data_in : in signed(11 downto 0); + data_out : out std_logic_vector(11 downto 0) +); +end FIR; + +architecture behavior of FIR is + +signal d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15 : signed(15 downto 0); +signal sum : signed(15 downto 0); + +begin + +process(clock,reset) +begin + if (reset = '1') then + d0 <= (others => '0'); + d1 <= (others => '0'); + d2 <= (others => '0'); + d3 <= (others => '0'); + d4 <= (others => '0'); + d5 <= (others => '0'); + d6 <= (others => '0'); + d7 <= (others => '0'); + d8 <= (others => '0'); + d9 <= (others => '0'); + d10 <= (others => '0'); + d11 <= (others => '0'); + d12 <= (others => '0'); + d13 <= (others => '0'); + d14 <= (others => '0'); + d15 <= (others => '0'); + sum <= (others => '0'); + data_out <= (others => '0'); + ELSIF rising_edge(clock) THEN + d0 <= data_in(11)&data_in(11)&data_in(11)&data_in(11)&data_in; + d1 <= d0; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + d7 <= d6; + d8 <= d7; + d9 <= d8; + d10 <= d9; + d11 <= d10; + d12 <= d11; + d13 <= d12; + d14 <= d13; + d15 <= d14; + sum <= (d0+d1+d2+d3+d4+d5+d6+d7+d8+d9+d10+d11+d12+d13+d14+d15) srl 4; + data_out <= std_logic_vector(sum(11 downto 0)); + end if; +end process; +end behavior; \ No newline at end of file Index: all_digital_fm_receiver/tags/ver-1/fm.txt =================================================================== --- all_digital_fm_receiver/tags/ver-1/fm.txt (nonexistent) +++ all_digital_fm_receiver/tags/ver-1/fm.txt (revision 5) @@ -0,0 +1,1000 @@ +01111111 +01110110 +01011010 +00110000 +11111110 +11001101 +10100011 +10001000 +10000000 +10001100 +10101001 +11010100 +00000110 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all_digital_fm_receiver/tags/ver-1/circuit.vhd (nonexistent) +++ all_digital_fm_receiver/tags/ver-1/circuit.vhd (revision 5) @@ -0,0 +1,101 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + + + +ENTITY circuit IS +-- Declarations + PORT( + clk : IN std_logic; + reset : IN std_logic; + fmin : IN std_logic_vector(7 downto 0); + dmout : OUT std_logic_vector (11 DOWNTO 0) + ); +END circuit ; + + +ARCHITECTURE behavior OF circuit IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL d1 : signed(11 DOWNTO 0); + SIGNAL d2 : signed(11 DOWNTO 0); + SIGNAL dout : signed(7 DOWNTO 0); + SIGNAL output : signed(7 DOWNTO 0); + + + + -- Component Declarations + COMPONENT multiplier + PORT ( + clk : IN std_logic ; + reset : IN std_logic ; + input1 : IN std_logic_vector (7 DOWNTO 0); + input2 : IN signed (7 DOWNTO 0); + output : OUT signed (7 DOWNTO 0) + ); + END COMPONENT; + COMPONENT fir + PORT ( + clock : IN std_logic ; + reset : IN std_logic ; + data_in : IN signed (11 DOWNTO 0); + data_out : OUT std_logic_vector (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT loop_filter + PORT ( + clk : IN std_logic ; + reset : IN std_logic ; + c : IN signed (7 DOWNTO 0); + d1 : OUT signed (11 DOWNTO 0); + d2 : OUT signed (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT nco + PORT ( + clk : IN std_logic ; + reset : IN std_logic ; + din : IN signed (11 DOWNTO 0); + dout : OUT signed (7 DOWNTO 0) + ); + END COMPONENT; + + +BEGIN + -- Instance port mappings. + I1 : multiplier + PORT MAP ( + clk => clk, + reset => reset, + input1 => fmin, + input2 => dout, + output => output + ); + I4 : fir + PORT MAP ( + clock => clk, + reset => reset, + data_in => d1, + data_out => dmout + ); + I3 : loop_filter + PORT MAP ( + clk => clk, + reset => reset, + c => output, + d1 => d1, + d2 => d2 + ); + I2 : nco + PORT MAP ( + clk => clk, + reset => reset, + din => d2, + dout => dout + ); + + + END behavior; Index: all_digital_fm_receiver/tags/ver-1/cos.txt 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downto 0) + ); +END multiplier ; + + +ARCHITECTURE behavior OF multiplier IS + +signal out_temp : signed(15 downto 0); +signal input1_buf : signed(15 downto 0); +signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0); + +begin + +process(CLK, RESET) +begin + if (RESET='1') then + out_temp <= (others => '0'); + output <= (others => '0'); + input1_buf <= (others => '0'); + part0 <= (others => '0'); + part1 <= (others => '0'); + part2 <= (others => '0'); + part3 <= (others => '0'); + part4 <= (others => '0'); + part5 <= (others => '0'); + part6 <= (others => '0'); + part7 <= (others => '0'); + elsif rising_edge(CLK) then + input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1); + if (input2(0)='1') then + part0 <= -(input1_buf); + else + part0 <= (others => '0'); + end if; + if (input2(1)='1') then + if (input2(0)='1') then + part1 <= (others => '0'); + else + part1 <= -(input1_buf); + end if; + else + if (input2(0)='1') then + part1 <= input1_buf; + else + part1 <= (others => '0'); + end if; + end if; + if (input2(2)='1') then + if (input2(1)='1') then + part2 <= (others => '0'); + else + part2 <= -(input1_buf); + end if; + else + if (input2(1)='1') then + part2 <= input1_buf; + else + part2 <= (others => '0'); + end if; + end if; + if (input2(3)='1') then + if (input2(2)='1') then + part3 <= (others => '0'); + else + part3 <= -(input1_buf); + end if; + else + if (input2(2)='1') then + part3 <= input1_buf; + else + part3 <= (others => '0'); + end if; + end if; + if (input2(4)='1') then + if (input2(3)='1') then + part4 <= (others => '0'); + else + part4 <= -(input1_buf); + end if; + else + if (input2(3)='1') then + part4 <= input1_buf; + else + part4 <= (others => '0'); + end if; + end if; + if (input2(5)='1') then + if (input2(4)='1') then + part5 <= (others => '0'); + else + part5 <= -(input1_buf); + end if; + else + if (input2(4)='1') then + part5 <= input1_buf; + else + part5 <= (others => '0'); + end if; + end if; + if (input2(6)='1') then + if (input2(5)='1') then + part6 <= (others => '0'); + else + part6 <= -(input1_buf); + end if; + else + if (input2(5)='1') then + part6 <= input1_buf; + else + part6 <= (others => '0'); + end if; + end if; + if (input2(7)='1') then + if (input2(6)='1') then + part7 <= (others => '0'); + else + part7 <= -(input1_buf); + end if; + else + if (input2(6)='1') then + part7 <= input1_buf; + else + part7 <= (others => '0'); + end if; + end if; + out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000"); + output <= out_temp(15 downto 8); +end if; +end process; +END behavior; + Index: all_digital_fm_receiver/tags/ver-1/circuit_tb.vhd =================================================================== --- all_digital_fm_receiver/tags/ver-1/circuit_tb.vhd (nonexistent) +++ all_digital_fm_receiver/tags/ver-1/circuit_tb.vhd (revision 5) @@ -0,0 +1,64 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE std.textio.ALL; + +ENTITY circuit_tb IS +END circuit_tb; + +ARCHITECTURE behavior OF circuit_tb IS + +file vectors: text open read_mode is "fm.txt"; + + + COMPONENT circuit + PORT( + clk : IN std_logic; + reset : IN std_logic; + fmin : IN std_logic_vector(7 downto 0); + dmout : OUT std_logic_vector(11 downto 0) + ); + END COMPONENT; + + SIGNAL clk : std_logic := '0' ; + SIGNAL reset : std_logic := '1'; + SIGNAL fmin : std_logic_vector(7 downto 0); + SIGNAL dmout : std_logic_vector(11 downto 0); + constant clkperiod : time := 62.5 ns; -- 16 MHz of frequency + +BEGIN + + uut: circuit PORT MAP( + clk => clk, + reset => reset, + fmin => fmin, + dmout => dmout + ); + + RESET_GEN: process + begin + LOOP1: for N in 0 to 3 loop + wait until falling_edge(CLK); + end loop LOOP1; + RESET <= '0' ; + end process RESET_GEN; + +clk <= not clk after clkperiod / 2; + +process +variable vectorline : line; +variable fmin_var : bit_vector(7 downto 0); +begin +while not endfile(vectors) loop + if (reset = '1') then + fmin <= (others => '0'); + else + readline(vectors, vectorline); + read(vectorline, fmin_var); + fmin <= to_stdlogicvector(fmin_var); + end if; + wait for clkperiod; +end loop; +end process; + +END; Index: all_digital_fm_receiver/tags/ver-1/loop_filter.vhd =================================================================== --- all_digital_fm_receiver/tags/ver-1/loop_filter.vhd (nonexistent) +++ all_digital_fm_receiver/tags/ver-1/loop_filter.vhd (revision 5) @@ -0,0 +1,38 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + + + +ENTITY loop_filter IS +-- Declarations + port ( CLK : in std_logic; + RESET : in std_logic; + C : in signed(7 downto 0); + D1 : out signed(11 downto 0); + D2 : out signed(11 downto 0) + ); +END loop_filter ; + + +ARCHITECTURE behavior OF loop_filter IS + +signal E : signed(11 downto 0); +signal dtemp : signed(11 downto 0); + +begin +process(CLK, RESET) +begin + if (RESET='1') then + D1 <= (others => '0'); + D2 <= (others => '0'); + E <= (others => '0'); + dtemp <= (others => '0'); + elsif rising_edge(CLK) then + dtemp <= (C(7)&C(7)&C(7)&C&'0') + dtemp - E; + E <= dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11 downto 4); + D1 <= dtemp; + D2 <= dtemp(11 downto 4)&"0000"; + end if; +end process; +END behavior; Index: all_digital_fm_receiver/tags =================================================================== --- all_digital_fm_receiver/tags (nonexistent) +++ all_digital_fm_receiver/tags (revision 5)

all_digital_fm_receiver/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##