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URL https://opencores.org/ocsvn/apb_mstr/apb_mstr/trunk

Subversion Repositories apb_mstr

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    from Rev 4 to Rev 5
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Rev 4 → Rev 5

/apb_mstr/trunk/run/run.bat
1,6 → 1,4
 
echo off
 
..\..\..\robust.exe ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header
 
echo Completed RobustVerilog APB master run - results in run/out/
..\..\..\robust.exe ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header -gui -debug
/apb_mstr/trunk/run/run.sh
1,5 → 1,3
#!/bin/bash
 
../../../robust ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header ${@}
 
echo Completed RobustVerilog APB master run - results in run/out/
../../../robust ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
/apb_mstr/trunk/src/base/axi2apb_rd.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_rd.v
OUTFILE PREFIX_rd.v
 
module PREFIX_axi2apb_rd (PORTS);
module PREFIX_rd (PORTS);
 
input clk;
input reset;
/apb_mstr/trunk/src/base/def_apb_master_static.txt
26,21 → 26,25
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi_master.txt
 
SWAP.GLOBAL DATA_BITS 32 ##AXI and APB data bits
SWAP.GLOBAL ID_NUM 1 ##Number of IDs (internal masters)
SWAP.GLOBAL ID0_VAL ID_BITS'b0000 ##AXI ID0
 
GROUP STUB_AXI_A overrides {
ID ID_BITS output
ADDR ADDR_BITS output
LEN LEN_BITS output
SIZE SIZE_BITS output
VALID 1 output
READY 1 input
}
 
 
ENDUSER ##don't use AXI master USER params in gui
INCLUDE def_axi_master.txt
STARTUSER
 
SWAP MODEL_NAME APB master stub
SWAP.GLOBAL DATA_BITS 32 ##AXI and APB data bits
SWAP.GLOBAL ID_NUM 1 ##Number of IDs (internal masters)
SWAP.GLOBAL ID0_VAL ID_BITS'b0000 ##AXI ID0
 
GROUP STUB_AXI_A overrides {
ID ID_BITS output
ADDR ADDR_BITS output
LEN LEN_BITS output
SIZE SIZE_BITS output
VALID 1 output
READY 1 input
}
 
/apb_mstr/trunk/src/base/apb_master.v
65,13 → 65,13
//////////////////////////////////////
 
 
OUTFILE apb_master.v
OUTFILE PREFIX.v
 
INCLUDE def_apb_master.txt
 
VERIFY (DATA_BITS==32) else only 32 bit data supported
module apb_master(PORTS);
module PREFIX(PORTS);
 
input clk;
99,18 → 99,18
initial
begin
#1;
apb_master_axi_master.enable_all;
apb_master_axi_master.use_addr_base=1;
apb_master_axi_master.len_min=0;
apb_master_axi_master.len_max=0;
apb_master_axi_master.size_min=2;
apb_master_axi_master.size_max=2;
PREFIX_axi_master.enable_all;
PREFIX_axi_master.use_addr_base=1;
PREFIX_axi_master.len_min=0;
PREFIX_axi_master.len_max=0;
PREFIX_axi_master.size_min=2;
PREFIX_axi_master.size_max=2;
end
CREATE axi_master.v DEFCMD(SWAP.GLOBAL CONST(PREFIX) apb_master_axi_master)
CREATE axi_master.v DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi_master)
apb_master_axi_master apb_master_axi_master(
PREFIX_axi_master PREFIX_axi_master(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
118,9 → 118,9
);
 
CREATE axi2apb.v DEFCMD(SWAP CONST(SLAVE_NUM) 1) DEFCMD(SWAP.GLOBAL CONST(PREFIX) apb_master)
CREATE axi2apb.v DEFCMD(SWAP CONST(SLAVE_NUM) 1) DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi2apb)
 
apb_master_axi2apb apb_master_axi2apb(
PREFIX_axi2apb PREFIX_axi2apb(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
140,7 → 140,7
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] wdata;
begin
apb_master_axi_master.write_single(0, addr, wdata);
PREFIX_axi_master.write_single(0, addr, wdata);
end
endtask
 
148,7 → 148,7
input [ADDR_BITS-1:0] addr;
output [DATA_BITS-1:0] rdata;
begin
apb_master_axi_master.read_single(0, addr, rdata);
PREFIX_axi_master.read_single(0, addr, rdata);
end
endtask
 
156,7 → 156,7
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] expected;
begin
apb_master_axi_master.check_single(0, addr, expected);
PREFIX_axi_master.check_single(0, addr, expected);
end
endtask
 
164,7 → 164,7
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] data;
begin
apb_master_axi_master.write_and_check_single(0, addr, data);
PREFIX_axi_master.write_and_check_single(0, addr, data);
end
endtask
 
/apb_mstr/trunk/src/base/def_axi2apb.txt
31,21 → 31,21
 
SWAP #FFD #1 ## flip-flop delay
 
SWAP PREFIX soc ## prefix for all modules and file names
SWAP.USER PREFIX axi2apb ## prefix for all modules and file names
 
SWAP SLAVE_NUM 8 ## number of APB slaves
SWAP.USER SLAVE_NUM 8 ## number of APB slaves
 
SWAP CMD_DEPTH 2 ## number of AXI command FIFO
SWAP.USER CMD_DEPTH 2 ## number of AXI command FIFO
 
SWAP ADDR_BITS 24 ## AXI and APB address bits
SWAP ID_BITS 4 ## AXI ID bits
SWAP DEC_BITS 8 ## Address MSBits for slave decoding
SWAP.USER ADDR_BITS 24 ## AXI and APB address bits
SWAP.USER ID_BITS 4 ## AXI ID bits
SWAP.USER DEC_BITS 8 ## Address MSBits for slave decoding
 
SWAP DEC_ADDR0 DEC_BITS'h00 ## Slave 0 address deciding
SWAP DEC_ADDR1 DEC_BITS'h01 ## Slave 1 address deciding
SWAP DEC_ADDR2 DEC_BITS'h02 ## Slave 2 address deciding
SWAP DEC_ADDR3 DEC_BITS'h03 ## Slave 3 address deciding
SWAP DEC_ADDR4 DEC_BITS'h10 ## Slave 4 address deciding
SWAP DEC_ADDR5 DEC_BITS'h11 ## Slave 5 address deciding
SWAP DEC_ADDR6 DEC_BITS'h12 ## Slave 6 address deciding
SWAP DEC_ADDR7 DEC_BITS'h13 ## Slave 7 address deciding
SWAP.USER DEC_ADDR0 DEC_BITS'h00 ## Slave 0 address deciding
SWAP.USER DEC_ADDR1 DEC_BITS'h01 ## Slave 1 address deciding
SWAP.USER DEC_ADDR2 DEC_BITS'h02 ## Slave 2 address deciding
SWAP.USER DEC_ADDR3 DEC_BITS'h03 ## Slave 3 address deciding
SWAP.USER DEC_ADDR4 DEC_BITS'h10 ## Slave 4 address deciding
SWAP.USER DEC_ADDR5 DEC_BITS'h11 ## Slave 5 address deciding
SWAP.USER DEC_ADDR6 DEC_BITS'h12 ## Slave 6 address deciding
SWAP.USER DEC_ADDR7 DEC_BITS'h13 ## Slave 7 address deciding
/apb_mstr/trunk/src/base/axi2apb_mux.v
28,10 → 28,10
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_mux.v
OUTFILE PREFIX_mux.v
 
ITER SX
module PREFIX_axi2apb_mux (PORTS);
module PREFIX_mux (PORTS);
 
 
input clk;
/apb_mstr/trunk/src/base/def_axi_master.txt
26,23 → 26,23
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi_master_static.txt
 
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
SWAP PREFIX axi_master ##prefix for all module and file names
SWAP ID_BITS 4 ##AXI ID bits
SWAP ADDR_BITS 32 ##AXI address bits
SWAP DATA_BITS 64 ##AXI data bits
SWAP LEN_BITS 4 ##AXI LEN bits
SWAP SIZE_BITS 2 ##AXI SIZE bits
 
SWAP CMD_DEPTH 4 ##AXI command depth for read and write
 
SWAP ID_NUM 3 ##Number of IDs (internal masters)
SWAP ID0_VAL ID_BITS'b0011 ##AXI ID0
SWAP ID1_VAL ID_BITS'b0010 ##AXI ID1
SWAP ID2_VAL ID_BITS'b1010 ##AXI ID2
 
 
INCLUDE def_axi_master_static.txt
 
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
SWAP.USER PREFIX axi_master ##prefix for all module and file names
SWAP.USER ID_BITS 4 ##AXI ID bits
SWAP.USER ADDR_BITS 32 ##AXI address bits
SWAP.USER DATA_BITS 64 ##AXI data bits
SWAP.USER LEN_BITS 4 ##AXI LEN bits
SWAP.USER SIZE_BITS 2 ##AXI SIZE bits
 
SWAP.USER CMD_DEPTH 4 ##AXI command depth for read and write
 
SWAP.USER ID_NUM 3 ##Number of IDs (internal masters)
SWAP.USER ID0_VAL ID_BITS'b0011 ##AXI ID0
SWAP.USER ID1_VAL ID_BITS'b0010 ##AXI ID1
SWAP.USER ID2_VAL ID_BITS'b1010 ##AXI ID2
 
/apb_mstr/trunk/src/base/def_axi2apb_static.txt
27,6 → 27,8
//// ////
//////////////////////////////////////////////////////////////////##>
 
SWAP MODEL_NAME AXI2APB bridge
SWAP SLV_BITS LOG2(EXPR(SLAVE_NUM+1)) ##one more for decerr slave
 
LOOP SX SLAVE_NUM
/apb_mstr/trunk/src/base/axi2apb.v
28,10 → 28,10
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb.v
OUTFILE PREFIX.v
 
ITER SX
module PREFIX_axi2apb (PORTS);
module PREFIX (PORTS);
 
input clk;
input reset;
73,7 → 73,7
 
CREATE axi2apb_cmd.v
PREFIX_axi2apb_cmd PREFIX_axi2apb_cmd(
PREFIX_cmd PREFIX_cmd(
.clk(clk),
.reset(reset),
.AWGROUP_APB_AXI_A(AWGROUP_APB_AXI_A),
89,7 → 89,7
 
CREATE axi2apb_rd.v
PREFIX_axi2apb_rd PREFIX_axi2apb_rd(
PREFIX_rd PREFIX_rd(
.clk(clk),
.reset(reset),
.GROUP_APB3(GROUP_APB3),
101,7 → 101,7
);
CREATE axi2apb_wr.v
PREFIX_axi2apb_wr PREFIX_axi2apb_wr(
PREFIX_wr PREFIX_wr(
.clk(clk),
.reset(reset),
.GROUP_APB3(GROUP_APB3),
116,7 → 116,7
 
CREATE axi2apb_ctrl.v
PREFIX_axi2apb_ctrl PREFIX_axi2apb_ctrl(
PREFIX_ctrl PREFIX_ctrl(
.clk(clk),
.reset(reset),
.finish_wr(finish_wr),
133,7 → 133,7
IFDEF TRUE(SLAVE_NUM>1)
CREATE axi2apb_mux.v
PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
PREFIX_mux PREFIX_mux(
.clk(clk),
.reset(reset),
.cmd_addr(cmd_addr),
/apb_mstr/trunk/src/base/def_axi_master_static.txt
27,6 → 27,8
//// ////
//////////////////////////////////////////////////////////////////##>
 
SWAP MODEL_NAME AXI master stub
VERIFY (DATA_BITS <= 64) else stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus
 
/apb_mstr/trunk/src/base/axi2apb_wr.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_wr.v
OUTFILE PREFIX_wr.v
 
module PREFIX_axi2apb_wr (PORTS);
module PREFIX_wr (PORTS);
 
input clk;
input reset;
/apb_mstr/trunk/src/base/def_apb_master.txt
31,7 → 31,9
 
SWAP.GLOBAL #FFD #1 ##Flip-flop delay
SWAP.GLOBAL ADDR_BITS 16 ##APB address bits
SWAP.USER PREFIX apb_master ##Prefix for all module and file names
SWAP.GLOBAL.USER ADDR_BITS 16 ##APB address bits
 
DEFINE APB3 ##if set use pready and pslverr APB3 signals
DEFINE.USER APB3 ##if set use pready and pslverr APB3 signals
/apb_mstr/trunk/src/base/axi2apb_cmd.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_cmd.v
OUTFILE PREFIX_cmd.v
 
module PREFIX_axi2apb_cmd (PORTS);
module PREFIX_cmd (PORTS);
 
input clk;
input reset;
/apb_mstr/trunk/src/base/axi2apb_ctrl.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_ctrl.v
OUTFILE PREFIX_ctrl.v
 
module PREFIX_axi2apb_ctrl (PORTS);
module PREFIX_ctrl (PORTS);
 
 
input clk;

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