URL
https://opencores.org/ocsvn/artec_dongle_ii_fpga/artec_dongle_ii_fpga/trunk
Subversion Repositories artec_dongle_ii_fpga
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Rev 4 → Rev 5
/trunk/src/bus_arbiter/bus_arbiter.vhd
0,0 → 1,78
------------------------------------------------------------------ |
-- Universal dongle board source code |
-- |
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee> |
-- |
-- This source code is free hardware; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
-- License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- |
-- This source code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public |
-- License along with this library; if not, write to the Free Software |
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
-- |
-- |
-- The complete text of the GNU Lesser General Public License can be found in |
-- the file 'lesser.txt'. |
|
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library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.std_logic_arith.all; |
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use bus_arbiter_pkg.all; |
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entity bus_arbiter is |
generic ( |
dev_count: integer:= 1; |
has_clock: array(integer range 0 to dev_count-1) of std_logic:=(others=>'0') --if provided clock should be used |
); |
port ( |
clk : in std_logic; --default system clock |
reset_n : in std_logic; |
-- mem Bus out |
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mem_clk : out std_logic; |
mem_rstn : out std_logic; --reset to mem block (used when mux'ing clock) |
mem_addr : out std_logic_vector(23 downto 0); |
mem_do : out std_logic_vector(15 downto 0); |
mem_di : in std_logic_vector(15 downto 0); |
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mem_wr : out std_logic; --write not read signal |
mem_val : out std_logic; |
mem_ack : in std_logic; |
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-- dev Bus in |
dev_clk : in array(integer range 0 to dev_count-1) of std_logic; --clock option |
dev_addr : in array(integer range 0 to dev_count-1) of std_logic_vector(23 downto 0); |
dev_do : out array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0); |
dev_di : in array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0); |
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dev_wr : in array(integer range 0 to dev_count-1) of std_logic; --write not read signal |
dev_val : in array(integer range 0 to dev_count-1) of std_logic; |
dev_ack : out array(integer range 0 to dev_count-1) of std_logic |
); |
end bus_arbiter; |
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architecture RTL of bus_arbiter is |
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begin |
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end RTL; |
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/trunk/src/bus_arbiter/bus_arbiter_pkg.vhd
0,0 → 1,19
package bus_arbiter_pkg is |
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type vci_master is |
record |
dev_clk : array(integer range 0 to dev_count-1) of std_logic; --clock option |
dev_addr : array(integer range 0 to dev_count-1) of std_logic_vector(23 downto 0); |
dev_do : array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0); |
dev_di : array(integer range 0 to dev_count-1) of std_logic_vector(15 downto 0); |
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dev_wr : array(integer range 0 to dev_count-1) of std_logic; --write not read signal |
dev_val : array(integer range 0 to dev_count-1) of std_logic; |
dev_ack : array(integer range 0 to dev_count-1) of std_logic; |
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end record; |
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end bus_arbiter_pkg; |