URL
https://opencores.org/ocsvn/axi_vga_fb/axi_vga_fb/trunk
Subversion Repositories axi_vga_fb
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- from Rev 4 to Rev 5
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Rev 4 → Rev 5
/axi_vga_fb/trunk/v586fb_rgb656.c
0,0 → 1,130
/* |
* linux/drivers/video/v586fb.c -- v586 frame buffer device |
* |
* Copyright (C) 2017 |
* |
* Valptek <contact@valptek.com> |
* |
* This file is subject to the terms and conditions of the GNU General Public |
* License. See the file COPYING in the main directory of this archive for |
* more details. |
*/ |
|
#include <linux/kernel.h> |
#include <linux/errno.h> |
#include <linux/string.h> |
#include <linux/mm.h> |
#include <linux/delay.h> |
#include <linux/interrupt.h> |
#include <linux/platform_device.h> |
|
#include <asm/uaccess.h> |
#include <asm/setup.h> |
#include <linux/fb.h> |
#include <linux/module.h> |
#include <asm/pgtable.h> |
|
#define v586_PHYS_SCREEN_ADDR 0x40F00000 |
#define v586_PHYS_SCREEN_SIZE 0x00040000 |
/* static void *videomemory; */ |
static u_long videomemorysize = v586_PHYS_SCREEN_SIZE; |
module_param(videomemorysize, ulong, 0); |
|
static struct fb_fix_screeninfo v586fb_fix = { |
.id = "v586fb", |
.smem_len = 640*200*2, |
.type = FB_TYPE_PACKED_PIXELS, |
.visual = FB_VISUAL_TRUECOLOR, |
.line_length = 640*2, |
.accel = FB_ACCEL_NONE, |
}; |
|
static struct fb_var_screeninfo v586fb_var = { |
.xres = 640, |
.yres = 200, |
.xres_virtual = 640, |
.yres_virtual = 200, |
.bits_per_pixel = 16, |
.red = {11, 5, 0}, |
.green = {5, 6, 0}, |
.blue = {0, 5, 0}, |
.activate = FB_ACTIVATE_NOW, |
.height = 230, |
.width = 300, |
.vmode = FB_VMODE_NONINTERLACED, |
}; |
|
static struct fb_ops v586fb_ops = { |
.owner = THIS_MODULE, |
.fb_fillrect = cfb_fillrect, |
.fb_copyarea = cfb_copyarea, |
.fb_imageblit = cfb_imageblit, |
}; |
|
static int v586fb_probe(struct platform_device *dev) |
{ |
struct fb_info *info; |
|
v586fb_fix.smem_start = v586_PHYS_SCREEN_ADDR; |
|
info = framebuffer_alloc(sizeof(u32) * 16, &dev->dev); |
if (!info) |
return -ENOMEM; |
|
if (!request_mem_region(v586_PHYS_SCREEN_ADDR, v586_PHYS_SCREEN_SIZE, "v586fb")) { |
printk(KERN_INFO"v586fb: cannot get framebuffer\n"); |
} |
|
info->var = v586fb_var; |
info->fix = v586fb_fix; |
info->fbops = &v586fb_ops; |
info->flags = FBINFO_DEFAULT; /* not as module for now */ |
info->par = NULL; |
info->screen_base = ioremap(v586_PHYS_SCREEN_ADDR,videomemorysize); /* (char *) v586fb_fix.smem_start; */ |
|
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { |
framebuffer_release(info); |
return -ENOMEM; |
} |
|
if (register_framebuffer(info) < 0) { |
printk(KERN_ERR "Unable to register v586fb frame buffer\n"); |
fb_dealloc_cmap(&info->cmap); |
framebuffer_release(info); |
return -EINVAL; |
} |
|
fb_info(info, "v586fb frame buffer alive and kicking !\n"); |
return 0; |
} |
|
static struct platform_driver v586fb_driver = { |
.probe = v586fb_probe, |
.driver = { |
.name = "v586fb", |
}, |
}; |
|
static struct platform_device v586fb_device = { |
.name = "v586fb", |
}; |
|
int __init v586fb_init(void) |
{ |
int ret = 0; |
|
if (fb_get_options("v586fb", NULL)) |
return -ENODEV; |
|
ret = platform_driver_register(&v586fb_driver); |
|
if (!ret) { |
ret = platform_device_register(&v586fb_device); |
if (ret) |
platform_driver_unregister(&v586fb_driver); |
} |
return ret; |
} |
|
module_init(v586fb_init); |
MODULE_LICENSE("GPL"); |
axi_vga_fb/trunk/v586fb_rgb656.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: axi_vga_fb/trunk/vga_rgb565.v
===================================================================
--- axi_vga_fb/trunk/vga_rgb565.v (nonexistent)
+++ axi_vga_fb/trunk/vga_rgb565.v (revision 5)
@@ -0,0 +1,157 @@
+///////////////////////////////////
+// AXI to VGA frame buffer
+// fixed 640x200x16bpp RGB565 , 256kByte internal vram ressource
+// (c) Valptek 2017
+///////////////////////////////////
+
+
+module vga(
+ input s00_AXI_RSTN,
+ input s00_AXI_CLK,
+ output [3:0] r4,g4,b4,
+ output hz,vt,
+ // axi bus
+ input [31:0] s00_AXI_AWADDR, s00_AXI_ARADDR,
+ input s00_AXI_AWVALID,s00_AXI_ARVALID,s00_AXI_WVALID,s00_AXI_RREADY,s00_AXI_WLAST,
+ output reg s00_AXI_AWREADY,s00_AXI_ARREADY,s00_AXI_WREADY,s00_AXI_RVALID,s00_AXI_RLAST,
+ output reg [31:0] s00_AXI_RDATA,
+ input [31:0] s00_AXI_WDATA,
+ input [3:0] s00_AXI_WSTRB,
+ input [1:0] s00_AXI_ARBURST,
+ input [7:0] s00_AXI_ARLEN,
+ input [2:0] s00_AXI_ARSIZE,
+ input [1:0] s00_AXI_AWBURST,
+ input [7:0] s00_AXI_AWLEN,
+ input [2:0] s00_AXI_AWSIZE,
+ input s00_AXI_BREADY,
+ output s00_AXI_BVALID
+ );
+
+// video ram
+reg [7:0] vmem1 [0:(640*200/2)-1];
+reg [7:0] vmem2 [0:(640*200/2)-1];
+reg [7:0] vmem3 [0:(640*200/2)-1];
+reg [7:0] vmem4 [0:(640*200/2)-1];
+
+reg [7:0] Qreg1,Qreg2,Qreg3,Qreg4;
+reg [15:0] wadd,radd,vadd,gadd;
+reg [1:0] vbits;
+reg wreq1,wreq2,wreq3,wreq4;
+
+reg [15:0] fifo;
+reg [31:0] wdat;
+reg [1:0] gclk;
+reg [9:0] counX, counY;
+wire [9:0] nextcounX;
+reg hSync, vSync;
+reg rd_rq,wr_rq,wr_gnt,rd_gnt;
+reg [3:0] wr_strb;
+
+
+always @(posedge s00_AXI_CLK) Qreg1 <= vmem1[vadd];
+always @(posedge s00_AXI_CLK) Qreg2 <= vmem2[vadd];
+always @(posedge s00_AXI_CLK) Qreg3 <= vmem3[vadd];
+always @(posedge s00_AXI_CLK) Qreg4 <= vmem4[vadd];
+
+
+always @(posedge s00_AXI_CLK) if (wreq1) vmem1[vadd] <= wdat[31:24];
+always @(posedge s00_AXI_CLK) if (wreq2) vmem2[vadd] <= wdat[23:16];
+always @(posedge s00_AXI_CLK) if (wreq3) vmem3[vadd] <= wdat[15:8];
+always @(posedge s00_AXI_CLK) if (wreq4) vmem4[vadd] <= wdat[7:0];
+
+//
+// Internal BUS : write generate & decode + round robin for video display
+//
+always @(posedge s00_AXI_CLK or negedge s00_AXI_RSTN)
+if (s00_AXI_RSTN == 0)
+ begin
+ s00_AXI_AWREADY <= 0;
+ s00_AXI_ARREADY <= 0;
+ s00_AXI_WREADY <= 0;
+ s00_AXI_RVALID <= 0;
+ s00_AXI_RLAST <= 0;
+ rd_rq <= 0;
+ wr_rq <= 0;
+ end
+else
+begin
+ if ( ((s00_AXI_AWVALID == 1) && (s00_AXI_AWREADY ==0)) ) begin s00_AXI_AWREADY <=1; wadd <= s00_AXI_AWADDR[17:2]; end
+
+ if ( ((s00_AXI_ARVALID == 1) && (s00_AXI_ARREADY ==0)) ) begin rd_rq <= 1; s00_AXI_ARREADY <=1; radd <= s00_AXI_ARADDR[17:2]; end else
+ begin
+ s00_AXI_ARREADY <=0;
+ s00_AXI_AWREADY <=0;
+ if (rd_gnt ==1)
+ begin
+ rd_rq <=0;
+
+ s00_AXI_RVALID <= 1;
+ s00_AXI_RLAST <= 1;
+ end
+ else
+ begin
+ s00_AXI_RVALID <= 0;
+ s00_AXI_RLAST <= 1;
+ end
+ end
+
+ if ( wr_gnt == 1) begin s00_AXI_WREADY <=1; wr_rq <=0; wr_strb <= 0; end else
+ if ((s00_AXI_WVALID == 1) && (s00_AXI_WREADY ==0)) begin wr_rq <= 1; wr_strb <= s00_AXI_WSTRB; wdat <= s00_AXI_WDATA; end else
+ s00_AXI_WREADY <=0;
+
+
+end
+
+
+// clock divider gap
+always @(posedge s00_AXI_CLK) if (~s00_AXI_RSTN) gclk <=0; else gclk <= gclk + 1;
+
+// vram read write control
+always @(posedge s00_AXI_CLK)
+ if (~s00_AXI_RSTN)
+ begin
+ gadd <= 0;
+ fifo <= 0;
+ rd_gnt <= 0;
+ wr_gnt <= 0;
+ vadd <= 0;
+ s00_AXI_RDATA <=0;
+ end
+ else
+ begin
+ if ((gclk == 0) && (wr_rq ==1)) begin wr_gnt <= 1; vadd <= wadd; {wreq1,wreq2,wreq3,wreq4} <= wr_strb; end else
+ if ((gclk == 0) && (rd_rq ==1)) begin vadd <= radd; end else
+ if ((gclk == 1) && (wr_rq ==1)) begin {wreq1,wreq2,wreq3,wreq4} <= 0; vadd <= gadd; end else
+ if ((gclk == 1) && (rd_rq ==1)) begin rd_gnt <= 1; vadd <= gadd; end else
+ if (gclk == 1) begin vadd <= gadd; end else
+ if (gclk == 2) begin wr_gnt <=0; rd_gnt <=0; s00_AXI_RDATA <= {Qreg1,Qreg2,Qreg3,Qreg4}; end
+
+ // update video address
+ if ((counY < 10'd400) && (nextcounX <10'd640)) gadd <=nextcounX[9:1]+{counY[9:1],8'b0}+{counY[9:1],6'b0};
+ if (gclk == 3) begin
+ if (nextcounX[0] == 1'b1) fifo <= {Qreg1,Qreg2}; else fifo <= {Qreg3,Qreg4};
+ end
+ end
+
+// raster
+always @(posedge s00_AXI_CLK) if (~s00_AXI_RSTN) counX <=0; else if (gclk ==3) begin if (counX==799) counX <=0; else counX <= nextcounX; end
+always @(posedge s00_AXI_CLK) if (~s00_AXI_RSTN) counY <=0; else if((gclk ==3)&&(counX==799)) begin if (counY==524) counY <= 0; else counY <= counY + 1'b1; end
+
+always @(posedge s00_AXI_CLK) if (~s00_AXI_RSTN) hSync <=0; else hSync <= (counX>=656) && (counX<752);
+always @(posedge s00_AXI_CLK) if (~s00_AXI_RSTN) vSync <=0; else vSync <= (counY>=490) && (counY<492);
+
+// dac
+assign r4 = (counX>639) ? 0 : (counY>399) ? 0 :
+ fifo[15:12];
+
+assign g4 = (counX>639) ? 0 : (counY>399) ? 0 :
+ fifo[10:7];
+
+assign b4 = (counX>639) ? 0 : (counY>399) ? 0 :
+ fifo[ 4: 1];
+
+assign hz = ~hSync;
+assign vt = vSync;
+assign nextcounX = counX +1;
+
+endmodule