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Rev 4 → Rev 5

/trunk/CODE/LIBS/hdlc_components_pkg.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update : 2000/12/30
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
33,6 → 33,14
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : RxEnable bug fixed
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
73,6 → 81,8
rst : in std_logic;
FlagDetect : out std_logic;
Abort : out std_logic;
RXEN : in std_logic;
RXEN_O : out std_logic;
RXD : out std_logic;
RX : in std_logic);
end component;
85,7 → 95,7
RxData : out std_logic_vector(7 downto 0);
ValidFrame : out std_logic;
AbortSignal : out std_logic;
FrameError : out std_logic;
FrameError : out std_logic;
Readbyte : in std_logic;
rdy : out std_logic;
RxEn : in std_logic);
/trunk/CODE/RX/TB/Rx_tb.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update : 2000/12/30
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
33,6 → 33,15
-- ToOptimize : Add an input procedure to insert data pattern
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Rx Enable and delayed Read tests are added
-- ToOptimize : Add an input procedure to insert data pattern
-- Bugs :
-------------------------------------------------------------------------------
 
 
 
68,27 → 77,11
rst_i <= '0',
'1' after 30 ns;
 
RxEn_i <= '1';
RxEn_i <= '1',
'0' after 960 ns,
'1' after 1280 ns;
-------------------------------------------------------------------------------
-- purpose: Generate data
-- type : sequential
-- inputs :
-- outputs:
-- send_data_proc : process
-- begin -- process send_data_proc
--RxEn_i <= '1';
-- Rx_i <= '0';
-- wait until rst_i = '1';
 
 
-- for i in 0 to DataStreem'length -1 loop
-- wait until Rxclk_i = '0';
-- Rx_i <= DataStreem(i);
 
 
-- end loop; -- i
-- end process send_data_proc;
 
-- purpose: Serial interface stimulus
-- type : sequential
-- inputs :
118,10 → 111,14
variable counter : integer := 0; -- Counter
begin -- process backend_proc
if rdy_i = '1' then
if counter mod 2 = 0 then
-- Counter is used to generate Readbyte signal at different delays
if not((counter > 20) and (counter < 40)) then
Readbyte_i <= '1' after 60 ns;
elsif(counter mod 2 = 0) then
-- data bits will be lost in this case
Readbyte_i <= '1' after 350 ns;
else
Readbyte_i <= '1' after 350 ns;
Readbyte_i <= '1' after 60 ns;
end if;
counter := counter+1;
else
/trunk/CODE/RX/SCRIPTS/WAVE.DO
3,16 → 3,18
add wave -noupdate -format Logic /rx_tb_ent/rxclk_i
add wave -noupdate -format Logic /rx_tb_ent/rst_i
add wave -noupdate -format Logic /rx_tb_ent/rx_i
add wave -noupdate -format Logic /rx_tb_ent/uut/rxd_i
add wave -noupdate -format Literal /rx_tb_ent/rxdata_i
add wave -noupdate -format Logic /rx_tb_ent/validframe_i
add wave -noupdate -format Logic /rx_tb_ent/readbyte_i
add wave -noupdate -format Logic /rx_tb_ent/rdy_i
add wave -noupdate -format Logic /rx_tb_ent/rxen_i
add wave -noupdate -format Logic /rx_tb_ent/uut/rxd_i
add wave -noupdate -format Logic /rx_tb_ent/uut/enable_i
add wave -noupdate -format Logic /rx_tb_ent/uut/aval_i
add wave -noupdate -format Logic /rx_tb_ent/uut/flagdetect_i
add wave -noupdate -format Logic /rx_tb_ent/validframe_i
add wave -noupdate -format Logic /rx_tb_ent/uut/initzero_i
add wave -noupdate -format Logic /rx_tb_ent/frameerror_i
add wave -noupdate -format Logic /rx_tb_ent/abortsignal_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {399808 ps}
WaveRestoreZoom {0 ps} {1463296 ps}
WaveRestoreCursors {806902 ps}
WaveRestoreZoom {0 ps} {2940 ns}
/trunk/CODE/RX/CORE/flag_detect.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update: 2001/01/05
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
40,7 → 40,14
-- Desccription : Code clean
--
-------------------------------------------------------------------------------
 
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : RXEN bug fixed
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
51,6 → 58,8
rst : in std_logic; -- system reset
FlagDetect : out std_logic; -- Flag detected
Abort : out std_logic; -- Abort signal detected
RxEn : in std_logic; -- RX enable
RXEn_O : out std_logic; -- RXEN output signal
RXD : out std_logic; -- RXD output
RX : in std_logic); -- RX signal
 
66,13 → 75,14
-- type : sequential
-- inputs : RXclk, rst
-- outputs:
bitstreem_proc : process (RXclk, rst)
bitstreem_proc : process (RXclk, rst)
 
variable FlagVar : std_logic; -- Flag detected variable
variable FlagVar : std_logic; -- Flag detected variable
variable Enable_Reg : std_logic_vector(7 downto 0); -- Enable Register
 
begin -- process bitstreem_proc
if rst = '0' then -- asynchronous reset (active low)
 
-- state := IDLE;
FlagDetect <= '0';
Abort <= '0';
 
82,6 → 92,9
 
ShiftReg <= (others => '0');
 
RXEN_O <= '1';
Enable_Reg := (others => '1');
 
elsif RXclk'event and RXclk = '1' then -- rising clock edge
 
FlagVar := not ShiftReg(0) and ShiftReg(1) and ShiftReg(2) and ShiftReg(3) and ShiftReg(4) and ShiftReg(5) and ShiftReg(6) and not ShiftReg(7);
94,7 → 107,10
ShiftReg(7 downto 0) <= RX & ShiftReg(7 downto 1);
RXD <= ShiftReg(0);
 
RXEN_O <= Enable_Reg(0);
 
Enable_Reg(7 downto 0) := RXEN & Enable_Reg(7 downto 1);
 
end if;
end process bitstreem_proc;
 
/trunk/CODE/RX/CORE/RxChannel.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update : 2000/12/30
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
33,10 → 33,19
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : RXEN bug fixed
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.hdlc_components_pkg.all;
use work.hdlc_components_pkg.all;
 
entity RxChannel_ent is
 
63,6 → 72,8
signal FlagDetect_i : std_logic; -- flag Detect internal
signal Abort_i : std_logic; -- Internal Abort signal
signal initzero_i : std_logic; -- Init Zero detect block
signal rxen_i : std_logic; -- RXenable internal
 
begin -- RxChannel_beh
 
-------------------------------------------------------------------------------
71,7 → 82,7
port map (
RxClk => RxClk,
rst => rst,
RxEn => RxEn,
RxEn => RxEn_i,
AbortedFrame => AbortSignal,
Abort => Abort_i,
FlagDetect => FlagDetect_i,
99,6 → 110,8
rst => rst,
FlagDetect => FlagDetect_i,
Abort => Abort_i,
RXEN => RXEN,
RxEN_o => RXEN_i,
RXD => RXD_i,
RX => RX);
-------------------------------------------------------------------------------
/trunk/CODE/RX/CORE/Zero_detect.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update : 2000/1/1
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: FPGA express 3
34,6 → 34,16
-- for low speed backend interface
-- (flow control is used to manage this problem)
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Enable bug fixed
-- ToOptimize : Needs large external buffer (1 byte internal buffer)
-- for low speed backend interface
-- (flow control is used to manage this problem)
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
96,12 → 106,12
if StartofFrame = '0' then
 
-- add new bit to the check register
checkreg := RxD & checkreg(5 downto 1);
tempRegister(counter) := RxD;
checkreg := RxD & checkreg(5 downto 1);
tempRegister(counter) := RxD;
else
-- reset the check register
checkreg := (RxD , others => '0');
counter := 0;
checkreg := (RxD, others => '0');
counter := 0;
tempRegister(counter) := RxD;
end if;
 
162,17 → 172,18
rdy <= '0';
 
elsif Rxclk'event and Rxclk = '1' then -- rising clock edge
if enable = '1' then
 
if flag = '1' then
 
if flag = '1' then
status := '1'; -- Can not take more
 
status := '1'; -- Can not take more
RxData <= DataRegister;
rdy_var := '1';
 
RxData <= DataRegister;
rdy_var := '1';
end if; -- flag
 
end if;
 
end if; -- enable
if readbyte = '1' then
 
status := '0'; -- can take more data
179,68 → 190,15
 
rdy_var := '0';
 
end if;
end if; -- readbyte
 
rdy <= rdy_var;
aval <= not status;
end if; -- clk
 
end if;
 
 
 
end process backend_proc;
 
-------------------------------------------------------------------------------
 
-- purpose: serial to Parallel conversion and inserted Zero detection
-- type : sequential
-- inputs : Rxclk, rst
-- outputs:
-- S2P_proc : process (Rxclk, rst)
 
 
-- variable tmpdatareg : std_logic_vector(MAX_REG_SIZE-1 downto 0);
-- -- Temporary variable for storing data
 
-- begin -- process P2S_proc
-- if rst = '0' then -- asynchronous reset (active low)
-- counter := 0;
-- DataRegister <= (others => '0');
 
 
-- elsif Rxclk'event and Rxclk = '1' then -- rising clock edge
 
-- -- 01111101 must be set back to 0111111
-- ZeroDetected := DataRegister(0) and not DataRegister(1) and DataRegister(2) and DataRegister(3) and DataRegister(4) and DataRegister(5) and DataRegister(6);
 
 
-- tmpdatareg(MAX_REG_SIZE-1) := RxD; -- new data
 
-- if ZeroDetected = '1' then -- check old data if it contains inserted zero
 
-- tmpdatareg(MAX_REG_SIZE-2 downto 0) := tmpdatareg(MAX_REG_SIZE-1 downto 2) tmpdatareg(0);
 
-- else
 
-- tmpdatareg(MAX_REG_SIZE-2 downto 0) := tmpdatareg(MAX_REG_SIZE-1 downto1);
 
 
-- end if;
 
 
---- tmpdatareg(counter) <= RxD; -- generates a large Mux
 
---- if counter = MAX_REG_SIZE-1 then
---- counter <= 0;
---- else
---- counter <= counter +1;
---- end if;
 
 
-- DataRegister <= tmpdatareg;
 
 
-- end if;
-- end process S2P_proc;
 
end ZeroDetect_beh;
/trunk/CODE/RX/CORE/Rxcont.vhd
82,8 → 82,8
FlagInit := '0';
initzero <= '0';
FrameStatusReg := (others => '0');
FrameError <= '0';
FlagCounter := 0;
FrameError <= '0';
FlagCounter := 0;
 
elsif Rxclk'event and Rxclk = '1' then -- rising clock edge
-------------------------------------------------------------------------------
139,7 → 139,7
if counter = 5 then
 
enable <= '0';
 
counter := 0;
FrameError <= '1';
 
else

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