URL
https://opencores.org/ocsvn/lwrisc/lwrisc/trunk
Subversion Repositories lwrisc
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- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/reg_file.v
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/trunk/clairisc_def.h
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/trunk/sim_rom.v
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/trunk/pc_stack.v
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/trunk/decoder.v
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/trunk/regs.v
File deleted
/trunk/memory.v
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/trunk/alu.v
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/trunk/test.v
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/trunk/E2V.c
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/trunk/alt_ram.v
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/trunk/Book1.xls
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trunk/Book1.xls
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Index: trunk/LWRISC8.v
===================================================================
--- trunk/LWRISC8.v (revision 4)
+++ trunk/LWRISC8.v (nonexistent)
@@ -1,340 +0,0 @@
-`define MUXA_W 0
-`define MUXA_BD 1
-`define MUXB_K 0
-`define MUXB_F 1
-
-`define BRC_NOP 0
-`define BRC_ZERO 1
-`define BRC_NZERO 2
-
-`define BG_ZERO 1
-`define BG_NZERO 2
-`define BG_IGN 0
-`define BG_NOP 0
-
-`define PC_NOP 0
-`define PC_BRC 1
-`define PC_GOTO 2
-`define PC_CALL 3
-`define PC_RET 4
-
-`define R1_LEN 1
-`define R2_LEN 2
-`define R3_LEN 3
-`define R4_LEN 4
-`define R5_LEN 5
-`define R8_LEN 8
-`define R12_LEN 12
-
-`define ALU_ADD 1
-`define ALU_SUB 2
-`define ALU_AND 3
-`define ALU_OR 4
-`define ALU_XOR 5
-`define ALU_COM 6
-`define ALU_ROR 7
-`define ALU_ROL 8
-`define ALU_SWAP 9
-`define ALU_BSF 10
-`define ALU_BCF 11
-`define ALU_ZERO 12
-`define ALU_DEC 13
-`define ALU_INC 14
-`define ALU_PB 15
-`define ALU_PA 16
-module ttoe(
- input [2:0] din,
- output reg [7:0] dout
- );
-
- always @ (*)
- case (din)
- 0:dout=1<<0;
- 1:dout=1<<1;
- 2:dout=1<<2;
- 3:dout=1<<3;
- 4:dout=1<<4;
- 5:dout=1<<5;
- 6:dout=1<<6;
- 7:dout=1<<7;
- endcase
-endmodule
-
-
-
-module alu_muxa(
- input ctl,
- output reg [7:0]alu_a,
- input [7:0]w,
- input [7:0]bd
- );
-
- always@(*)
- if (ctl==`MUXA_W)
- alu_a=w;
- else
- alu_a=bd;
-endmodule
-
-module alu_muxb(
- input ctl,
- output reg [7:0] alu_b,
- input [8:0] k,
- input [7:0] f
- );
-
- always@(*)
- if (ctl==`MUXB_K)
- alu_b=k[7:0];
- else alu_b=f;
-
-endmodule
-
-
-module w_reg(input [7:0]d,input clk,output reg [7:0] q,input w_wr_en) ;
-always @(posedge clk) if (w_wr_en) q<=d;
-endmodule
-
-module pc_gen(
-
- input [10:0]pc_i,
- output reg [10:0] pc_o,
- input [7:0] jmp_addr,
- input [10:0] stack_pc,
- input [4:0]ctl,
- input brc,
- input [7:0]status
-
- );
-
- always @ (*)
- case(ctl)
- `PC_NOP :pc_o = pc_i+1;
- `PC_BRC : if(brc)pc_o = {status[7:6],jmp_addr[7:0]}; //jmp_addr means K
- `PC_GOTO,
- `PC_CALL: pc_o = {status[7:6],jmp_addr[7:0]};
- `PC_RET: pc_o = stack_pc;
- default
- pc_o = pc_i+1;
- endcase
-endmodule
-
-
-module bg(
- input z ,
- input [1:0]ctl,
- output reg branch);
- always @(*)
- case (ctl)
- `BG_ZERO :branch = z;
- `BG_NZERO :branch = ~z;
- default branch = 0;
- endcase
- endmodule
-
-`if 0
-module decoder(
- input [11:0]inst,
- output reg [2:0]pc_ctl,
- output reg [1:0]stack_op,
- output reg alu_muxa,
- output reg alu_muxb,
- output reg [3:0]alu_op,
- output reg men_wr,
- output reg w_wr,
- output reg c_wr,
- output reg z_wr,
- output reg [1:0]bg_op
- );
- always @(inst) begin
- casex (inst) //synopsys parallel_case
- 12'b0000_0000_0000: //REPLACE ID = NOP
-
- 12'b0000_001X_XXXX: //REPLACE ID = MOVWF
-
- 12'b0000_0100_0000: //REPLACE ID = CLRW
-
- 12'b0000_011X_XXXX: //REPLACE ID = CLRF
-
- 12'b0000_100X_XXXX: //REPLACE ID = SUBWF_W
-
- 12'b0000_101X_XXXX: //REPLACE ID = SUBWF_F
-
- 12'b0000_110X_XXXX: //REPLACE ID = DECF_W
-
- 12'b0000_111X_XXXX: //REPLACE ID = DECF_F
-
- 12'b0001_000X_XXXX: //REPLACE ID = IORWF _W
-
- 12'b0001_001X_XXXX: //REPLACE ID = IORWF_F
-
- 12'b0001_010X_XXXX: //REPLACE ID = ANDWF_W
-
- 12'b0001_011X_XXXX: //REPLACE ID = ANDWF_F
-
- 12'b0001_100X_XXXX: //REPLACE ID = XORWF_W
-
- 12'b0001_101X_XXXX: //REPLACE ID = XORWF_F
-
- 12'b0001_110X_XXXX: //REPLACE ID = ADDWF_W
-
- 12'b0001_111X_XXXX: //REPLACE ID = ADDWF_F
-
- 12'b0010_000X_XXXX: //REPLACE ID = MOVF_W
-
- 12'b0010_001X_XXXX: //REPLACE ID = MOVF_F
-
- 12'b0010_010X_XXXX: //REPLACE ID = COMF_W
-
- 12'b0010_011X_XXXX: //REPLACE ID = COMF_F
-
- 12'b0010_100X_XXXX: //REPLACE ID = INCF_W
-
- 12'b0010_101X_XXXX: //REPLACE ID = INCF_F
-
- 12'b0010_110X_XXXX: //REPLACE ID = DECFSZ_W
-
- 12'b0010_111X_XXXX: //REPLACE ID = DECFSZ_F
-
- 12'b0011_000X_XXXX: //REPLACE ID = RRF_W
-
- 12'b0011_001X_XXXX: //REPLACE ID = RRF_F
-
- 12'b0011_010X_XXXX: //REPLACE ID = RLF_W
-
- 12'b0011_011X_XXXX: //REPLACE ID = RLF_F
-
- 12'b0011_100X_XXXX: //REPLACE ID = SWAPF_W
-
- 12'b0011_101X_XXXX: //REPLACE ID = SWAPF_F
-
- 12'b0011_110X_XXXX: //REPLACE ID = INCFSZ_W
-
- 12'b0011_111X_XXXX: //REPLACE ID = INCFSZ_F
-
- 12'b0100_XXXX_XXXX: //REPLACE ID = BCF
-
- 12'b0101_XXXX_XXXX: //REPLACE ID = BSF
-
- 12'b0110_XXXX_XXXX: //REPLACE ID = BTFSC
-
- 12'b0111_XXXX_XXXX: //REPLACE ID = BTFSS
-
- 12'b0000_0000_0010: //REPLACE ID = OPTION
-
- 12'b0000_0000_0011: //REPLACE ID = SLEEP
-
- 12'b0000_0000_0100: //REPLACE ID = CLRWDT
-
- 12'b0000_0000_0101: //REPLACE ID = TRIS 5
-
- 12'b0000_0000_0110: //REPLACE ID = TRIS 6
-
- 12'b0000_0000_0111: //REPLACE ID = TRIS 7
-
- 12'b1000_XXXX_XXXX: //REPLACE ID = RETLW
-
- 12'b1001_XXXX_XXXX: //REPLACE ID = CALL
-
- 12'b101X_XXXX_XXXX: //REPLACE ID = GOTO
-
- 12'b1100_XXXX_XXXX: //REPLACE ID = MOVLW
-
- 12'b1101_XXXX_XXXX: //REPLACE ID = IORLW
-
- 12'b1110_XXXX_XXXX: //REPLACE ID = ANDLW
-
- 12'b1111_XXXX_XXXX: //REPLACE ID = XORLW
-
- default:
-
- endcase
- end
-endmodule
-`endif
-
-module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
-module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule
-module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule
-module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
-module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
-module r8_reg_clr_cls(input[`R8_LEN-1:0] r8_i,output reg[`R8_LEN-1:0] r8_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r8_o<=0;else if(cls)r8_o<=r8_o;else r8_o<=r8_i;endmodule
-module r12_reg_clr_cls(input[`R12_LEN-1:0] r12_i,output reg[`R12_LEN-1:0] r12_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r12_o<=0;else if(cls)r12_o<=r12_o;else r12_o<=r12_i;endmodule
-
-`define PUSH 2'B01
-`define POP 2'B10
-`define NOP 2'B00
-
-// A Basic Synchrounous FIFO (4 entries deep)
-module sfifo4x11(clk, ctl,din, dout);
- input clk;
- input [1:0] ctl;
- input [10:0] din;
- output [10:0] dout;
- reg [10:0] stack1, stack2, stack3, stack4;
- assign dout = stack1;
- always @(posedge clk)
- begin
- case (ctl)
- `PUSH :// PUSH stack
- begin
- stack4 <= stack3;
- stack3 <= stack2;
- stack2 <= stack1;
- stack1 <= din;
- end
- `POP :// POP stack
- begin
- stack1 <= stack2;
- stack2 <= stack3;
- stack3 <= stack4;
- end
- // default ://do nothing
- endcase
- end
-endmodule
-
-
-
-module alu(op,a,b,y,cin,cout,zout);
- input [4:0] op; // ALU Operation
- input [7:0] a; // 8-bit Input a
- input [7:0] b; // 8-bit Input b
- output [7:0] y; // 8-bit Output
- input cin;
- output cout;
- output zout;
- // Reg declarations for outputs
- reg [7:0] y;
- // Internal declarations
- reg addercout; // Carry out straight from the adder itself.
- always @(*) begin
- case (op) // synsys parallel_case
- `ALU_ADD: {addercout, y} = a + b;
- `ALU_SUB: {addercout, y} = b - a; // Carry out is really "borrow"
- `ALU_AND: {addercout, y} = {1'b0, a & b};
- `ALU_ROR: {addercout, y} = {b[0], cin, b[7:1]};
- `ALU_ROL: {addercout, y} = {b[7], b[6:0], cin};
- `ALU_OR: {addercout, y} = {1'b0, a | b};
- `ALU_XOR: {addercout, y} = {1'b0, a ^ b};
- `ALU_COM: {addercout, y} = {1'b0, ~b};
- `ALU_SWAP: {addercout, y} = {1'b0, b[3:0], b[7:4]};
- /*below added by liwei*/
- `ALU_BTFSC {addercout, y} = {1'b0, a & b };
- `ALU_BTFSS {addercout, y} = {1'b0, ~a | b };
- `ALU_DEC: y = b - 1;
- `ALU_INC: y = 1 + b;
- `ALU_PA : {addercout, y} = {1'b0, a};
- `ALU_PB : {addercout, y} = {1'b0, b};
- `ALU_BSF : {addercout, y} = {1b'0,a | b};
- `ALU_BCF : {addercout, y} = {1'b0,~a & b};
- `ALU_ZERO: {addercout, y} = {1'b0, 8'h00};
- default: {addercout, y} = {1'b0, 8'h00};
- endcase
- end
-
- assign zout = (y == 8'h00);
- assign cout = (op == `ALUOP_SUB) ? ~addercout : addercout;
-
-endmodule
-
Index: trunk/risc_core.bde
===================================================================
--- trunk/risc_core.bde (revision 4)
+++ trunk/risc_core.bde (nonexistent)
@@ -1,9095 +0,0 @@
-SCHM0103
-
-HEADER
-{
- FREEID 15592
- VARIABLES
- {
- #BLOCKTABLE_FILE="#table.bde"
- #BLOCKTABLE_INCLUDED="1"
- #LANGUAGE="VERILOG"
- #MODULE="ClaiRISC_core"
- AUTHOR="΢ÈíÓû§"
- COMPANY="΢ÈíÖйú"
- CREATIONDATE="2008-2-25"
- TITLE="ClaiRISC"
- }
- SYMBOL "#default" "alu" "alu"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140880898"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,240,200)
- FREEID 17
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,220,200)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,93,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (169,30,215,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,93,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (147,70,215,94)
- ALIGN 6
- MARGINS (1,1)
- PARENT 8
- }
- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,60,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 10
- }
- TEXT 13, 0, 0
- {
- TEXT "$#NAME"
- RECT (169,110,215,134)
- ALIGN 6
- MARGINS (1,1)
- PARENT 12
- }
- TEXT 15, 0, 0
- {
- TEXT "$#NAME"
- RECT (20,148,99,172)
- ALIGN 4
- MARGINS (1,1)
- PARENT 14
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="a(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (240,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cout"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="b(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (240,80)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="y(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cin"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 12, 0, 0
- {
- COORD (240,120)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="zout"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 14, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="op(4:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "alu_muxa" "alu_muxa"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1203406438"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,320,160)
- FREEID 11
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,300,160)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,104,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (183,30,295,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,60,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,93,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="bd(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (320,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="alu_a(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ctl"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="w(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "alu_muxb" "alu_muxb"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140881510"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,320,160)
- FREEID 11
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,300,160)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (183,30,295,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,93,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,93,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ctl"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (320,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="alu_b(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="f(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="k(8:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "bg" "bg"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140877883"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
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- FREEID 8
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
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- AREA (20,0,180,120)
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- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,115,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
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- TEXT 5, 0, 0
- {
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- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,38,94)
- ALIGN 4
- MARGINS (1,1)
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- PIN 2, 0, 0
- {
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- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ctl(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (200,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="branch"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="z"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "mem_man" "mem_man"
- {
- HEADER
- {
- VARIABLES
- {
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- #LANGUAGE="VERILOG"
- #MODIFIED="1203406652"
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- {
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- {
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- {
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- AREA (20,0,420,480)
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- TEXT 3, 0, 0
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- TEXT "$#NAME"
- RECT (25,30,71,54)
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- TEXT 5, 0, 0
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- TEXT 7, 0, 0
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- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (391,70,415,94)
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- MARGINS (1,1)
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- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
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- TEXT 13, 0, 0
- {
- TEXT "$#NAME"
- RECT (314,110,415,134)
- ALIGN 6
- MARGINS (1,1)
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- TEXT 15, 0, 0
- {
- TEXT "$#NAME"
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- TEXT 17, 0, 0
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- TEXT 19, 0, 0
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- TEXT 21, 0, 0
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- TEXT 23, 0, 0
- {
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- MARGINS (1,1)
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- TEXT 25, 0, 0
- {
- TEXT "$#NAME"
- RECT (237,230,415,254)
- ALIGN 6
- MARGINS (1,1)
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- TEXT 27, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,270,60,294)
- ALIGN 4
- MARGINS (1,1)
- PARENT 26
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- TEXT 29, 0, 0
- {
- TEXT "$#NAME"
- RECT (292,270,415,294)
- ALIGN 6
- MARGINS (1,1)
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- TEXT 31, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,310,159,334)
- ALIGN 4
- MARGINS (1,1)
- PARENT 30
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- TEXT 33, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,350,82,374)
- ALIGN 4
- MARGINS (1,1)
- PARENT 32
- }
- TEXT 35, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,390,71,414)
- ALIGN 4
- MARGINS (1,1)
- PARENT 34
- }
- TEXT 37, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,430,49,454)
- ALIGN 4
- MARGINS (1,1)
- PARENT 36
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="c_wr"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (440,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="bank(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ci"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (440,80)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="co"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 12, 0, 0
- {
- COORD (440,120)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="dout(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 14, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="din(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 16, 0, 0
- {
- COORD (440,160)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="exp_dout(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 18, 0, 0
- {
- COORD (0,200)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="exp_din(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 20, 0, 0
- {
- COORD (440,200)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="exp_rd_addr(6:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 22, 0, 0
- {
- COORD (0,240)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="rd_addr(6:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 24, 0, 0
- {
- COORD (440,240)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="exp_wr_addr(6:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 26, 0, 0
- {
- COORD (0,280)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="rst"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 28, 0, 0
- {
- COORD (440,280)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="status(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 30, 0, 0
- {
- COORD (0,320)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="wr_addr(6:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 32, 0, 0
- {
- COORD (0,360)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="wr_en"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 34, 0, 0
- {
- COORD (0,400)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="z_wr"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 36, 0, 0
- {
- COORD (0,440)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="zi"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "pc_gen" "pc_gen"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1204259715"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,-80,280,280)
- FREEID 23
- }
-
- BODY
- {
- RECT 1, -1, 0
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- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,-80,260,280)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (143,30,255,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (20,68,110,92)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (20,108,121,132)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,150,137,174)
- ALIGN 4
- MARGINS (1,1)
- PARENT 10
- }
- TEXT 13, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,190,181,214)
- ALIGN 4
- MARGINS (1,1)
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- TEXT 15, 0, 0
- {
- TEXT "$#NAME"
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- TEXT 18, 0, 0
- {
- TEXT "$#NAME"
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- TEXT 21, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,-50,60,-26)
- ALIGN 4
- MARGINS (1,1)
- PARENT 20
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="brc"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (280,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="pc_o(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ctl(2:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ins(11:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="pc_i(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 12, 0, 0
- {
- COORD (0,200)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="stack_pc(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 14, 0, 0
- {
- COORD (0,240)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="status(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 17, 0, 0
- {
- COORD (0,0)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #MODIFIED=""
- #NAME="ek(8:0)"
- #NUMBER="0"
- #SIDE="left"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 20, 0, 0
- {
- COORD (0,-40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #MODIFIED=""
- #NAME="rst"
- #NUMBER="0"
- #SIDE="left"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "sfifo4x11" "sfifo4x11"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1203406747"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,260,160)
- FREEID 11
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,240,160)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (123,30,235,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,115,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,126,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (260,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="dout(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ctl(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="din(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "w_reg" "w_reg"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1203406755"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,240,160)
- FREEID 11
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,220,160)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (147,30,215,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,93,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,104,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (240,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="q(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="d(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="w_wr_en"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "decoder" "decoder"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140882181"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,320,440)
- FREEID 25
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,300,440)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,137,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (205,30,295,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (205,70,295,94)
- ALIGN 6
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (172,110,295,134)
- ALIGN 6
- MARGINS (1,1)
- PARENT 8
- }
- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (183,150,295,174)
- ALIGN 6
- MARGINS (1,1)
- PARENT 10
- }
- TEXT 13, 0, 0
- {
- TEXT "$#NAME"
- RECT (249,190,295,214)
- ALIGN 6
- MARGINS (1,1)
- PARENT 12
- }
- TEXT 15, 0, 0
- {
- TEXT "$#NAME"
- RECT (227,230,295,254)
- ALIGN 6
- MARGINS (1,1)
- PARENT 14
- }
- TEXT 17, 0, 0
- {
- TEXT "$#NAME"
- RECT (172,270,295,294)
- ALIGN 6
- MARGINS (1,1)
- PARENT 16
- }
- TEXT 19, 0, 0
- {
- TEXT "$#NAME"
- RECT (150,310,295,334)
- ALIGN 6
- MARGINS (1,1)
- PARENT 18
- }
- TEXT 21, 0, 0
- {
- TEXT "$#NAME"
- RECT (249,350,295,374)
- ALIGN 6
- MARGINS (1,1)
- PARENT 20
- }
- TEXT 23, 0, 0
- {
- TEXT "$#NAME"
- RECT (249,390,295,414)
- ALIGN 6
- MARGINS (1,1)
- PARENT 22
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="inst(11:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (320,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="alu_muxa"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (320,80)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="alu_muxb"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (320,120)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="alu_op(4:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (320,160)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="bg_op(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 12, 0, 0
- {
- COORD (320,200)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="c_wr"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 14, 0, 0
- {
- COORD (320,240)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="men_wr"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 16, 0, 0
- {
- COORD (320,280)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="pc_ctl(2:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 18, 0, 0
- {
- COORD (320,320)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="stack_op(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 20, 0, 0
- {
- COORD (320,360)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="w_wr"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 22, 0, 0
- {
- COORD (320,400)
- VARIABLES
- {
- #DIRECTION="OUT"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="z_wr"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "ins2bd" "ins2bd"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140882215"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,200,80)
- FREEID 6
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,180,80)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,126,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (96,30,175,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ins(11:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (200,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="bd(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "r8_reg_clr_cls" "r8_reg_clr_cls"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140882281"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,180,200)
- FREEID 12
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,160,200)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (54,30,155,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,60,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,60,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,150,126,174)
- ALIGN 4
- MARGINS (1,1)
- PARENT 10
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (180,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r8_o(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clr"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cls"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r8_i(7:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "ek_reg_clr_cls" "ek_reg_clr_cls"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1140882775"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,180,200)
- FREEID 12
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,160,200)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (54,30,155,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,60,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,60,134)
- ALIGN 4
- MARGINS (1,1)
- PARENT 8
- }
- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,150,126,174)
- ALIGN 4
- MARGINS (1,1)
- PARENT 10
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (180,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r9_o(8:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clr"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cls"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="ins(11:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "mem_addr" "mem_addr"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1204085384"
- }
- }
- PAGE ""
- {
- PAGEHEADER
- {
- RECT (0,0,300,120)
- FREEID 9
- }
-
- BODY
- {
- RECT 1, -1, 0
- {
- VARIABLES
- {
- #OUTLINE_FILLING="1"
- }
- AREA (20,0,280,120)
- }
- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,126,54)
- ALIGN 4
- MARGINS (1,1)
- PARENT 2
- }
- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (119,30,275,54)
- ALIGN 6
- MARGINS (1,1)
- PARENT 4
- }
- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,70,126,94)
- ALIGN 4
- MARGINS (1,1)
- PARENT 6
- }
- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="addr(4:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (300,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="file_addr(6:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="bank(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "ins2wb_addr" "ins2wb_addr"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
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- TEXT 3, 0, 0
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- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
- RECT (101,30,235,54)
- ALIGN 6
- MARGINS (1,1)
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- PIN 2, 0, 0
- {
- COORD (-120,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
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- #VERILOG_TYPE="wire"
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- LINE 2, 0, 0
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- }
- PIN 4, 0, 0
- {
- COORD (260,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
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- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
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- SYMBOL "#default" "r5_reg_clr_cls" "r5_reg_clr_cls"
- {
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- VARIABLES
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- #LANGUAGE="VERILOG"
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- TEXT "$#NAME"
- RECT (25,150,126,174)
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- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
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- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
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- }
- PIN 4, 0, 0
- {
- COORD (180,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
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- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
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- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clr"
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- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cls"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r5_i(4:0)"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
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- }
- }
- }
- }
- SYMBOL "#default" "pram" "pram"
- {
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- #LANGUAGE="VERILOG"
- #MODIFIED="1140885812"
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- PAGE ""
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- AREA (20,0,200,240)
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- TEXT 3, 0, 0
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- TEXT "$#NAME"
- RECT (25,30,60,54)
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- TEXT 5, 0, 0
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- TEXT "$#NAME"
- RECT (83,30,195,54)
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- MARGINS (1,1)
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- TEXT 7, 0, 0
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- TEXT "$#NAME"
- RECT (25,70,126,94)
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- TEXT 9, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,110,170,134)
- ALIGN 4
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- TEXT 11, 0, 0
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- TEXT "$#NAME"
- RECT (25,150,49,174)
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- TEXT 13, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,190,170,214)
- ALIGN 4
- MARGINS (1,1)
- PARENT 12
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- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
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- }
- PIN 4, 0, 0
- {
- COORD (220,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="dout(11:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="din(11:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="rd_addr(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="we"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 12, 0, 0
- {
- COORD (0,200)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="wr_addr(10:0)"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "r1_reg_clr_cls" "r1_reg_clr_cls"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1203988930"
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- }
- PAGE ""
- {
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- {
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-
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- TEXT 3, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,30,60,54)
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- MARGINS (1,1)
- PARENT 2
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- TEXT 5, 0, 0
- {
- TEXT "$#NAME"
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- ALIGN 6
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- TEXT 7, 0, 0
- {
- TEXT "$#NAME"
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- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,150,126,174)
- ALIGN 4
- MARGINS (1,1)
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- PIN 2, 0, 0
- {
- COORD (0,40)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clk"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (180,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r1_o(0:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
- }
- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clr"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cls"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r1_i(0:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "r2_reg_clr_cls" "r2_reg_clr_cls"
- {
- HEADER
- {
- VARIABLES
- {
- #DESCRIPTION=""
- #LANGUAGE="VERILOG"
- #MODIFIED="1203989499"
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- }
- PAGE ""
- {
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- {
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- FREEID 12
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- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,150,126,174)
- ALIGN 4
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- PIN 2, 0, 0
- {
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- VARIABLES
- {
- #DIRECTION="IN"
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- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (180,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r2_o(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="reg"
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- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clr"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
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- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cls"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r2_i(1:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
- SYMBOL "#default" "r11_reg_clr_cls" "r11_reg_clr_cls"
- {
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- {
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- {
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- #LANGUAGE="VERILOG"
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- TEXT 11, 0, 0
- {
- TEXT "$#NAME"
- RECT (25,150,148,174)
- ALIGN 4
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- {
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- VARIABLES
- {
- #DIRECTION="IN"
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- #MDA_RECORD_TOKEN="OTHER"
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- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 4, 0, 0
- {
- COORD (200,40)
- VARIABLES
- {
- #DIRECTION="OUT"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
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- LINE 2, 0, 0
- {
- POINTS ( (-20,0), (0,0) )
- }
- }
- PIN 6, 0, 0
- {
- COORD (0,80)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="clr"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 8, 0, 0
- {
- COORD (0,120)
- VARIABLES
- {
- #DIRECTION="IN"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="cls"
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- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- PIN 10, 0, 0
- {
- COORD (0,160)
- VARIABLES
- {
- #DIRECTION="IN"
- #DOWNTO="1"
- #LENGTH="20"
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="r11_i(10:0)"
- #NUMBER="0"
- #VERILOG_TYPE="wire"
- }
- LINE 2, 0, 0
- {
- POINTS ( (0,0), (20,0) )
- }
- }
- }
- }
- }
-}
-
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- COORD (1660,420)
- }
- VTX 9996, 0, 0
- {
- COORD (1600,1660)
- }
- VTX 9997, 0, 0
- {
- COORD (1340,1680)
- }
- VTX 9998, 0, 0
- {
- COORD (1600,1380)
- }
- VTX 9999, 0, 0
- {
- COORD (1160,1680)
- }
- VTX 10004, 0, 0
- {
- COORD (960,1520)
- }
- VTX 10005, 0, 0
- {
- COORD (1400,2300)
- }
- VTX 10006, 0, 0
- {
- COORD (760,860)
- }
- VTX 10007, 0, 0
- {
- COORD (680,860)
- }
- VTX 10008, 0, 0
- {
- COORD (1400,2180)
- }
- VTX 10009, 0, 0
- {
- COORD (640,1840)
- }
- VTX 10010, 0, 0
- {
- COORD (960,1720)
- }
- VTX 10011, 0, 0
- {
- COORD (1160,1800)
- }
- VTX 10014, 0, 0
- {
- COORD (1020,1840)
- }
- VTX 10015, 0, 0
- {
- COORD (1600,1620)
- }
- VTX 10016, 0, 0
- {
- COORD (980,2020)
- }
- VTX 10017, 0, 0
- {
- COORD (960,1560)
- }
- VTX 10018, 0, 0
- {
- COORD (800,2140)
- }
- VTX 10019, 0, 0
- {
- COORD (1160,1920)
- }
- VTX 10020, 0, 0
- {
- COORD (800,2020)
- }
- VTX 10022, 0, 0
- {
- COORD (1980,940)
- }
- VTX 10023, 0, 0
- {
- COORD (1940,1100)
- }
- VTX 10029, 0, 0
- {
- COORD (440,920)
- }
- VTX 10032, 0, 0
- {
- COORD (440,1040)
- }
- VTX 10033, 0, 0
- {
- COORD (440,1000)
- }
- VTX 10036, 0, 0
- {
- COORD (1120,2220)
- }
- VTX 10037, 0, 0
- {
- COORD (1120,2240)
- }
- VTX 10038, 0, 0
- {
- COORD (1160,1760)
- }
- VTX 10039, 0, 0
- {
- COORD (360,1540)
- }
- WIRE 10040, 0, 0
- {
- NET 133
- VTX 9854, 9855
- }
- VTX 10041, 0, 0
- {
- COORD (1440,1100)
- }
- BUS 10042, 0, 0
- {
- NET 138
- VTX 9856, 10041
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10043, 0, 0
- {
- COORD (1440,880)
- }
- BUS 10044, 0, 0
- {
- NET 138
- VTX 10041, 10043
- }
- BUS 10045, 0, 0
- {
- NET 138
- VTX 10043, 9857
- }
- VTX 10046, 0, 0
- {
- COORD (1900,1160)
- }
- WIRE 10047, 0, 0
- {
- NET 133
- VTX 9854, 10046
- }
- VTX 10048, 0, 0
- {
- COORD (1480,1160)
- }
- WIRE 10049, 0, 0
- {
- NET 133
- VTX 10046, 10048
- }
- VTX 10050, 0, 0
- {
- COORD (1480,1700)
- }
- WIRE 10051, 0, 0
- {
- NET 133
- VTX 10048, 10050
- }
- WIRE 10052, 0, 0
- {
- NET 133
- VTX 10050, 9858
- }
- VTX 10053, 0, 0
- {
- COORD (2060,1340)
- }
- WIRE 10054, 0, 0
- {
- NET 230
- VTX 9859, 10053
- }
- VTX 10055, 0, 0
- {
- COORD (2060,1100)
- }
- WIRE 10056, 0, 0
- {
- NET 230
- VTX 10053, 10055
- }
- VTX 10057, 0, 0
- {
- COORD (1580,1100)
- }
- WIRE 10058, 0, 0
- {
- NET 230
- VTX 10055, 10057
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10059, 0, 0
- {
- COORD (1580,920)
- }
- WIRE 10060, 0, 0
- {
- NET 230
- VTX 10057, 10059
- }
- WIRE 10061, 0, 0
- {
- NET 230
- VTX 10059, 9860
- }
- VTX 10062, 0, 0
- {
- COORD (1880,840)
- }
- WIRE 10063, 0, 0
- {
- NET 247
- VTX 9861, 10062
- }
- VTX 10064, 0, 0
- {
- COORD (1880,1240)
- }
- WIRE 10065, 0, 0
- {
- NET 247
- VTX 10062, 10064
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10066, 0, 0
- {
- COORD (1580,1240)
- }
- WIRE 10067, 0, 0
- {
- NET 247
- VTX 10064, 10066
- }
- VTX 10068, 0, 0
- {
- COORD (1580,1340)
- }
- WIRE 10069, 0, 0
- {
- NET 247
- VTX 10066, 10068
- }
- WIRE 10070, 0, 0
- {
- NET 247
- VTX 10068, 9862
- }
- VTX 10071, 0, 0
- {
- COORD (2080,1380)
- }
- BUS 10072, 0, 0
- {
- NET 12776
- VTX 9863, 10071
- }
- VTX 10073, 0, 0
- {
- COORD (2080,1220)
- }
- BUS 10074, 0, 0
- {
- NET 12776
- VTX 10071, 10073
- }
- VTX 10075, 0, 0
- {
- COORD (1340,1220)
- }
- BUS 10076, 0, 0
- {
- NET 12776
- VTX 10073, 10075
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10077, 0, 0
- {
- COORD (1340,1240)
- }
- BUS 10078, 0, 0
- {
- NET 12776
- VTX 10075, 10077
- }
- VTX 10079, 0, 0
- {
- COORD (1010,1240)
- }
- BUS 10080, 0, 0
- {
- NET 12776
- VTX 10077, 10079
- }
- VTX 10081, 0, 0
- {
- COORD (1010,1140)
- }
- BUS 10082, 0, 0
- {
- NET 12776
- VTX 10079, 10081
- }
- BUS 10083, 0, 0
- {
- NET 12776
- VTX 10081, 9864
- }
- VTX 10084, 0, 0
- {
- COORD (470,580)
- }
- BUS 10085, 0, 0
- {
- NET 1936
- VTX 9865, 10084
- }
- VTX 10086, 0, 0
- {
- COORD (470,660)
- }
- BUS 10087, 0, 0
- {
- NET 1936
- VTX 10084, 10086
- }
- BUS 10088, 0, 0
- {
- NET 1936
- VTX 10086, 12686
- }
- VTX 10094, 0, 0
- {
- COORD (1920,880)
- }
- BUS 10095, 0, 0
- {
- NET 872
- VTX 9868, 10094
- }
- VTX 10096, 0, 0
- {
- COORD (1920,1200)
- }
- BUS 10097, 0, 0
- {
- NET 872
- VTX 10094, 10096
- }
- VTX 10098, 0, 0
- {
- COORD (1560,1200)
- }
- BUS 10099, 0, 0
- {
- NET 872
- VTX 10096, 10098
- }
- BUS 10100, 0, 0
- {
- NET 872
- VTX 10098, 9869
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10101, 0, 0
- {
- COORD (1560,1420)
- }
- BUS 10102, 0, 0
- {
- NET 872
- VTX 9869, 10101
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 10103, 0, 0
- {
- NET 872
- VTX 10101, 9870
- }
- VTX 10111, 0, 0
- {
- COORD (1400,1300)
- }
- BUS 10112, 0, 0
- {
- NET 872
- VTX 9869, 10111
- }
- VTX 10113, 0, 0
- {
- COORD (1400,1000)
- }
- BUS 10114, 0, 0
- {
- NET 872
- VTX 10111, 10113
- }
- VTX 10115, 0, 0
- {
- COORD (750,1000)
- }
- BUS 10116, 0, 0
- {
- NET 872
- VTX 10113, 10115
- }
- VTX 10117, 0, 0
- {
- COORD (750,900)
- }
- BUS 10118, 0, 0
- {
- NET 872
- VTX 10115, 10117
- }
- BUS 10119, 0, 0
- {
- NET 872
- VTX 10117, 9873
- }
- VTX 10120, 0, 0
- {
- COORD (1020,1680)
- }
- WIRE 10121, 0, 0
- {
- NET 1106
- VTX 9874, 10120
- }
- VTX 10122, 0, 0
- {
- COORD (1020,1260)
- }
- WIRE 10123, 0, 0
- {
- NET 1106
- VTX 10120, 10122
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10124, 0, 0
- {
- COORD (700,1260)
- }
- WIRE 10125, 0, 0
- {
- NET 1106
- VTX 10122, 10124
- }
- VTX 10126, 0, 0
- {
- COORD (700,1100)
- }
- WIRE 10127, 0, 0
- {
- NET 1106
- VTX 10124, 10126
- }
- VTX 10128, 0, 0
- {
- COORD (740,1100)
- }
- WIRE 10129, 0, 0
- {
- NET 1106
- VTX 10126, 10128
- }
- VTX 10130, 0, 0
- {
- COORD (740,940)
- }
- WIRE 10131, 0, 0
- {
- NET 1106
- VTX 10128, 10130
- }
- WIRE 10132, 0, 0
- {
- NET 1106
- VTX 10130, 9875
- }
- BUS 10137, 0, 0
- {
- NET 1168
- VTX 9879, 9871
- }
- VTX 10138, 0, 0
- {
- COORD (380,1360)
- }
- BUS 10139, 0, 0
- {
- NET 1168
- VTX 9880, 10138
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 10140, 0, 0
- {
- NET 1168
- VTX 10138, 9881
- }
- BUS 10141, 0, 0
- {
- NET 1168
- VTX 9881, 9871
- }
- BUS 10142, 0, 0
- {
- NET 1168
- VTX 9882, 9881
- }
- BUS 10143, 0, 0
- {
- NET 1168
- VTX 9883, 9880
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 10144, 0, 0
- {
- NET 1168
- VTX 9880, 9884
- }
- VTX 10145, 0, 0
- {
- COORD (1460,1920)
- }
- BUS 10146, 0, 0
- {
- NET 1845
- VTX 9885, 10145
- }
- VTX 10147, 0, 0
- {
- COORD (1460,1880)
- }
- BUS 10148, 0, 0
- {
- NET 1845
- VTX 10145, 10147
- }
- BUS 10149, 0, 0
- {
- NET 1845
- VTX 10147, 9886
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10150, 0, 0
- {
- COORD (1640,1760)
- }
- BUS 10151, 0, 0
- {
- NET 1858
- VTX 9887, 10150
- }
- VTX 10152, 0, 0
- {
- COORD (2120,1760)
- }
- BUS 10153, 0, 0
- {
- NET 1858
- VTX 10150, 10152
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10154, 0, 0
- {
- COORD (2120,1300)
- }
- BUS 10155, 0, 0
- {
- NET 1858
- VTX 10152, 10154
- }
- BUS 10156, 0, 0
- {
- NET 1858
- VTX 10154, 9888
- }
- VTX 10169, 0, 0
- {
- COORD (1040,1640)
- }
- BUS 10170, 0, 0
- {
- NET 1460
- VTX 9897, 10169
- }
- VTX 10171, 0, 0
- {
- COORD (1040,1300)
- }
- BUS 10172, 0, 0
- {
- NET 1460
- VTX 10169, 10171
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10173, 0, 0
- {
- COORD (680,1300)
- }
- BUS 10174, 0, 0
- {
- NET 1460
- VTX 10171, 10173
- }
- VTX 10175, 0, 0
- {
- COORD (680,1160)
- }
- BUS 10176, 0, 0
- {
- NET 1460
- VTX 10173, 10175
- }
- VTX 10177, 0, 0
- {
- COORD (340,1160)
- }
- BUS 10178, 0, 0
- {
- NET 1460
- VTX 10175, 10177
- }
- VTX 10179, 0, 0
- {
- COORD (340,540)
- }
- BUS 10180, 0, 0
- {
- NET 1460
- VTX 10177, 10179
- }
- BUS 10181, 0, 0
- {
- NET 1460
- VTX 10179, 9898
- }
- VTX 10212, 0, 0
- {
- COORD (640,1240)
- }
- BUS 10213, 0, 0
- {
- NET 1443
- VTX 9907, 10212
- }
- VTX 10214, 0, 0
- {
- COORD (640,1300)
- }
- BUS 10215, 0, 0
- {
- NET 1443
- VTX 10212, 10214
- }
- VTX 10216, 0, 0
- {
- COORD (300,1300)
- }
- BUS 10217, 0, 0
- {
- NET 1443
- VTX 10214, 10216
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10218, 0, 0
- {
- COORD (300,1580)
- }
- BUS 10219, 0, 0
- {
- NET 1443
- VTX 10216, 10218
- }
- BUS 10220, 0, 0
- {
- NET 1443
- VTX 10218, 9908
- }
- BUS 10221, 0, 0
- {
- NET 1168
- VTX 9884, 9909
- }
- VTX 10222, 0, 0
- {
- COORD (280,1920)
- }
- BUS 10223, 0, 0
- {
- NET 1935
- VTX 9906, 10222
- }
- BUS 10224, 0, 0
- {
- NET 1935
- VTX 10222, 9910
- }
- WIRE 10225, 0, 0
- {
- NET 4576
- VTX 9911, 9912
- }
- WIRE 10226, 0, 0
- {
- NET 4576
- VTX 9913, 9914
- }
- VTX 10227, 0, 0
- {
- COORD (200,1840)
- }
- WIRE 10228, 0, 0
- {
- NET 4576
- VTX 10227, 9915
- }
- WIRE 10229, 0, 0
- {
- NET 4576
- VTX 10227, 9916
- }
- WIRE 10230, 0, 0
- {
- NET 4576
- VTX 9916, 9914
- }
- VTX 10231, 0, 0
- {
- COORD (620,1920)
- }
- WIRE 10232, 0, 0
- {
- NET 4576
- VTX 9917, 10231
- }
- VTX 10233, 0, 0
- {
- COORD (620,1660)
- }
- WIRE 10234, 0, 0
- {
- NET 4576
- VTX 10231, 10233
- }
- WIRE 10235, 0, 0
- {
- NET 4576
- VTX 10233, 9916
- }
- WIRE 10236, 0, 0
- {
- NET 4576
- VTX 9918, 9919
- }
- WIRE 10237, 0, 0
- {
- NET 4576
- VTX 9919, 9920
- }
- WIRE 10238, 0, 0
- {
- NET 4576
- VTX 9920, 9912
- }
- WIRE 10239, 0, 0
- {
- NET 4576
- VTX 9914, 9921
- }
- WIRE 10240, 0, 0
- {
- NET 4576
- VTX 9921, 9918
- }
- VTX 10241, 0, 0
- {
- COORD (1060,1380)
- }
- WIRE 10242, 0, 0
- {
- NET 4576
- VTX 9922, 10241
- }
- VTX 10243, 0, 0
- {
- COORD (1060,1280)
- }
- WIRE 10244, 0, 0
- {
- NET 4576
- VTX 10241, 10243
- }
- VTX 10245, 0, 0
- {
- COORD (620,1280)
- }
- WIRE 10246, 0, 0
- {
- NET 4576
- VTX 10243, 10245
- }
- VTX 10247, 0, 0
- {
- COORD (620,1340)
- }
- WIRE 10248, 0, 0
- {
- NET 4576
- VTX 10245, 10247
- }
- WIRE 10249, 0, 0
- {
- NET 4576
- VTX 10247, 9921
- }
- VTX 10250, 0, 0
- {
- COORD (750,1060)
- }
- WIRE 10251, 0, 0
- {
- NET 4576
- VTX 9923, 10250
- }
- VTX 10252, 0, 0
- {
- COORD (750,1080)
- }
- WIRE 10253, 0, 0
- {
- NET 4576
- VTX 10250, 10252
- }
- WIRE 10254, 0, 0
- {
- NET 4576
- VTX 10252, 9918
- }
- WIRE 10255, 0, 0
- {
- NET 4576
- VTX 9912, 9924
- }
- VTX 10288, 0, 0
- {
- COORD (140,1500)
- }
- WIRE 10289, 0, 0
- {
- NET 12889
- VTX 9936, 10288
- }
- WIRE 10290, 0, 0
- {
- NET 12889
- VTX 10288, 9937
- }
- WIRE 10291, 0, 0
- {
- NET 12889
- VTX 9936, 9938
- }
- WIRE 10297, 0, 0
- {
- NET 12889
- VTX 9940, 9941
- }
- WIRE 10298, 0, 0
- {
- NET 12889
- VTX 9941, 9936
- }
- VTX 10299, 0, 0
- {
- COORD (560,1960)
- }
- WIRE 10300, 0, 0
- {
- NET 12889
- VTX 9942, 10299
- }
- VTX 10301, 0, 0
- {
- COORD (560,1640)
- }
- WIRE 10302, 0, 0
- {
- NET 12889
- VTX 10299, 10301
- }
- VTX 10303, 0, 0
- {
- COORD (320,1640)
- }
- WIRE 10304, 0, 0
- {
- NET 12889
- VTX 10301, 10303
- }
- WIRE 10305, 0, 0
- {
- NET 12889
- VTX 10303, 9943
- }
- WIRE 10306, 0, 0
- {
- NET 12889
- VTX 9944, 9942
- }
- WIRE 10307, 0, 0
- {
- NET 12889
- VTX 9945, 11537
- }
- VTX 10308, 0, 0
- {
- COORD (1640,2120)
- }
- BUS 10309, 0, 0
- {
- NET 1858
- VTX 9887, 10308
- }
- BUS 10310, 0, 0
- {
- NET 1858
- VTX 10308, 9946
- }
- BUS 10311, 0, 0
- {
- NET 1858
- VTX 9947, 9887
- }
- BUS 10312, 0, 0
- {
- NET 1977
- VTX 9948, 9949
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10313, 0, 0
- {
- COORD (1340,2080)
- }
- BUS 10314, 0, 0
- {
- NET 1977
- VTX 9950, 10313
- }
- VTX 10315, 0, 0
- {
- COORD (1340,2100)
- }
- BUS 10316, 0, 0
- {
- NET 1977
- VTX 10313, 10315
- }
- VTX 10317, 0, 0
- {
- COORD (1100,2100)
- }
- BUS 10318, 0, 0
- {
- NET 1977
- VTX 10315, 10317
- }
- BUS 10319, 0, 0
- {
- NET 1977
- VTX 10317, 9948
- }
- VTX 10325, 0, 0
- {
- COORD (980,1400)
- }
- WIRE 10326, 0, 0
- {
- NET 948
- VTX 9953, 10325
- }
- VTX 10327, 0, 0
- {
- COORD (980,1240)
- }
- WIRE 10328, 0, 0
- {
- NET 948
- VTX 10325, 10327
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10329, 0, 0
- {
- COORD (720,1240)
- }
- WIRE 10330, 0, 0
- {
- NET 948
- VTX 10327, 10329
- }
- VTX 10331, 0, 0
- {
- COORD (720,1120)
- }
- WIRE 10332, 0, 0
- {
- NET 948
- VTX 10329, 10331
- }
- VTX 10333, 0, 0
- {
- COORD (320,1120)
- }
- WIRE 10334, 0, 0
- {
- NET 948
- VTX 10331, 10333
- }
- VTX 10335, 0, 0
- {
- COORD (320,340)
- }
- WIRE 10336, 0, 0
- {
- NET 948
- VTX 10333, 10335
- }
- WIRE 10337, 0, 0
- {
- NET 948
- VTX 10335, 9954
- }
- VTX 10338, 0, 0
- {
- COORD (950,220)
- }
- WIRE 10339, 0, 0
- {
- NET 4307
- VTX 9955, 10338
- }
- VTX 10340, 0, 0
- {
- COORD (950,810)
- }
- WIRE 10341, 0, 0
- {
- NET 4307
- VTX 10338, 10340
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10342, 0, 0
- {
- COORD (1015,810)
- }
- WIRE 10343, 0, 0
- {
- NET 4307
- VTX 10340, 10342
- }
- VTX 10344, 0, 0
- {
- COORD (1015,1100)
- }
- WIRE 10345, 0, 0
- {
- NET 4307
- VTX 10342, 10344
- }
- WIRE 10346, 0, 0
- {
- NET 4307
- VTX 10344, 9956
- }
- VTX 10347, 0, 0
- {
- COORD (1000,1360)
- }
- WIRE 10348, 0, 0
- {
- NET 935
- VTX 9957, 10347
- }
- VTX 10349, 0, 0
- {
- COORD (1000,1040)
- }
- WIRE 10350, 0, 0
- {
- NET 935
- VTX 10347, 10349
- }
- VTX 10351, 0, 0
- {
- COORD (1360,1040)
- }
- WIRE 10352, 0, 0
- {
- NET 935
- VTX 10349, 10351
- }
- VTX 10353, 0, 0
- {
- COORD (1360,260)
- }
- WIRE 10354, 0, 0
- {
- NET 935
- VTX 10351, 10353
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10355, 0, 0
- {
- COORD (1090,260)
- }
- WIRE 10356, 0, 0
- {
- NET 935
- VTX 10353, 10355
- }
- VTX 10357, 0, 0
- {
- COORD (1090,200)
- }
- WIRE 10358, 0, 0
- {
- NET 935
- VTX 10355, 10357
- }
- WIRE 10359, 0, 0
- {
- NET 935
- VTX 10357, 9958
- }
- VTX 10360, 0, 0
- {
- COORD (560,1460)
- }
- BUS 10361, 0, 0
- {
- NET 1442
- VTX 9959, 10360
- }
- VTX 10362, 0, 0
- {
- COORD (560,1380)
- }
- BUS 10363, 0, 0
- {
- NET 1442
- VTX 10360, 10362
- }
- VTX 10364, 0, 0
- {
- COORD (360,1380)
- }
- BUS 10365, 0, 0
- {
- NET 1442
- VTX 10362, 10364
- }
- VTX 10366, 0, 0
- {
- COORD (360,800)
- }
- BUS 10367, 0, 0
- {
- NET 1442
- VTX 10364, 10366
- }
- VTX 10368, 0, 0
- {
- COORD (1020,800)
- }
- BUS 10369, 0, 0
- {
- NET 1442
- VTX 10366, 10368
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10370, 0, 0
- {
- COORD (1020,840)
- }
- BUS 10371, 0, 0
- {
- NET 1442
- VTX 10368, 10370
- }
- BUS 10372, 0, 0
- {
- NET 1442
- VTX 10370, 9960
- }
- BUS 10373, 0, 0
- {
- NET 139
- VTX 9961, 9962
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10374, 0, 0
- {
- COORD (1010,860)
- }
- BUS 10375, 0, 0
- {
- NET 1929
- VTX 9963, 10374
- }
- VTX 10376, 0, 0
- {
- COORD (1010,920)
- }
- BUS 10377, 0, 0
- {
- NET 1929
- VTX 10374, 10376
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 10378, 0, 0
- {
- NET 1929
- VTX 10376, 9964
- }
- VTX 10379, 0, 0
- {
- COORD (1400,80)
- }
- WIRE 10380, 0, 0
- {
- NET 4306
- VTX 9965, 10379
- }
- VTX 10381, 0, 0
- {
- COORD (1400,980)
- }
- WIRE 10382, 0, 0
- {
- NET 4306
- VTX 10379, 10381
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10383, 0, 0
- {
- COORD (1020,980)
- }
- WIRE 10384, 0, 0
- {
- NET 4306
- VTX 10381, 10383
- }
- VTX 10385, 0, 0
- {
- COORD (1020,880)
- }
- WIRE 10386, 0, 0
- {
- NET 4306
- VTX 10383, 10385
- }
- WIRE 10387, 0, 0
- {
- NET 4306
- VTX 10385, 9966
- }
- VTX 10388, 0, 0
- {
- COORD (200,80)
- }
- WIRE 10389, 0, 0
- {
- NET 4576
- VTX 9967, 10388
- }
- WIRE 10390, 0, 0
- {
- NET 4576
- VTX 10388, 9912
- }
- VTX 10391, 0, 0
- {
- COORD (660,220)
- }
- WIRE 10392, 0, 0
- {
- NET 4576
- VTX 9968, 10391
- }
- WIRE 10393, 0, 0
- {
- NET 4576
- VTX 10391, 9967
- }
- VTX 10394, 0, 0
- {
- COORD (640,300)
- }
- WIRE 10395, 0, 0
- {
- NET 3828
- VTX 9969, 10394
- }
- WIRE 10396, 0, 0
- {
- NET 3828
- VTX 10394, 9970
- }
- VTX 10397, 0, 0
- {
- COORD (640,160)
- }
- WIRE 10398, 0, 0
- {
- NET 3828
- VTX 9971, 10397
- }
- WIRE 10399, 0, 0
- {
- NET 3828
- VTX 10397, 9970
- }
- WIRE 10400, 0, 0
- {
- NET 3107
- VTX 13307, 9972
- }
- WIRE 10401, 0, 0
- {
- NET 3107
- VTX 9972, 9973
- }
- VTX 10402, 0, 0
- {
- COORD (700,260)
- }
- WIRE 10403, 0, 0
- {
- NET 3107
- VTX 9974, 10402
- }
- VTX 10404, 0, 0
- {
- COORD (700,120)
- }
- WIRE 10405, 0, 0
- {
- NET 3107
- VTX 10402, 10404
- }
- WIRE 10406, 0, 0
- {
- NET 3107
- VTX 10404, 9972
- }
- VTX 10407, 0, 0
- {
- COORD (480,220)
- }
- WIRE 10408, 0, 0
- {
- NET 3828
- VTX 9970, 10407
- }
- WIRE 10409, 0, 0
- {
- NET 3828
- VTX 10407, 9975
- }
- VTX 10410, 0, 0
- {
- COORD (1360,1440)
- }
- BUS 10411, 0, 0
- {
- NET 1123
- VTX 9976, 10410
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10412, 0, 0
- {
- COORD (1360,1140)
- }
- BUS 10413, 0, 0
- {
- NET 1123
- VTX 10410, 10412
- }
- VTX 10414, 0, 0
- {
- COORD (1480,1140)
- }
- BUS 10415, 0, 0
- {
- NET 1123
- VTX 10412, 10414
- }
- VTX 10416, 0, 0
- {
- COORD (1480,1020)
- }
- BUS 10417, 0, 0
- {
- NET 1123
- VTX 10414, 10416
- }
- VTX 10418, 0, 0
- {
- COORD (1960,1020)
- }
- BUS 10419, 0, 0
- {
- NET 1123
- VTX 10416, 10418
- }
- VTX 10420, 0, 0
- {
- COORD (1960,980)
- }
- BUS 10421, 0, 0
- {
- NET 1123
- VTX 10418, 10420
- }
- BUS 10422, 0, 0
- {
- NET 1123
- VTX 10420, 9977
- }
- VTX 10436, 0, 0
- {
- COORD (2180,860)
- }
- BUS 10437, 0, 0
- {
- NET 12187
- VTX 9980, 10436
- }
- VTX 10438, 0, 0
- {
- COORD (2180,1040)
- }
- BUS 10439, 0, 0
- {
- NET 12187
- VTX 10436, 10438
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10440, 0, 0
- {
- COORD (1600,1040)
- }
- BUS 10441, 0, 0
- {
- NET 12187
- VTX 10438, 10440
- }
- VTX 10442, 0, 0
- {
- COORD (1600,960)
- }
- BUS 10443, 0, 0
- {
- NET 12187
- VTX 10440, 10442
- }
- BUS 10444, 0, 0
- {
- NET 12187
- VTX 10442, 9981
- }
- WIRE 10445, 0, 0
- {
- NET 4576
- VTX 9982, 9983
- }
- WIRE 10446, 0, 0
- {
- NET 4576
- VTX 9983, 9967
- }
- VTX 10447, 0, 0
- {
- COORD (1920,860)
- }
- WIRE 10448, 0, 0
- {
- NET 4576
- VTX 9984, 10447
- }
- VTX 10449, 0, 0
- {
- COORD (1920,660)
- }
- WIRE 10450, 0, 0
- {
- NET 4576
- VTX 10447, 10449
- }
- VTX 10451, 0, 0
- {
- COORD (1420,660)
- }
- WIRE 10452, 0, 0
- {
- NET 4576
- VTX 10449, 10451
- }
- VTX 10453, 0, 0
- {
- COORD (1420,280)
- }
- WIRE 10454, 0, 0
- {
- NET 4576
- VTX 10451, 10453
- }
- VTX 10455, 0, 0
- {
- COORD (1080,280)
- }
- WIRE 10456, 0, 0
- {
- NET 4576
- VTX 10453, 10455
- }
- WIRE 10457, 0, 0
- {
- NET 4576
- VTX 10455, 9983
- }
- WIRE 10458, 0, 0
- {
- NET 3107
- VTX 9985, 11943
- }
- WIRE 10464, 0, 0
- {
- NET 3107
- VTX 12356, 9988
- }
- VTX 10472, 0, 0
- {
- COORD (1460,1480)
- }
- BUS 10473, 0, 0
- {
- NET 1023
- VTX 9990, 10472
- }
- VTX 10474, 0, 0
- {
- COORD (1460,620)
- }
- BUS 10475, 0, 0
- {
- NET 1023
- VTX 10472, 10474
- }
- VTX 10476, 0, 0
- {
- COORD (1640,620)
- }
- BUS 10477, 0, 0
- {
- NET 1023
- VTX 10474, 10476
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10478, 0, 0
- {
- COORD (1640,540)
- }
- BUS 10479, 0, 0
- {
- NET 1023
- VTX 10476, 10478
- }
- BUS 10480, 0, 0
- {
- NET 1023
- VTX 10478, 9991
- }
- VTX 10481, 0, 0
- {
- COORD (1880,420)
- }
- BUS 10482, 0, 0
- {
- NET 5229
- VTX 9992, 10481
- }
- VTX 10483, 0, 0
- {
- COORD (1880,560)
- }
- BUS 10484, 0, 0
- {
- NET 5229
- VTX 10481, 10483
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 10485, 0, 0
- {
- NET 5229
- VTX 10483, 9993
- }
- VTX 10486, 0, 0
- {
- COORD (1440,420)
- }
- WIRE 10487, 0, 0
- {
- NET 4576
- VTX 9994, 10486
- }
- VTX 10488, 0, 0
- {
- COORD (1440,20)
- }
- WIRE 10489, 0, 0
- {
- NET 4576
- VTX 10486, 10488
- }
- VTX 10490, 0, 0
- {
- COORD (1080,20)
- }
- WIRE 10491, 0, 0
- {
- NET 4576
- VTX 10488, 10490
- }
- WIRE 10492, 0, 0
- {
- NET 4576
- VTX 10490, 9983
- }
- VTX 10497, 0, 0
- {
- COORD (1360,1660)
- }
- WIRE 10498, 0, 0
- {
- NET 4335
- VTX 9996, 10497
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10499, 0, 0
- {
- COORD (1360,1680)
- }
- WIRE 10500, 0, 0
- {
- NET 4335
- VTX 10497, 10499
- }
- WIRE 10501, 0, 0
- {
- NET 4335
- VTX 10499, 9997
- }
- WIRE 10502, 0, 0
- {
- NET 4576
- VTX 9998, 9922
- }
- VTX 10503, 0, 0
- {
- COORD (1120,1680)
- }
- WIRE 10504, 0, 0
- {
- NET 4576
- VTX 9999, 10503
- }
- WIRE 10505, 0, 0
- {
- NET 4576
- VTX 10503, 9922
- }
- VTX 10527, 0, 0
- {
- COORD (1080,1520)
- }
- WIRE 10528, 0, 0
- {
- NET 1076
- VTX 10004, 10527
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10529, 0, 0
- {
- COORD (1080,2300)
- }
- WIRE 10530, 0, 0
- {
- NET 1076
- VTX 10527, 10529
- }
- WIRE 10531, 0, 0
- {
- NET 1076
- VTX 10529, 10005
- }
- WIRE 10532, 0, 0
- {
- NET 4576
- VTX 10006, 10007
- }
- WIRE 10533, 0, 0
- {
- NET 4576
- VTX 10007, 9920
- }
- VTX 10534, 0, 0
- {
- COORD (1380,2180)
- }
- WIRE 10535, 0, 0
- {
- NET 4576
- VTX 10008, 10534
- }
- VTX 10536, 0, 0
- {
- COORD (1380,1940)
- }
- WIRE 10537, 0, 0
- {
- NET 4576
- VTX 10534, 10536
- }
- VTX 10538, 0, 0
- {
- COORD (1500,1940)
- }
- WIRE 10539, 0, 0
- {
- NET 4576
- VTX 10536, 10538
- }
- VTX 10540, 0, 0
- {
- COORD (1500,740)
- }
- WIRE 10541, 0, 0
- {
- NET 4576
- VTX 10538, 10540
- }
- VTX 10542, 0, 0
- {
- COORD (1340,740)
- }
- WIRE 10543, 0, 0
- {
- NET 4576
- VTX 10540, 10542
- }
- VTX 10544, 0, 0
- {
- COORD (1340,760)
- }
- WIRE 10545, 0, 0
- {
- NET 4576
- VTX 10542, 10544
- }
- VTX 10546, 0, 0
- {
- COORD (680,760)
- }
- WIRE 10547, 0, 0
- {
- NET 4576
- VTX 10544, 10546
- }
- WIRE 10548, 0, 0
- {
- NET 4576
- VTX 10546, 10007
- }
- WIRE 10549, 0, 0
- {
- NET 3107
- VTX 11912, 9987
- }
- BUS 10550, 0, 0
- {
- NET 1168
- VTX 9884, 10009
- }
- VTX 10551, 0, 0
- {
- COORD (1100,1720)
- }
- WIRE 10552, 0, 0
- {
- NET 1089
- VTX 10010, 10551
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10553, 0, 0
- {
- COORD (1100,1800)
- }
- WIRE 10554, 0, 0
- {
- NET 1089
- VTX 10551, 10553
- }
- WIRE 10555, 0, 0
- {
- NET 1089
- VTX 10553, 10011
- }
- VTX 10569, 0, 0
- {
- COORD (1040,2040)
- }
- BUS 10570, 0, 0
- {
- NET 1977
- VTX 9948, 10569
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10571, 0, 0
- {
- COORD (1040,1840)
- }
- BUS 10572, 0, 0
- {
- NET 1977
- VTX 10569, 10571
- }
- BUS 10573, 0, 0
- {
- NET 1977
- VTX 10571, 10014
- }
- VTX 10574, 0, 0
- {
- COORD (1140,1620)
- }
- VTX 10576, 0, 0
- {
- COORD (1140,2020)
- }
- WIRE 10577, 0, 0
- {
- NET 4563
- VTX 10574, 10576
- }
- WIRE 10578, 0, 0
- {
- NET 4563
- VTX 10576, 10016
- }
- VTX 10579, 0, 0
- {
- COORD (1000,1560)
- }
- WIRE 10580, 0, 0
- {
- NET 1059
- VTX 10017, 10579
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 10581, 0, 0
- {
- COORD (1000,1760)
- }
- WIRE 10582, 0, 0
- {
- NET 1059
- VTX 10579, 10581
- }
- VTX 10583, 0, 0
- {
- COORD (1040,1760)
- }
- WIRE 10584, 0, 0
- {
- NET 1059
- VTX 10581, 10583
- }
- VTX 10585, 0, 0
- {
- COORD (1040,1820)
- }
- WIRE 10586, 0, 0
- {
- NET 1059
- VTX 10583, 10585
- }
- VTX 10587, 0, 0
- {
- COORD (1100,1820)
- }
- WIRE 10588, 0, 0
- {
- NET 1059
- VTX 10585, 10587
- }
- VTX 10589, 0, 0
- {
- COORD (1100,1940)
- }
- WIRE 10590, 0, 0
- {
- NET 1059
- VTX 10587, 10589
- }
- VTX 10591, 0, 0
- {
- COORD (780,1940)
- }
- WIRE 10592, 0, 0
- {
- NET 1059
- VTX 10589, 10591
- }
- VTX 10593, 0, 0
- {
- COORD (780,2140)
- }
- WIRE 10594, 0, 0
- {
- NET 1059
- VTX 10591, 10593
- }
- WIRE 10595, 0, 0
- {
- NET 1059
- VTX 10593, 10018
- }
- WIRE 10596, 0, 0
- {
- NET 4576
- VTX 10019, 9917
- }
- VTX 10597, 0, 0
- {
- COORD (720,2020)
- }
- WIRE 10598, 0, 0
- {
- NET 4576
- VTX 10020, 10597
- }
- WIRE 10599, 0, 0
- {
- NET 4576
- VTX 10597, 9917
- }
- VTX 10617, 0, 0
- {
- COORD (1940,940)
- }
- WIRE 10618, 0, 0
- {
- NET 3990
- VTX 10022, 10617
- }
- WIRE 10619, 0, 0
- {
- NET 3990
- VTX 10617, 10023
- }
- WIRE 10644, 0, 0
- {
- NET 4576
- VTX 9919, 10029
- }
- VTX 10648, 0, 0
- {
- COORD (260,1000)
- }
- WIRE 10649, 0, 0
- {
- NET 12889
- VTX 9938, 10648
- }
- BUS 10651, 0, 0
- {
- NET 1935
- VTX 9906, 10032
- }
- WIRE 10661, 0, 0
- {
- NET 4482
- VTX 10036, 10037
- }
- VTX 10662, 0, 0
- {
- COORD (1120,1760)
- }
- WIRE 10663, 0, 0
- {
- NET 4482
- VTX 10038, 10662
- }
- WIRE 10664, 0, 0
- {
- NET 4482
- VTX 10662, 10036
- }
- WIRE 10665, 0, 0
- {
- NET 12889
- VTX 9943, 9941
- }
- WIRE 10666, 0, 0
- {
- NET 12889
- VTX 10039, 9943
- }
- VTX 10668, 0, 0
- {
- COORD (320,1960)
- }
- VTX 10669, 0, 0
- {
- COORD (280,1940)
- }
- VTX 10670, 0, 0
- {
- COORD (320,1880)
- }
- VTX 10671, 0, 0
- {
- COORD (280,1880)
- }
- VTX 10672, 0, 0
- {
- COORD (320,2000)
- }
- VTX 10673, 0, 0
- {
- COORD (280,2000)
- }
- VTX 10674, 0, 0
- {
- COORD (300,1960)
- }
- WIRE 10675, 0, 0
- {
- NET 3179
- VTX 10674, 10668
- }
- VTX 10676, 0, 0
- {
- COORD (300,1940)
- }
- WIRE 10677, 0, 0
- {
- NET 3179
- VTX 10674, 10676
- }
- WIRE 10678, 0, 0
- {
- NET 3179
- VTX 10676, 10669
- }
- BUS 10679, 0, 0
- {
- NET 3171
- VTX 10671, 10670
- }
- BUS 10680, 0, 0
- {
- NET 3175
- VTX 10673, 10672
- }
- VTX 10868, 0, 0
- {
- COORD (2040,1420)
- }
- VTX 10869, 0, 0
- {
- COORD (2180,1420)
- }
- VTX 10870, 0, 0
- {
- COORD (2040,1460)
- }
- VTX 10871, 0, 0
- {
- COORD (2180,1460)
- }
- VTX 10872, 0, 0
- {
- COORD (2040,1500)
- }
- VTX 10873, 0, 0
- {
- COORD (2180,1500)
- }
- BUS 10876, 0, 0
- {
- NET 2053
- VTX 10868, 10869
- }
- BUS 10877, 0, 0
- {
- NET 2000
- VTX 10870, 10871
- }
- BUS 10878, 0, 0
- {
- NET 2004
- VTX 10872, 10873
- }
- VTX 10977, 0, 0
- {
- COORD (800,2060)
- }
- VTX 10992, 0, 0
- {
- COORD (760,2060)
- }
- WIRE 10993, 0, 0
- {
- NET 3107
- VTX 10977, 10992
- }
- VTX 10994, 0, 0
- {
- COORD (760,2200)
- }
- WIRE 10995, 0, 0
- {
- NET 3107
- VTX 10992, 10994
- }
- VTX 10998, 0, 0
- {
- COORD (1520,700)
- }
- WIRE 10999, 0, 0
- {
- NET 3107
- VTX 9987, 10998
- }
- VTX 11000, 0, 0
- {
- COORD (1520,1960)
- }
- VTX 11002, 0, 0
- {
- COORD (1360,1960)
- }
- WIRE 11003, 0, 0
- {
- NET 3107
- VTX 11000, 11002
- }
- WIRE 11004, 0, 0
- {
- NET 3107
- VTX 11002, 12486
- }
- VTX 11154, 0, 0
- {
- COORD (1600,1460)
- }
- VTX 11155, 0, 0
- {
- COORD (2180,1580)
- }
- VTX 11156, 0, 0
- {
- COORD (1530,1460)
- }
- BUS 11157, 0, 0
- {
- NET 3140
- VTX 11154, 11156
- }
- VTX 11158, 0, 0
- {
- COORD (1530,1800)
- }
- BUS 11159, 0, 0
- {
- NET 3140
- VTX 11156, 11158
- }
- VTX 11160, 0, 0
- {
- COORD (2140,1800)
- }
- BUS 11161, 0, 0
- {
- NET 3140
- VTX 11158, 11160
- }
- VTX 11162, 0, 0
- {
- COORD (2140,1580)
- }
- BUS 11163, 0, 0
- {
- NET 3140
- VTX 11160, 11162
- }
- BUS 11164, 0, 0
- {
- NET 3140
- VTX 11162, 11155
- }
- VTX 11188, 0, 0
- {
- COORD (1900,600)
- }
- WIRE 11189, 0, 0
- {
- NET 133
- VTX 11188, 9854
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 11274, 0, 0
- {
- COORD (1600,1500)
- }
- VTX 11275, 0, 0
- {
- COORD (1960,2080)
- }
- VTX 11276, 0, 0
- {
- COORD (1600,1580)
- }
- VTX 11277, 0, 0
- {
- COORD (1960,1880)
- }
- VTX 11278, 0, 0
- {
- COORD (1560,1500)
- }
- BUS 11279, 0, 0
- {
- NET 3427
- VTX 11274, 11278
- }
- VTX 11280, 0, 0
- {
- COORD (1560,1980)
- }
- BUS 11281, 0, 0
- {
- NET 3427
- VTX 11278, 11280
- }
- VTX 11282, 0, 0
- {
- COORD (1980,1980)
- }
- BUS 11283, 0, 0
- {
- NET 3427
- VTX 11280, 11282
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 11284, 0, 0
- {
- COORD (1980,2080)
- }
- BUS 11285, 0, 0
- {
- NET 3427
- VTX 11282, 11284
- }
- BUS 11286, 0, 0
- {
- NET 3427
- VTX 11284, 11275
- }
- VTX 11287, 0, 0
- {
- COORD (1580,1580)
- }
- BUS 11288, 0, 0
- {
- NET 1880
- VTX 11276, 11287
- }
- VTX 11289, 0, 0
- {
- COORD (1580,1780)
- }
- BUS 11290, 0, 0
- {
- NET 1880
- VTX 11287, 11289
- }
- VTX 11291, 0, 0
- {
- COORD (1980,1780)
- }
- BUS 11292, 0, 0
- {
- NET 1880
- VTX 11289, 11291
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 11293, 0, 0
- {
- COORD (1980,1880)
- }
- BUS 11294, 0, 0
- {
- NET 1880
- VTX 11291, 11293
- }
- BUS 11295, 0, 0
- {
- NET 1880
- VTX 11293, 11277
- }
- VTX 11332, 0, 0
- {
- COORD (1020,1180)
- }
- VTX 11335, 0, 0
- {
- COORD (980,1180)
- }
- BUS 11336, 0, 0
- {
- NET 1250
- VTX 11339, 11335
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 11337, 0, 0
- {
- NET 1250
- VTX 11335, 11332
- }
- VTX 11339, 0, 0
- {
- COORD (980,1060)
- }
- BUS 11340, 0, 0
- {
- NET 1250
- VTX 9876, 11339
- }
- VTX 11537, 0, 0
- {
- COORD (760,1140)
- }
- WIRE 11538, 0, 0
- {
- NET 12889
- VTX 9939, 11537
- }
- WIRE 11539, 0, 0
- {
- NET 12889
- VTX 11537, 9938
- }
- VTX 11765, 0, 0
- {
- COORD (1540,1620)
- }
- VTX 11766, 0, 0
- {
- COORD (2180,1660)
- }
- WIRE 11767, 0, 0
- {
- NET 4563
- VTX 10015, 11765
- VARIABLES
- {
- #NAMED="1"
- }
- }
- WIRE 11768, 0, 0
- {
- NET 4563
- VTX 11765, 10574
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 11770, 0, 0
- {
- COORD (1540,1820)
- }
- WIRE 11771, 0, 0
- {
- NET 4563
- VTX 11765, 11770
- }
- VTX 11772, 0, 0
- {
- COORD (2180,1820)
- }
- WIRE 11773, 0, 0
- {
- NET 4563
- VTX 11770, 11772
- }
- WIRE 11774, 0, 0
- {
- NET 4563
- VTX 11772, 11766
- }
- INSTANCE 11775, 0, 0
- {
- VARIABLES
- {
- #COMPONENT="Output"
- #LIBRARY="#terminals"
- #REFERENCE="exp_wren"
- #SYMBOL="Output"
- }
- COORD (2180,1660)
- VERTEXES ( (2,11766) )
- }
- TEXT 11776, 0, 0
- {
- TEXT "$#REFERENCE"
- RECT (2232,1643,2370,1678)
- ALIGN 4
- MARGINS (1,1)
- PARENT 11775
- }
- VTX 11883, 0, 0
- {
- COORD (1600,1540)
- }
- VTX 11885, 0, 0
- {
- COORD (1380,1540)
- }
- WIRE 11886, 0, 0
- {
- NET 12897
- VTX 11883, 11885
- }
- VTX 11887, 0, 0
- {
- COORD (1380,1860)
- }
- WIRE 11888, 0, 0
- {
- NET 12897
- VTX 11885, 11887
- }
- VTX 11889, 0, 0
- {
- COORD (1060,1860)
- }
- WIRE 11890, 0, 0
- {
- NET 12897
- VTX 11887, 11889
- }
- VTX 11891, 0, 0
- {
- COORD (1060,1780)
- }
- WIRE 11892, 0, 0
- {
- NET 12897
- VTX 11889, 11891
- }
- VTX 11893, 0, 0
- {
- COORD (240,1780)
- }
- WIRE 11894, 0, 0
- {
- NET 12897
- VTX 11891, 11893
- }
- VTX 11898, 0, 0
- {
- COORD (1660,500)
- }
- VTX 11899, 0, 0
- {
- COORD (1560,520)
- }
- VTX 11900, 0, 0
- {
- COORD (1560,500)
- }
- WIRE 11901, 0, 0
- {
- NET 4214
- VTX 11898, 11900
- }
- WIRE 11902, 0, 0
- {
- NET 4214
- VTX 11900, 11899
- }
- VTX 11903, 0, 0
- {
- COORD (1160,1720)
- }
- VTX 11904, 0, 0
- {
- COORD (1150,1720)
- }
- WIRE 11905, 0, 0
- {
- NET 3107
- VTX 11903, 11904
- }
- VTX 11906, 0, 0
- {
- COORD (1150,1500)
- }
- WIRE 11907, 0, 0
- {
- NET 3107
- VTX 11904, 11906
- }
- VTX 11908, 0, 0
- {
- COORD (1420,1500)
- }
- WIRE 11909, 0, 0
- {
- NET 3107
- VTX 11906, 11908
- }
- VTX 11910, 0, 0
- {
- COORD (1420,760)
- }
- WIRE 11911, 0, 0
- {
- NET 3107
- VTX 11908, 11910
- }
- VTX 11912, 0, 0
- {
- COORD (1960,760)
- }
- WIRE 11913, 0, 0
- {
- NET 3107
- VTX 11910, 11912
- }
- WIRE 11915, 0, 0
- {
- NET 3107
- VTX 11912, 11943
- }
- VTX 11943, 0, 0
- {
- COORD (1960,900)
- }
- VTX 11945, 0, 0
- {
- COORD (800,2100)
- }
- VTX 11946, 0, 0
- {
- COORD (1520,1000)
- }
- WIRE 11947, 0, 0
- {
- NET 3107
- VTX 10998, 11946
- }
- WIRE 11948, 0, 0
- {
- NET 3107
- VTX 11946, 11000
- }
- VTX 11949, 0, 0
- {
- COORD (790,2100)
- }
- WIRE 11950, 0, 0
- {
- NET 3107
- VTX 11945, 11949
- }
- VTX 11951, 0, 0
- {
- COORD (790,1945)
- }
- WIRE 11952, 0, 0
- {
- NET 3107
- VTX 11949, 11951
- }
- VTX 11953, 0, 0
- {
- COORD (1155,1945)
- }
- WIRE 11954, 0, 0
- {
- NET 3107
- VTX 11951, 11953
- }
- VTX 11955, 0, 0
- {
- COORD (1155,1865)
- }
- WIRE 11956, 0, 0
- {
- NET 3107
- VTX 11953, 11955
- }
- VTX 11957, 0, 0
- {
- COORD (1475,1865)
- }
- WIRE 11958, 0, 0
- {
- NET 3107
- VTX 11955, 11957
- }
- VTX 11959, 0, 0
- {
- COORD (1475,1000)
- }
- WIRE 11960, 0, 0
- {
- NET 3107
- VTX 11957, 11959
- }
- WIRE 11961, 0, 0
- {
- NET 3107
- VTX 11959, 11946
- }
- VTX 12008, 0, 0
- {
- COORD (1600,1300)
- }
- VTX 12009, 0, 0
- {
- COORD (1580,2180)
- }
- VTX 12010, 0, 0
- {
- COORD (1590,1300)
- }
- WIRE 12011, 0, 0
- {
- NET 4417
- VTX 12008, 12010
- }
- VTX 12012, 0, 0
- {
- COORD (1590,2120)
- }
- WIRE 12013, 0, 0
- {
- NET 4417
- VTX 12010, 12012
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 12014, 0, 0
- {
- COORD (1600,2120)
- }
- WIRE 12015, 0, 0
- {
- NET 4417
- VTX 12012, 12014
- }
- VTX 12016, 0, 0
- {
- COORD (1600,2180)
- }
- WIRE 12017, 0, 0
- {
- NET 4417
- VTX 12014, 12016
- }
- WIRE 12018, 0, 0
- {
- NET 4417
- VTX 12016, 12009
- }
- NET BUS 12187, 0, 0
- {
- VARIABLES
- {
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="w_alu_op_r[4:0]"
- #VERILOG_TYPE="wire"
- }
- }
- VTX 12356, 0, 0
- {
- COORD (2120,560)
- }
- VTX 12417, 0, 0
- {
- COORD (1960,660)
- }
- WIRE 12418, 0, 0
- {
- NET 3107
- VTX 9987, 12417
- }
- VTX 12419, 0, 0
- {
- COORD (2120,660)
- }
- WIRE 12420, 0, 0
- {
- NET 3107
- VTX 12417, 12419
- }
- WIRE 12422, 0, 0
- {
- NET 3107
- VTX 12356, 12419
- }
- VTX 12479, 0, 0
- {
- COORD (1400,2220)
- }
- VTX 12482, 0, 0
- {
- COORD (1360,2220)
- }
- WIRE 12483, 0, 0
- {
- NET 3107
- VTX 12486, 12482
- }
- WIRE 12484, 0, 0
- {
- NET 3107
- VTX 12482, 12479
- }
- VTX 12486, 0, 0
- {
- COORD (1360,2200)
- }
- WIRE 12487, 0, 0
- {
- NET 3107
- VTX 10994, 12486
- }
- VTX 12587, 0, 0
- {
- COORD (1400,2260)
- }
- VTX 12588, 0, 0
- {
- COORD (1180,2220)
- }
- WIRE 12589, 0, 0
- {
- NET 4482
- VTX 10036, 12588
- }
- VTX 12590, 0, 0
- {
- COORD (1180,2260)
- }
- WIRE 12591, 0, 0
- {
- NET 4482
- VTX 12588, 12590
- }
- WIRE 12592, 0, 0
- {
- NET 4482
- VTX 12590, 12587
- }
- VTX 12685, 0, 0
- {
- COORD (640,920)
- }
- VTX 12686, 0, 0
- {
- COORD (720,660)
- }
- VTX 12688, 0, 0
- {
- COORD (720,920)
- }
- BUS 12689, 0, 0
- {
- NET 1936
- VTX 12686, 12688
- VARIABLES
- {
- #NAMED="1"
- }
- }
- BUS 12690, 0, 0
- {
- NET 1936
- VTX 12688, 12685
- }
- NET BUS 12776, 0, 0
- {
- VARIABLES
- {
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="w_file_o[7:0]"
- #VERILOG_TYPE="wire"
- }
- }
- NET WIRE 12889, 0, 0
- WIRE 12891, 0, 0
- {
- NET 12889
- VTX 10648, 10033
- }
- VTX 12892, 0, 0
- {
- COORD (440,960)
- }
- VTX 12893, 0, 0
- {
- COORD (240,960)
- }
- WIRE 12894, 0, 0
- {
- NET 12897
- VTX 11893, 12893
- }
- WIRE 12896, 0, 0
- {
- NET 12897
- VTX 12892, 12893
- }
- NET WIRE 12897, 0, 0
- VTX 13254, 0, 0
- {
- COORD (2120,340)
- }
- WIRE 13255, 0, 0
- {
- NET 3107
- VTX 13266, 13254
- VARIABLES
- {
- #NAMED="1"
- }
- }
- WIRE 13256, 0, 0
- {
- NET 3107
- VTX 13254, 12356
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13261, 0, 0
- {
- COORD (1660,460)
- }
- VTX 13263, 0, 0
- {
- COORD (1560,460)
- }
- WIRE 13264, 0, 0
- {
- NET 3107
- VTX 13261, 13263
- }
- VTX 13266, 0, 0
- {
- COORD (1560,340)
- }
- WIRE 13270, 0, 0
- {
- NET 3107
- VTX 13263, 13266
- }
- VTX 13307, 0, 0
- {
- COORD (1060,340)
- }
- WIRE 13311, 0, 0
- {
- NET 3107
- VTX 13307, 13266
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13405, 0, 0
- {
- COORD (1020,480)
- }
- VTX 13407, 0, 0
- {
- COORD (960,1600)
- }
- VTX 13408, 0, 0
- {
- COORD (1020,520)
- }
- VTX 13409, 0, 0
- {
- COORD (1020,560)
- }
- VTX 13410, 0, 0
- {
- COORD (1020,600)
- }
- VTX 13411, 0, 0
- {
- COORD (740,500)
- }
- VTX 13412, 0, 0
- {
- COORD (1020,640)
- }
- VTX 13413, 0, 0
- {
- COORD (2040,1540)
- }
- VTX 13414, 0, 0
- {
- COORD (1020,680)
- }
- VTX 13415, 0, 0
- {
- COORD (1020,440)
- }
- VTX 13416, 0, 0
- {
- COORD (1020,400)
- }
- VTX 13417, 0, 0
- {
- COORD (1000,340)
- }
- WIRE 13418, 0, 0
- {
- NET 3107
- VTX 13307, 13417
- }
- VTX 13419, 0, 0
- {
- COORD (1000,480)
- }
- WIRE 13420, 0, 0
- {
- NET 3107
- VTX 13417, 13419
- VARIABLES
- {
- #NAMED="1"
- }
- }
- WIRE 13421, 0, 0
- {
- NET 3107
- VTX 13419, 13405
- }
- VTX 13433, 0, 0
- {
- COORD (1140,1600)
- }
- BUS 13434, 0, 0
- {
- NET 1040
- VTX 13407, 13433
- }
- VTX 13435, 0, 0
- {
- COORD (1140,1460)
- }
- BUS 13436, 0, 0
- {
- NET 1040
- VTX 13433, 13435
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13437, 0, 0
- {
- COORD (1440,1460)
- }
- BUS 13438, 0, 0
- {
- NET 1040
- VTX 13435, 13437
- }
- VTX 13439, 0, 0
- {
- COORD (1440,1120)
- }
- BUS 13440, 0, 0
- {
- NET 1040
- VTX 13437, 13439
- }
- VTX 13441, 0, 0
- {
- COORD (1560,1120)
- }
- BUS 13442, 0, 0
- {
- NET 1040
- VTX 13439, 13441
- }
- VTX 13443, 0, 0
- {
- COORD (1560,600)
- }
- BUS 13444, 0, 0
- {
- NET 1040
- VTX 13441, 13443
- }
- VTX 13445, 0, 0
- {
- COORD (1460,600)
- }
- BUS 13446, 0, 0
- {
- NET 1040
- VTX 13443, 13445
- }
- VTX 13447, 0, 0
- {
- COORD (1460,320)
- }
- BUS 13448, 0, 0
- {
- NET 1040
- VTX 13445, 13447
- }
- VTX 13449, 0, 0
- {
- COORD (960,320)
- }
- BUS 13450, 0, 0
- {
- NET 1040
- VTX 13447, 13449
- }
- VTX 13451, 0, 0
- {
- COORD (960,520)
- }
- BUS 13452, 0, 0
- {
- NET 1040
- VTX 13449, 13451
- }
- BUS 13453, 0, 0
- {
- NET 15035
- VTX 13451, 13408
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13454, 0, 0
- {
- COORD (380,640)
- }
- BUS 13455, 0, 0
- {
- NET 1168
- VTX 9871, 13454
- }
- VTX 13456, 0, 0
- {
- COORD (760,640)
- }
- BUS 13457, 0, 0
- {
- NET 1168
- VTX 13454, 13456
- }
- VTX 13458, 0, 0
- {
- COORD (760,560)
- }
- BUS 13459, 0, 0
- {
- NET 1168
- VTX 13456, 13458
- }
- BUS 13460, 0, 0
- {
- NET 1168
- VTX 13458, 13409
- }
- VTX 13461, 0, 0
- {
- COORD (1000,660)
- }
- BUS 13462, 0, 0
- {
- NET 1936
- VTX 12686, 13461
- }
- VTX 13463, 0, 0
- {
- COORD (1000,600)
- }
- BUS 13464, 0, 0
- {
- NET 1936
- VTX 13461, 13463
- }
- BUS 13465, 0, 0
- {
- NET 1936
- VTX 13463, 13410
- }
- VTX 13466, 0, 0
- {
- COORD (800,500)
- }
- BUS 13467, 0, 0
- {
- NET 1930
- VTX 13411, 13466
- }
- VTX 13468, 0, 0
- {
- COORD (800,640)
- }
- BUS 13469, 0, 0
- {
- NET 1930
- VTX 13466, 13468
- }
- BUS 13470, 0, 0
- {
- NET 1930
- VTX 13468, 13412
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13471, 0, 0
- {
- COORD (2160,1540)
- }
- BUS 13472, 0, 0
- {
- NET 801
- VTX 13413, 13471
- }
- VTX 13473, 0, 0
- {
- COORD (2160,1180)
- }
- BUS 13474, 0, 0
- {
- NET 801
- VTX 13471, 13473
- }
- VTX 13475, 0, 0
- {
- COORD (1540,1180)
- }
- BUS 13476, 0, 0
- {
- NET 801
- VTX 13473, 13475
- }
- VTX 13477, 0, 0
- {
- COORD (1540,780)
- }
- BUS 13478, 0, 0
- {
- NET 801
- VTX 13475, 13477
- }
- VTX 13479, 0, 0
- {
- COORD (1000,780)
- }
- BUS 13480, 0, 0
- {
- NET 801
- VTX 13477, 13479
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13481, 0, 0
- {
- COORD (1000,680)
- }
- BUS 13482, 0, 0
- {
- NET 801
- VTX 13479, 13481
- }
- BUS 13483, 0, 0
- {
- NET 801
- VTX 13481, 13414
- }
- VTX 13484, 0, 0
- {
- COORD (980,1020)
- }
- BUS 13485, 0, 0
- {
- NET 1250
- VTX 11339, 13484
- }
- VTX 13486, 0, 0
- {
- COORD (1380,1020)
- }
- BUS 13487, 0, 0
- {
- NET 1250
- VTX 13484, 13486
- }
- VTX 13488, 0, 0
- {
- COORD (1380,300)
- }
- BUS 13489, 0, 0
- {
- NET 1250
- VTX 13486, 13488
- }
- VTX 13490, 0, 0
- {
- COORD (980,300)
- }
- BUS 13491, 0, 0
- {
- NET 1250
- VTX 13488, 13490
- }
- VTX 13492, 0, 0
- {
- COORD (980,440)
- }
- BUS 13493, 0, 0
- {
- NET 1250
- VTX 13490, 13492
- }
- BUS 13494, 0, 0
- {
- NET 1250
- VTX 13492, 13415
- }
- VTX 13495, 0, 0
- {
- COORD (240,400)
- }
- WIRE 13497, 0, 0
- {
- NET 12897
- VTX 13495, 13416
- }
- VTX 13498, 0, 0
- {
- COORD (1340,740)
- }
- VTX 13499, 0, 0
- {
- COORD (1300,480)
- }
- VTX 13500, 0, 0
- {
- COORD (280,740)
- }
- BUS 13501, 0, 0
- {
- NET 1935
- VTX 9906, 13500
- }
- BUS 13502, 0, 0
- {
- NET 1935
- VTX 13500, 13498
- VARIABLES
- {
- #NAMED="1"
- }
- }
- VTX 13503, 0, 0
- {
- COORD (1340,480)
- }
- BUS 13504, 0, 0
- {
- NET 1935
- VTX 13499, 13503
- }
- BUS 13505, 0, 0
- {
- NET 1935
- VTX 13503, 13498
- }
- WIRE 13702, 0, 0
- {
- NET 12897
- VTX 12893, 13495
- }
- VTX 13703, 0, 0
- {
- COORD (180,400)
- }
- WIRE 13704, 0, 0
- {
- NET 12897
- VTX 13495, 13703
- }
- NET BUS 15035, 0, 0
- {
- VARIABLES
- {
- #MDA_RECORD_TOKEN="OTHER"
- #NAME="w_pc_gen_ctl[2:0]"
- #VERILOG_TYPE="wire"
- }
- }
- TEXT 15036, 0, 0
- {
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Index: trunk/mem_man.v
===================================================================
--- trunk/mem_man.v (revision 4)
+++ trunk/mem_man.v (nonexistent)
@@ -1,106 +0,0 @@
-`include "clairisc_def.h"
-
-module mem_man(
- input wr_en,
- input clk,
- input rst,
- output reg [7:0] dout,
- output co,
- output [1:0] bank,
- input [6:0] rd_addr,
- input [6:0] wr_addr,
- output [6:0] exp_wr_addr,
- output [6:0] exp_rd_addr,
- output [7:0] exp_dout,
- input ci,
- input zi,
- input z_wr,
- input c_wr,
- input [7:0] exp_din ,
- input [7:0] din ,
- output reg [7:0]status
- );
-
- reg wr_en_r;
- reg [6:0] din_r, wr_addr_r;
- reg [6:0] rd_addr_r;
-
- always @(posedge clk)
- begin
- wr_addr_r<=wr_addr;
- rd_addr_r<=rd_addr;
- wr_en_r<=wr_en;
- din_r<=din;
- end
-
- wire [7:0] ram_q ;
- wire [7:0] alt_ram_q;
-
-/*`ifdef SIM
- reg_file i_reg_file(
- .data(din),
- .wren(wr_en),
- .wraddress(wr_addr),
- .rdaddress(rd_addr),
- .clock(clk),
- .q(alt_ram_q)
- );
-`else
- */
- sim_reg_file i_reg_file(
- .data(din),
- .wren(wr_en),
- .wraddress(wr_addr),
- .rdaddress(rd_addr),
- .clock(clk),
- .q(alt_ram_q));
-//`endif
-
- assign ram_q = ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:alt_ram_q;
-
- /*status register*/
- wire write_status = wr_addr == `ADDR_STATUS && wr_en ;
- always@(posedge clk)
- begin
- if (rst)status<=8'h3f;//default value
- else
- if (write_status)status<=din;
- else
- begin
- if (c_wr)status[0]<=ci;
- if (z_wr)status[2]<=zi;
- end
- end
-
- assign co = status[0];
- assign zo = status[2];
-
- /*fsr register*/
- reg [6:0] fsr;
- wire write_fsr = wr_addr == `ADDR_FSR &&wr_en ;
- always@(posedge clk)
- begin
- if (rst)fsr<=0;
- else if(write_fsr) fsr<=din[6:0];
- end
-
- //reg [7:0] status;
- assign bank = fsr[6:5];
-
- /*data bus output logic*/
- always@(*)//select status,fsr,ram,exp_din
- casex(rd_addr_r)
- `ADDR_FSR:dout = fsr;
- `ADDR_STATUS:dout = status;
- 7'b00_01XXX,7'b01_01XXX,7'b10_01XXX,7'b11_01XXX,7'b00_10XXX,7'b00_11XXX,
- 7'b01_10XXX,7'b01_11XXX,7'b10_10XXX,7'b10_11XXX,7'b11_10XXX,7'b11_11XXX:
- dout = ram_q ;
- default dout = exp_din;
- endcase
-
- /*exp device bus logic*/
- assign exp_rd_addr = rd_addr;
- assign exp_wr_addr = wr_addr;
- assign exp_dout =din;
-
-endmodule
Index: trunk/utilities.v
===================================================================
--- trunk/utilities.v (revision 4)
+++ trunk/utilities.v (nonexistent)
@@ -1,107 +0,0 @@
-
-`include "clairisc_def.h"
-
-module ins2wb_addr(
- input [11:0] ins,
- output [4:0] wb_addr //wirte back addr
- );
- assign wb_addr = ins[4:0];
-endmodule
-
-module mem_addr(
- input [1:0] bank,
- input [4:0]addr,
- output [6:0] file_addr
- );
- assign file_addr = {bank[1:0],addr[4:0]};
-endmodule
-
-
-module ins2bd(
- input [11:0] ins,
- output reg [7:0] bd
- );
- always @ (*)
- case (ins[8:6])
- 0:bd=1<<0;
- 1:bd=1<<1;
- 2:bd=1<<2;
- 3:bd=1<<3;
- 4:bd=1<<4;
- 5:bd=1<<5;
- 6:bd=1<<6;
- 7:bd=1<<7;
- endcase
-endmodule
-
-module alu_muxa(
- input ctl,
- output reg [7:0]alu_a,
- input [7:0]w,
- input [7:0]bd
- );
- always@(*)
- if (ctl==`MUXA_W)
- alu_a=w;
- else
- alu_a=bd;
-endmodule
-
-module alu_muxb(
- input ctl,
- output reg [7:0] alu_b,
- input [8:0] k,
- input [7:0] f
- );
- always@(*)
- if (ctl==`MUXB_EK)
- alu_b=k[7:0];
- else alu_b=f;
-endmodule
-
-
-module pc_gen(
- input [10:0]pc_i,
- output reg [10:0] pc_o,
- input [11:0] ins,
- input [8:0] ek,
- input [10:0] stack_pc,
- input [2:0]ctl,
- input brc,
- input rst,
- input [7:0]status
- );
- always @ (*)
- if (rst)
- pc_o ='h1ff; //THE RST ENTRY
- else
- if (brc)
- begin
- pc_o = pc_i+1;
- end
- else
- begin
- case(ctl)
- // `PC_NOP :pc_o = pc_i+1;
- // `PC_BRC : if(brc)pc_o = {status[7:6],ek[8:0]}; //jmp_addr means K
- `PC_GOTO,
- `PC_CALL: pc_o = {status[7:6],ins[8:0]};
- `PC_RET: pc_o = stack_pc;
- default
- pc_o = pc_i+1;
- endcase
- end
-endmodule
-
-
-module bg(
- input z ,
- input [1:0]ctl,
- output reg branch);
- always @(*)
- case (ctl)
- `BG_ZERO :branch = ~z; //if the ALU result is 0 then the next instrction will be discarded
- `BG_NZERO :branch = z; //if the ALU result is not zero ,then skip the next instruction
- default branch = 0;
- endcase
-endmodule