URL
https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk
Subversion Repositories mod_mult_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/mod_mult_exp/trunk/bench/vhdl/mod_exp/ModExp32bitTB.vhd
0,0 → 1,229
----------------------------------------------------------------------- |
---- ---- |
---- Montgomery modular multiplier and exponentiator ---- |
---- ---- |
---- This file is part of the Montgomery modular multiplier ---- |
---- and exponentiator project ---- |
---- http://opencores.org/project,mod_mult_exp ---- |
---- ---- |
---- Description: ---- |
---- This is TestBench for the Montgomery modular exponentiator ---- |
---- with the 32 bit width. ---- |
---- It takes four nubers - base, power, modulus and Montgomery ---- |
---- residuum (2^(2*word_length) mod N) as the input and results ---- |
---- the modular exponentiation A^B mod M. ---- |
---- In fact input data are read through one input controlled by ---- |
---- the ctrl input. ---- |
---- To Do: ---- |
---- ---- |
---- Author(s): ---- |
---- - Krzysztof Gajewski, gajos@opencores.org ---- |
---- k.gajewski@gmail.com ---- |
---- ---- |
----------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and-or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
----------------------------------------------------------------------- |
LIBRARY ieee; |
use work.properties.ALL; |
USE ieee.std_logic_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY ModExp32bitTB IS |
END ModExp32bitTB; |
|
ARCHITECTURE behavior OF ModExp32bitTB IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT ModExp |
PORT( |
input : in STD_LOGIC_VECTOR(31 downto 0); |
ctrl : in STD_LOGIC_VECTOR(2 downto 0); |
clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
data_in_ready : in STD_LOGIC; |
ready : out STD_LOGIC; |
output : out STD_LOGIC_VECTOR(31 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal input : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); |
signal ctrl : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); |
signal clk : STD_LOGIC := '0'; |
signal reset : STD_LOGIC := '0'; |
signal data_in_ready : STD_LOGIC := '0'; |
|
--Outputs |
signal ready : STD_LOGIC; |
signal output : STD_LOGIC_VECTOR(31 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: ModExp PORT MAP ( |
input => input, |
ctrl => ctrl, |
clk => clk, |
reset => reset, |
data_in_ready => data_in_ready, |
ready => ready, |
output => output |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '1'; |
wait for clk_period/2; |
clk <= '0'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
reset <= '1'; |
wait for 100 ns; |
reset <= '0'; |
wait for clk_period*10; |
|
---- Preparation for test case 1 ----------------- |
-- base = 123456789 in decimal |
-- = 0x75bcd15 in hexadecimal |
-- exponent = 654321 in decimal |
-- = 0x9fbf1 in hexhexadecimal |
-- modulus = 2147483659 in decimal |
-- = 0x8000000b in hexhexadecimal |
-- expected_result = 347621222 in decimal, |
-- in hex 0x14b84766 |
-- power_mod( |
-- 123456789, |
-- 654321, |
-- 2147483659 |
-- ) = |
-- = 347621222 |
-- = 0x14b84766 in hexadecimal |
-- where 484 is the residuum |
-------------------------------------------------- |
|
data_in_ready <= '1'; |
ctrl <= mn_read_base; |
input <= x"075bcd15"; |
wait for clk_period*2; |
|
ctrl <= mn_read_modulus; |
input <= x"8000000b"; |
wait for clk_period*2; |
|
ctrl <= mn_read_exponent; |
input <= x"0009fbf1"; |
wait for clk_period*2; |
|
ctrl <= mn_read_residuum; |
input <= x"000001e4"; |
wait for clk_period*2; |
|
ctrl <= mn_count_power; |
|
wait until ready = '1' and clk = '0'; |
|
if output /= x"14b84766" then |
report "RESULT MISMATCH! Test case 1 failed" severity ERROR; |
assert false severity failure; |
else |
report "Test case 1 successful" severity note; |
end if; |
|
ctrl <= mn_show_result; |
wait for clk_period*10; |
|
ctrl <= mn_prepare_for_data; |
wait for clk_period*10; |
|
---- Preparation for test case 2 ----------------- |
-- base = 17654321 in decimal |
-- = 10d6231 in hexadecimal |
-- exponent = 434342 in decimal |
-- = 6a0a6 in hexhexadecimal |
-- modulus = 2147483693 in decimal |
-- = 0x8000002d in hexhexadecimal |
-- expected_result = 1290319095 in decimal, |
-- in hex 0x4ce8b4f7 |
-- power_mod( |
-- 17654321, |
-- 434342, |
-- 2147483693 |
-- ) = |
-- = 1290319095 |
-- = 0x4ce8b4f7 in hexadecimal |
-- where 8100 is the residuum |
-------------------------------------------------- |
|
ctrl <= mn_read_base; |
input <= x"010d6231"; |
wait for clk_period*2; |
|
ctrl <= mn_read_modulus; |
input <= x"8000002d"; |
wait for clk_period*2; |
|
ctrl <= mn_read_exponent; |
input <= x"0006a0a6"; |
wait for clk_period*2; |
|
ctrl <= mn_read_residuum; |
input <= x"00001fa4"; |
wait for clk_period*2; |
|
ctrl <= mn_count_power; |
|
wait until ready = '1' and clk = '0'; |
|
if output /= x"4ce8b4f7" then |
report "RESULT MISMATCH! Test case 2 failed" severity ERROR; |
assert false severity failure; |
else |
report "Test case 2 successful" severity note; |
end if; |
|
ctrl <= mn_show_result; |
wait for clk_period*10; |
ctrl <= mn_prepare_for_data; |
wait for clk_period*10; |
|
assert false severity failure; |
end process; |
|
END; |
/mod_mult_exp/trunk/bench/vhdl/mod_exp/ModExp512bitTB.vhd
0,0 → 1,235
----------------------------------------------------------------------- |
---- ---- |
---- Montgomery modular multiplier and exponentiator ---- |
---- ---- |
---- This file is part of the Montgomery modular multiplier ---- |
---- and exponentiator project ---- |
---- http://opencores.org/project,mod_mult_exp ---- |
---- ---- |
---- Description: ---- |
---- This is TestBench for the Montgomery modular exponentiator ---- |
---- with the 512 bit width. ---- |
---- It takes four nubers - base, power, modulus and Montgomery ---- |
---- residuum (2^(2*word_length) mod N) as the input and results ---- |
---- the modular exponentiation A^B mod M. ---- |
---- In fact input data are read through one input controlled by ---- |
---- the ctrl input. ---- |
---- To Do: ---- |
---- ---- |
---- Author(s): ---- |
---- - Krzysztof Gajewski, gajos@opencores.org ---- |
---- k.gajewski@gmail.com ---- |
---- ---- |
----------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and-or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
----------------------------------------------------------------------- |
LIBRARY ieee; |
use work.properties.ALL; |
USE ieee.std_logic_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY ModExp512bitTB IS |
END ModExp512bitTB; |
|
ARCHITECTURE behavior OF ModExp512bitTB IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT ModExp |
PORT( |
input : in STD_LOGIC_VECTOR(511 downto 0); |
ctrl : in STD_LOGIC_VECTOR(2 downto 0); |
clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
data_in_ready : in STD_LOGIC; |
ready : out STD_LOGIC; |
output : out STD_LOGIC_VECTOR(511 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal input : STD_LOGIC_VECTOR(511 downto 0) := (others => '0'); |
signal ctrl : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); |
signal clk : STD_LOGIC := '0'; |
signal reset : STD_LOGIC := '0'; |
signal data_in_ready : STD_LOGIC := '0'; |
|
--Outputs |
signal ready : STD_LOGIC; |
signal output : STD_LOGIC_VECTOR(511 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: ModExp PORT MAP ( |
input => input, |
ctrl => ctrl, |
clk => clk, |
reset => reset, |
data_in_ready => data_in_ready, |
ready => ready, |
output => output |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '1'; |
wait for clk_period/2; |
clk <= '0'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
reset <= '1'; |
wait for 100 ns; |
reset <= '0'; |
wait for clk_period*10; |
|
---- Preparation for test case 1 ----------------- |
-- base = 409173825987017733751648542997566029938148046617392981389751408119740010106823408957031501223019018303621410623709446515603337041483208280918267736985 in decimal |
-- = 0x1ffffffffffffffffffff003031300d060960864801650304020105000420f75db0d45d3189d910fc5d782745578c59481accf6f7cbf5e79bdecbe5233399 in hexadecimal |
-- exponent = 4991398326204141236652697335767169457643189913066361675852469427068576791337775798287514344957972397666876518042551243608843475377858636774161719825165098 in decimal |
-- = 0x5f4d7261a28d1e9c9a45059eb0ce9122f6840ec7878d2d2a87057fb15db61eac7a37af6b0cb80f0001870b2a29e350f7b052cc89f1c7fbed07926640d6926b2a in hexhexadecimal |
-- modulus = 7630362531884975956392615644472323592768112181489355162005628253173318027895577525003064336256778044210380071348425604079063304117213210643679811834656203 in decimal |
-- = 0x91b06f65a203bebb1cfa1b065cb2142e3771d113024a902f0829be8effe539ff6caa7c4b7f87e1913481e8c4f88a3f3e27a853179119aa029fe00e4c45a6b5cb in hexhexadecimal |
-- expected_result = 1030188469358454649940099943953262093153216946958355916901057176262906329079894663437512624898962713254938994365603039233579679436863344699542897702118673 in decimal, |
-- in hex 13ab74d318c919ec6faa10bea70211d4a981e7c31fc5205a8bb28e754ea59bcdd7459d6880758653918e72376c061177fdd51e72bece6815aa24001bda6ea511 |
-- power_mod( |
-- 409173825987017733751648542997566029938148046617392981389751408119740010106823408957031501223019018303621410623709446515603337041483208280918267736985, |
-- 4991398326204141236652697335767169457643189913066361675852469427068576791337775798287514344957972397666876518042551243608843475377858636774161719825165098, |
-- 7630362531884975956392615644472323592768112181489355162005628253173318027895577525003064336256778044210380071348425604079063304117213210643679811834656203 |
-- ) = |
-- = 1030188469358454649940099943953262093153216946958355916901057176262906329079894663437512624898962713254938994365603039233579679436863344699542897702118673 |
-- = 13ab74d318c919ec6faa10bea70211d4a981e7c31fc5205a8bb28e754ea59bcdd7459d6880758653918e72376c061177fdd51e72bece6815aa24001bda6ea511 in hexadecimal |
-- where 1398454690893823236632472980512935706632382980363069616905016603014572888067778885889245016848922097099694154000460402372958600055088633374563202044624216 is the residuum |
-------------------------------------------------- |
|
data_in_ready <= '1'; |
ctrl <= mn_read_base; |
input <= x"0001ffffffffffffffffffff003031300d060960864801650304020105000420f75db0d45d3189d910fc5d782745578c59481accf6f7cbf5e79bdecbe5233399"; |
wait for clk_period*2; |
|
ctrl <= mn_read_modulus; |
input <= x"91b06f65a203bebb1cfa1b065cb2142e3771d113024a902f0829be8effe539ff6caa7c4b7f87e1913481e8c4f88a3f3e27a853179119aa029fe00e4c45a6b5cb"; |
wait for clk_period*2; |
|
ctrl <= mn_read_exponent; |
input <= x"5f4d7261a28d1e9c9a45059eb0ce9122f6840ec7878d2d2a87057fb15db61eac7a37af6b0cb80f0001870b2a29e350f7b052cc89f1c7fbed07926640d6926b2a"; |
wait for clk_period*2; |
|
ctrl <= mn_read_residuum; |
input <= "00011010101100111000000100001111010111001110011000001010110100001111011110111000011110111011111111011111011001111011010101010101010110010011001000010110100100100000010000100101001111011100001101111011001011010100011101100100011100101001110000101011100100101110111100101110011111101000111100101010100010000100011111010101111000100111101101011011000010111010011011000100000101001000111011010110110100001111001100001110001111111110000000011001010101111000101010101000110111011000110110110000000100010111110101011000"; |
wait for clk_period*2; |
|
ctrl <= mn_count_power; |
|
report "Please wait. It may take up ro few minutes..." severity note; |
|
wait until ready = '1' and clk = '0'; |
|
if output /= x"13ab74d318c919ec6faa10bea70211d4a981e7c31fc5205a8bb28e754ea59bcdd7459d6880758653918e72376c061177fdd51e72bece6815aa24001bda6ea511" then |
report "RESULT MISMATCH! Test case 1 failed" severity ERROR; |
assert false severity failure; |
else |
report "Test case 1 successful" severity note; |
end if; |
|
ctrl <= mn_show_result; |
wait for clk_period*10; |
|
ctrl <= mn_prepare_for_data; |
wait for clk_period*2; |
|
---- Preparation for test case 2 ----------------- |
-- base = 3273390607896141870013189696827599152216642046043064789483291368096133796404674554883270092325904157150886684127560071009217256545885393053328527589431 in decimal |
-- = 0x100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037 in hexadecimal |
-- exponent = 622376668989630299558359971768444342820680304013329676986135064534413345603604938346345762083389451304101819605682193623416033951320823027994905238921170 in decimal |
-- = 0xbe21d214053f66c3e101fd875b531ecaccca3befca14d989ae2ffe4d6bbf1a3df0c694dc4c83af61ee3cf7c7bc97c9d6844d5d1fe428105082910c637c55fd2 in hexhexadecimal |
-- modulus = 3351951982485649274893506249551461531869841455148098344430890360930446855046914914263767984168972974033957028381338463851007479808527777429670210341401251 in decimal |
-- = 0x400000000000000000000000000000000000000000000000000000000302929200000000000000000000000000000000000000000000000000005af3fbdb72a3 in hexhexadecimal |
-- expected_result = 1135574785903187283000914738069914842639275616893687122668359807022003618585980215260939798952644749528921700342000274265548842002316414917974647561961683 in decimal, |
-- in hex 15ae92ed25cdbb29458414ad1a28fa35f5bfc311d7e1efedba753e48ccee1e9ff1d160714449bf6f85a0e3fe0784548b3c461ac5fbf28b7a1c3c83f4dff6c0d3 |
-- power_mod( |
-- 3273390607896141870013189696827599152216642046043064789483291368096133796404674554883270092325904157150886684127560071009217256545885393053328527589431, |
-- 622376668989630299558359971768444342820680304013329676986135064534413345603604938346345762083389451304101819605682193623416033951320823027994905238921170, |
-- 3351951982485649274893506249551461531869841455148098344430890360930446855046914914263767984168972974033957028381338463851007479808527777429670210341401251 |
-- ) = |
-- = 1135574785903187283000914738069914842639275616893687122668359807022003618585980215260939798952644749528921700342000274265548842002316414917974647561961683 |
-- = 15ae92ed25cdbb29458414ad1a28fa35f5bfc311d7e1efedba753e48ccee1e9ff1d160714449bf6f85a0e3fe0784548b3c461ac5fbf28b7a1c3c83f4dff6c0d3 in hexadecimal |
-- where 3351951982485649274893506249551461531869841455148097408724357100071878499222574108103974817495155088879387961281773763412796138005544310585710276679277619 is the residuum |
-------------------------------------------------- |
|
|
ctrl <= mn_read_base; |
input <= x"00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037"; |
wait for clk_period*2; |
|
ctrl <= mn_read_modulus; |
input <= x"400000000000000000000000000000000000000000000000000000000302929200000000000000000000000000000000000000000000000000005af3fbdb72a3"; |
wait for clk_period*2; |
|
ctrl <= mn_read_exponent; |
input <= x"0be21d214053f66c3e101fd875b531ecaccca3befca14d989ae2ffe4d6bbf1a3df0c694dc4c83af61ee3cf7c7bc97c9d6844d5d1fe428105082910c637c55fd2"; |
wait for clk_period*2; |
|
ctrl <= mn_read_residuum; |
input <= "00111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111001010100001100110001111100000111011101010001011101111101110101100000111111010100011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100110100000000001000000110110110010000010111000001100010111100011000101010110010110110111001110000110011"; |
wait for clk_period*2; |
|
ctrl <= mn_count_power; |
|
report "Please wait. It may take up ro few minutes..." severity note; |
|
wait until ready = '1' and clk = '0'; |
|
if output /= x"15ae92ed25cdbb29458414ad1a28fa35f5bfc311d7e1efedba753e48ccee1e9ff1d160714449bf6f85a0e3fe0784548b3c461ac5fbf28b7a1c3c83f4dff6c0d3" then |
report "RESULT MISMATCH! Test case 2 failed" severity ERROR; |
assert false severity failure; |
else |
report "Test case 2 successful" severity note; |
end if; |
|
ctrl <= mn_show_result; |
wait for clk_period*10; |
|
ctrl <= mn_prepare_for_data; |
wait for clk_period*2; |
|
assert false severity failure; |
end process; |
|
END; |
/mod_mult_exp/trunk/bench/vhdl/mod_exp/ModExp64bitTB.vhd
0,0 → 1,229
----------------------------------------------------------------------- |
---- ---- |
---- Montgomery modular multiplier and exponentiator ---- |
---- ---- |
---- This file is part of the Montgomery modular multiplier ---- |
---- and exponentiator project ---- |
---- http://opencores.org/project,mod_mult_exp ---- |
---- ---- |
---- Description: ---- |
---- This is TestBench for the Montgomery modular exponentiator ---- |
---- with the 64 bit width. ---- |
---- It takes four nubers - base, power, modulus and Montgomery ---- |
---- residuum (2^(2*word_length) mod N) as the input and results ---- |
---- the modular exponentiation A^B mod M. ---- |
---- In fact input data are read through one input controlled by ---- |
---- the ctrl input. ---- |
---- To Do: ---- |
---- ---- |
---- Author(s): ---- |
---- - Krzysztof Gajewski, gajos@opencores.org ---- |
---- k.gajewski@gmail.com ---- |
---- ---- |
----------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and-or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
----------------------------------------------------------------------- |
LIBRARY ieee; |
use work.properties.ALL; |
USE ieee.std_logic_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY ModExp64bitTB IS |
END ModExp64bitTB; |
|
ARCHITECTURE behavior OF ModExp64bitTB IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT ModExp |
PORT( |
input : in STD_LOGIC_VECTOR(63 downto 0); |
ctrl : in STD_LOGIC_VECTOR(2 downto 0); |
clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
data_in_ready : in STD_LOGIC; |
ready : out STD_LOGIC; |
output : out STD_LOGIC_VECTOR(63 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal input : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); |
signal ctrl : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); |
signal clk : STD_LOGIC := '0'; |
signal reset : STD_LOGIC := '0'; |
signal data_in_ready : STD_LOGIC := '0'; |
|
--Outputs |
signal ready : STD_LOGIC; |
signal output : STD_LOGIC_VECTOR(63 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: ModExp PORT MAP ( |
input => input, |
ctrl => ctrl, |
clk => clk, |
reset => reset, |
data_in_ready => data_in_ready, |
ready => ready, |
output => output |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '1'; |
wait for clk_period/2; |
clk <= '0'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
reset <= '1'; |
wait for 100 ns; |
reset <= '0'; |
wait for clk_period*10; |
|
---- Preparation for test case 1 ----------------- |
-- base = 816881283968894723 in decimal |
-- = 0xb56253322a18703 in hexadecimal |
-- exponent = 281474976710679 in decimal |
-- = 0x1000000000017 in hexhexadecimal |
-- modulus = 4612794175830006917 in decimal |
-- = 0x4003efdd00569c85 in hexhexadecimal |
-- expected_result = 1851187696912577658 in decimal, |
-- in hex 19b0bd66ff0c347a |
-- power_mod( |
-- 816881283968894723, |
-- 281474976710679, |
-- 4612794175830006917 |
-- ) = |
-- = 1851187696912577658 |
-- = 19b0bd66ff0c347a in hexadecimal |
-- where 1762515348761952014 is the residuum |
-------------------------------------------------- |
|
data_in_ready <= '1'; |
ctrl <= mn_read_base; |
input <= x"0b56253322a18703"; |
wait for clk_period*2; |
|
ctrl <= mn_read_modulus; |
input <= x"4003efdd00569c85"; |
wait for clk_period*2; |
|
ctrl <= mn_read_exponent; |
input <= x"0001000000000017"; |
wait for clk_period*2; |
|
ctrl <= mn_read_residuum; |
input <= "0001100001110101101101100101111100011010001000010011111100001110"; |
wait for clk_period*2; |
|
ctrl <= mn_count_power; |
|
wait until ready = '1' and clk = '0'; |
|
if output /= x"19b0bd66ff0c347a" then |
report "RESULT MISMATCH! Test case 1 failed" severity ERROR; |
assert false severity failure; |
else |
report "Test case 1 successful" severity note; |
end if; |
|
ctrl <= mn_show_result; |
wait for clk_period*10; |
|
ctrl <= mn_prepare_for_data; |
wait for clk_period*10; |
|
---- Preparation for test case 2 ----------------- |
-- base = 816881283968894722 in decimal |
-- = 0xb56253322a18702 in hexadecimal |
-- exponent = 281474976710678 in decimal |
-- = 0x1000000000016 in hexhexadecimal |
-- modulus = 4612794175830006917 in decimal |
-- = 0x4003efdd00569c85 in hexhexadecimal |
-- expected_result = 3178815025358931436 in decimal, |
-- in hex 2c1d6b6c693185ec |
-- power_mod( |
-- 816881283968894722, |
-- 281474976710678, |
-- 4612794175830006917 |
-- ) = |
-- = 3178815025358931436 |
-- = 2c1d6b6c693185ec in hexadecimal |
-- where 1762515348761952014 is the residuum |
-------------------------------------------------- |
|
ctrl <= mn_read_base; |
input <= x"0b56253322a18702"; |
wait for clk_period*2; |
|
ctrl <= mn_read_modulus; |
input <= x"4003efdd00569c85"; |
wait for clk_period*2; |
|
ctrl <= mn_read_exponent; |
input <= x"0001000000000016"; |
wait for clk_period*2; |
|
ctrl <= mn_read_residuum; |
input <= "0001100001110101101101100101111100011010001000010011111100001110"; |
wait for clk_period*2; |
|
ctrl <= mn_count_power; |
|
wait until ready = '1' and clk = '0'; |
|
if output /= x"2c1d6b6c693185ec" then |
report "RESULT MISMATCH! Test case 2 failed" severity ERROR; |
assert false severity failure; |
else |
report "Test case 2 successful" severity note; |
end if; |
|
ctrl <= mn_show_result; |
wait for clk_period*10; |
ctrl <= mn_prepare_for_data; |
wait for clk_period*10; |
|
assert false severity failure; |
end process; |
|
END; |
/mod_mult_exp/trunk/rtl/vhdl/commons/properties_32bit.vhd
62,45 → 62,35
|
type multiplier_states is (NOP, CALCULATE_START, STOP); |
|
type finalizer_states is (FIRST_RUN, NOP, |
READ_DATA_HASH_M, READ_DATA_C1, READ_DATA_N, READ_DATA_E, READ_DATA_D2, READ_DATA_CINV, |
COUNT_C2, EXP_Z_C2, SAVE_EXP_Z_C2, EXP_P_C2, SAVE_EXP_P_C2, EXP_CONTROL_C2, EXP_END_C2, SAVE_EXP_MULT_C2, |
COUNT_Cinv, MULT_CINV, SAVE_MULT_CINV, |
COUNT_C, MULT_C, SAVE_MULT_C, |
COUNT_M, EXP_Z_M, SAVE_EXP_Z_M, EXP_P_M, SAVE_EXP_P_M, EXP_CONTROL_M, EXP_END_M, SAVE_EXP_M, |
MAKE_COMPARE, COMP, COMPARE_RESULT, |
INFO_RESULT, SHOW_RESULT, FAIL_STATE); |
type exponentiator_states is (FIRST_RUN, NOP, |
READ_DATA_BASE, READ_DATA_MODULUS, READ_DATA_EXPONENT, READ_DATA_RESIDUUM, |
COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT, |
INFO_RESULT, SHOW_RESULT); |
|
type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE, |
DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE, |
TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA); |
|
---- mnemonics for finalizer |
constant mn_read_hash_m : STD_LOGIC_VECTOR(7 downto 0) := "00000001"; |
constant mn_read_c1 : STD_LOGIC_VECTOR(7 downto 0) := "00000010"; |
constant mn_read_n : STD_LOGIC_VECTOR(7 downto 0) := "00000011"; |
constant mn_read_e : STD_LOGIC_VECTOR(7 downto 0) := "00000100"; |
constant mn_read_d2 : STD_LOGIC_VECTOR(7 downto 0) := "00000110"; |
constant mn_read_cinv : STD_LOGIC_VECTOR(7 downto 0) := "00000111"; |
constant mn_finalize : STD_LOGIC_VECTOR(7 downto 0) := "00001000"; |
constant mn_show_result : STD_LOGIC_VECTOR(7 downto 0) := "00001001"; |
constant mn_show_status : STD_LOGIC_VECTOR(7 downto 0) := "00001010"; |
constant mn_prepare_for_data : STD_LOGIC_VECTOR(7 downto 0) := "00001011"; |
---- mnemonics for exponentiator |
constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000"; |
constant mn_read_modulus : STD_LOGIC_VECTOR(2 downto 0) := "001"; |
constant mn_read_exponent : STD_LOGIC_VECTOR(2 downto 0) := "010"; |
constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011"; |
constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100"; |
constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101"; |
constant mn_show_status : STD_LOGIC_VECTOR(2 downto 0) := "110"; |
constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111"; |
|
---- addresses for memory data |
constant addr_hashM : STD_LOGIC_VECTOR(3 downto 0) := "0000"; |
constant addr_c1 : STD_LOGIC_VECTOR(3 downto 0) := "0001"; |
constant addr_N : STD_LOGIC_VECTOR(3 downto 0) := "0010"; |
constant addr_E : STD_LOGIC_VECTOR(3 downto 0) := "0011"; |
constant addr_d2 : STD_LOGIC_VECTOR(3 downto 0) := "0100"; |
constant addr_c2 : STD_LOGIC_VECTOR(3 downto 0) := "0101"; |
constant addr_c : STD_LOGIC_VECTOR(3 downto 0) := "0110"; |
constant addr_hashMc : STD_LOGIC_VECTOR(3 downto 0) := "0111"; |
constant addr_cinv : STD_LOGIC_VECTOR(3 downto 0) := "1000"; |
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001"; |
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101"; |
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110"; |
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111"; |
constant addr_base : STD_LOGIC_VECTOR(3 downto 0) := "0000"; |
constant addr_modulus : STD_LOGIC_VECTOR(3 downto 0) := "0010"; |
constant addr_exponent : STD_LOGIC_VECTOR(3 downto 0) := "0100"; |
constant addr_power : STD_LOGIC_VECTOR(3 downto 0) := "0101"; |
constant addr_residuum : STD_LOGIC_VECTOR(3 downto 0) := "1000"; |
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001"; |
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101"; |
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110"; |
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111"; |
|
---- help_statuses_for_clarity |
constant stat_all_data_readed : STD_LOGIC_VECTOR(5 downto 0) := "111111"; |
/mod_mult_exp/trunk/rtl/vhdl/commons/properties_64bit.vhd
62,45 → 62,35
|
type multiplier_states is (NOP, CALCULATE_START, STOP); |
|
type finalizer_states is (FIRST_RUN, NOP, |
READ_DATA_HASH_M, READ_DATA_C1, READ_DATA_N, READ_DATA_E, READ_DATA_D2, READ_DATA_CINV, |
COUNT_C2, EXP_Z_C2, SAVE_EXP_Z_C2, EXP_P_C2, SAVE_EXP_P_C2, EXP_CONTROL_C2, EXP_END_C2, SAVE_EXP_MULT_C2, |
COUNT_Cinv, MULT_CINV, SAVE_MULT_CINV, |
COUNT_C, MULT_C, SAVE_MULT_C, |
COUNT_M, EXP_Z_M, SAVE_EXP_Z_M, EXP_P_M, SAVE_EXP_P_M, EXP_CONTROL_M, EXP_END_M, SAVE_EXP_M, |
MAKE_COMPARE, COMP, COMPARE_RESULT, |
INFO_RESULT, SHOW_RESULT, FAIL_STATE); |
type exponentiator_states is (FIRST_RUN, NOP, |
READ_DATA_BASE, READ_DATA_MODULUS, READ_DATA_EXPONENT, READ_DATA_RESIDUUM, |
COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT, |
INFO_RESULT, SHOW_RESULT); |
|
type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE, |
DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE, |
TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA); |
|
---- mnemonics for finalizer |
constant mn_read_hash_m : STD_LOGIC_VECTOR(7 downto 0) := "00000001"; |
constant mn_read_c1 : STD_LOGIC_VECTOR(7 downto 0) := "00000010"; |
constant mn_read_n : STD_LOGIC_VECTOR(7 downto 0) := "00000011"; |
constant mn_read_e : STD_LOGIC_VECTOR(7 downto 0) := "00000100"; |
constant mn_read_d2 : STD_LOGIC_VECTOR(7 downto 0) := "00000110"; |
constant mn_read_cinv : STD_LOGIC_VECTOR(7 downto 0) := "00000111"; |
constant mn_finalize : STD_LOGIC_VECTOR(7 downto 0) := "00001000"; |
constant mn_show_result : STD_LOGIC_VECTOR(7 downto 0) := "00001001"; |
constant mn_show_status : STD_LOGIC_VECTOR(7 downto 0) := "00001010"; |
constant mn_prepare_for_data : STD_LOGIC_VECTOR(7 downto 0) := "00001011"; |
---- mnemonics for exponentiator |
constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000"; |
constant mn_read_modulus : STD_LOGIC_VECTOR(2 downto 0) := "001"; |
constant mn_read_exponent : STD_LOGIC_VECTOR(2 downto 0) := "010"; |
constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011"; |
constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100"; |
constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101"; |
constant mn_show_status : STD_LOGIC_VECTOR(2 downto 0) := "110"; |
constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111"; |
|
---- addresses for memory data |
constant addr_hashM : STD_LOGIC_VECTOR(3 downto 0) := "0000"; |
constant addr_c1 : STD_LOGIC_VECTOR(3 downto 0) := "0001"; |
constant addr_N : STD_LOGIC_VECTOR(3 downto 0) := "0010"; |
constant addr_E : STD_LOGIC_VECTOR(3 downto 0) := "0011"; |
constant addr_d2 : STD_LOGIC_VECTOR(3 downto 0) := "0100"; |
constant addr_c2 : STD_LOGIC_VECTOR(3 downto 0) := "0101"; |
constant addr_c : STD_LOGIC_VECTOR(3 downto 0) := "0110"; |
constant addr_hashMc : STD_LOGIC_VECTOR(3 downto 0) := "0111"; |
constant addr_cinv : STD_LOGIC_VECTOR(3 downto 0) := "1000"; |
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001"; |
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101"; |
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110"; |
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111"; |
constant addr_base : STD_LOGIC_VECTOR(3 downto 0) := "0000"; |
constant addr_modulus : STD_LOGIC_VECTOR(3 downto 0) := "0010"; |
constant addr_exponent : STD_LOGIC_VECTOR(3 downto 0) := "0100"; |
constant addr_power : STD_LOGIC_VECTOR(3 downto 0) := "0101"; |
constant addr_residuum : STD_LOGIC_VECTOR(3 downto 0) := "1000"; |
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001"; |
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101"; |
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110"; |
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111"; |
|
---- help_statuses_for_clarity |
constant stat_all_data_readed : STD_LOGIC_VECTOR(5 downto 0) := "111111"; |
/mod_mult_exp/trunk/rtl/vhdl/commons/properties.vhd
61,45 → 61,35
|
type multiplier_states is (NOP, CALCULATE_START, STOP); |
|
type finalizer_states is (FIRST_RUN, NOP, |
READ_DATA_HASH_M, READ_DATA_C1, READ_DATA_N, READ_DATA_E, READ_DATA_D2, READ_DATA_CINV, |
COUNT_C2, EXP_Z_C2, SAVE_EXP_Z_C2, EXP_P_C2, SAVE_EXP_P_C2, EXP_CONTROL_C2, EXP_END_C2, SAVE_EXP_MULT_C2, |
COUNT_Cinv, MULT_CINV, SAVE_MULT_CINV, |
COUNT_C, MULT_C, SAVE_MULT_C, |
COUNT_M, EXP_Z_M, SAVE_EXP_Z_M, EXP_P_M, SAVE_EXP_P_M, EXP_CONTROL_M, EXP_END_M, SAVE_EXP_M, |
MAKE_COMPARE, COMP, COMPARE_RESULT, |
INFO_RESULT, SHOW_RESULT, FAIL_STATE); |
type exponentiator_states is (FIRST_RUN, NOP, |
READ_DATA_BASE, READ_DATA_MODULUS, READ_DATA_EXPONENT, READ_DATA_RESIDUUM, |
COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT, |
INFO_RESULT, SHOW_RESULT); |
|
type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE, |
DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE, |
TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA); |
|
---- mnemonics for finalizer |
constant mn_read_hash_m : STD_LOGIC_VECTOR(7 downto 0) := "00000001"; |
constant mn_read_c1 : STD_LOGIC_VECTOR(7 downto 0) := "00000010"; |
constant mn_read_n : STD_LOGIC_VECTOR(7 downto 0) := "00000011"; |
constant mn_read_e : STD_LOGIC_VECTOR(7 downto 0) := "00000100"; |
constant mn_read_d2 : STD_LOGIC_VECTOR(7 downto 0) := "00000110"; |
constant mn_read_cinv : STD_LOGIC_VECTOR(7 downto 0) := "00000111"; |
constant mn_finalize : STD_LOGIC_VECTOR(7 downto 0) := "00001000"; |
constant mn_show_result : STD_LOGIC_VECTOR(7 downto 0) := "00001001"; |
constant mn_show_status : STD_LOGIC_VECTOR(7 downto 0) := "00001010"; |
constant mn_prepare_for_data : STD_LOGIC_VECTOR(7 downto 0) := "00001011"; |
---- mnemonics for exponentiator |
constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000"; |
constant mn_read_modulus : STD_LOGIC_VECTOR(2 downto 0) := "001"; |
constant mn_read_exponent : STD_LOGIC_VECTOR(2 downto 0) := "010"; |
constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011"; |
constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100"; |
constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101"; |
constant mn_show_status : STD_LOGIC_VECTOR(2 downto 0) := "110"; |
constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111"; |
|
---- addresses for memory data |
constant addr_hashM : STD_LOGIC_VECTOR(3 downto 0) := "0000"; |
constant addr_c1 : STD_LOGIC_VECTOR(3 downto 0) := "0001"; |
constant addr_N : STD_LOGIC_VECTOR(3 downto 0) := "0010"; |
constant addr_E : STD_LOGIC_VECTOR(3 downto 0) := "0011"; |
constant addr_d2 : STD_LOGIC_VECTOR(3 downto 0) := "0100"; |
constant addr_c2 : STD_LOGIC_VECTOR(3 downto 0) := "0101"; |
constant addr_c : STD_LOGIC_VECTOR(3 downto 0) := "0110"; |
constant addr_hashMc : STD_LOGIC_VECTOR(3 downto 0) := "0111"; |
constant addr_cinv : STD_LOGIC_VECTOR(3 downto 0) := "1000"; |
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001"; |
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101"; |
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110"; |
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111"; |
constant addr_base : STD_LOGIC_VECTOR(3 downto 0) := "0000"; |
constant addr_modulus : STD_LOGIC_VECTOR(3 downto 0) := "0010"; |
constant addr_exponent : STD_LOGIC_VECTOR(3 downto 0) := "0100"; |
constant addr_power : STD_LOGIC_VECTOR(3 downto 0) := "0101"; |
constant addr_residuum : STD_LOGIC_VECTOR(3 downto 0) := "1000"; |
constant addr_one : STD_LOGIC_VECTOR(3 downto 0) := "1001"; |
constant addr_unused : STD_LOGIC_VECTOR(3 downto 0) := "1101"; |
constant addr_z : STD_LOGIC_VECTOR(3 downto 0) := "1110"; |
constant addr_p : STD_LOGIC_VECTOR(3 downto 0) := "1111"; |
|
---- help_statuses_for_clarity |
constant stat_all_data_readed : STD_LOGIC_VECTOR(5 downto 0) := "111111"; |
/mod_mult_exp/trunk/rtl/vhdl/commons/Reg.vhd
0,0 → 1,84
----------------------------------------------------------------------- |
---- ---- |
---- Montgomery modular multiplier and exponentiator ---- |
---- ---- |
---- This file is part of the Montgomery modular multiplier ---- |
---- and exponentiator project ---- |
---- http://opencores.org/project,mod_mult_exp ---- |
---- ---- |
---- Description: ---- |
---- Register - nothing special. ---- |
---- To Do: ---- |
---- ---- |
---- Author(s): ---- |
---- - Krzysztof Gajewski, gajos@opencores.org ---- |
---- k.gajewski@gmail.com ---- |
---- ---- |
----------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and-or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
----------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use work.properties.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--use IEEE.NUMERIC_STD.ALL; |
|
-- Uncomment the following library declaration if instantiating |
-- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity Reg is |
generic(word_size : integer := WORD_LENGTH); |
port( |
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0); |
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0); |
enable : in STD_LOGIC; |
clk : in STD_LOGIC; |
reset : in STD_LOGIC |
); |
end Reg; |
|
architecture Behavioral of Reg is |
|
signal reg : STD_LOGIC_VECTOR(word_size - 1 downto 0); |
|
begin |
clock : process(clk, reset) |
begin |
if (reset = '1') then |
reg <= (others => '0'); |
elsif (clk = '1' and clk'Event) then |
if (enable = '1') then |
reg <= input; |
end if; |
end if; |
end process clock; |
output <= reg; |
end Behavioral; |
|
/mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_xmdf.tcl
0,0 → 1,263
# The package naming convention is <core_name>_xmdf |
package provide blockMemory_xmdf 1.0 |
|
# This includes some utilities that support common XMDF operations |
package require utilities_xmdf |
|
# Define a namespace for this package. The name of the name space |
# is <core_name>_xmdf |
namespace eval ::blockMemory_xmdf { |
# Use this to define any statics |
} |
|
# Function called by client to rebuild the params and port arrays |
# Optional when the use context does not require the param or ports |
# arrays to be available. |
proc ::blockMemory_xmdf::xmdfInit { instance } { |
# Variable containing name of library into which module is compiled |
# Recommendation: <module_name> |
# Required |
utilities_xmdf::xmdfSetData $instance Module Attributes Name blockMemory |
} |
# ::blockMemory_xmdf::xmdfInit |
|
# Function called by client to fill in all the xmdf* data variables |
# based on the current settings of the parameters |
proc ::blockMemory_xmdf::xmdfApplyParams { instance } { |
|
set fcount 0 |
# Array containing libraries that are assumed to exist |
# Examples include unisim and xilinxcorelib |
# Optional |
# In this example, we assume that the unisim library will |
# be available to the simulation and synthesis tool |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library |
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/blk_mem_gen_v7_1_readme.txt |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_ds512.pdf |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_v7_1_vinfo.html |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.ucf |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.xdc |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_prod.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.prj |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.scr |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/addr_gen.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_synth.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_tb.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_stim_gen.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_tb_pkg.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/checker.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/data_gen.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simcmds.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_isim.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.do |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_ncsim.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_vcs.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/ucli_commands.key |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/vcs_session.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_mti.do |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_ncsim.sv |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/random.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simcmds.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_isim.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.bat |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.do |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_ncsim.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_vcs.sh |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/ucli_commands.key |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/vcs_session.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_mti.do |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_ncsim.sv |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.asy |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.ngc |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.sym |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vhd |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vho |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.xco |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory_xmdf.tcl |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log |
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView |
incr fcount |
|
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blockMemory |
incr fcount |
|
} |
|
# ::gen_comp_name_xmdf::xmdfApplyParams |
/mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_exdes.ucf
0,0 → 1,57
################################################################################ |
# |
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. |
# |
# This file contains confidential and proprietary information |
# of Xilinx, Inc. and is protected under U.S. and |
# international copyright and other intellectual property |
# laws. |
# |
# DISCLAIMER |
# This disclaimer is not a license and does not grant any |
# rights to the materials distributed herewith. Except as |
# otherwise provided in a valid license issued to you by |
# Xilinx, and to the maximum extent permitted by applicable |
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
# (2) Xilinx shall not be liable (whether in contract or tort, |
# including negligence, or under any other theory of |
# liability) for any loss or damage of any kind or nature |
# related to, arising under or in connection with these |
# materials, including for any direct, or any indirect, |
# special, incidental, or consequential loss or damage |
# (including loss of data, profits, goodwill, or any type of |
# loss or damage suffered as a result of any action brought |
# by a third party) even if such damage or loss was |
# reasonably foreseeable or Xilinx had been advised of the |
# possibility of the same. |
# |
# CRITICAL APPLICATIONS |
# Xilinx products are not designed or intended to be fail- |
# safe, or for use in any application requiring fail-safe |
# performance, such as life-support or safety devices or |
# systems, Class III medical devices, nuclear facilities, |
# applications related to the deployment of airbags, or any |
# other applications that could lead to death, personal |
# injury, or severe property or environmental damage |
# (individually and collectively, "Critical |
# Applications"). Customer assumes the sole risk and |
# liability of any use of Xilinx products in Critical |
# Applications, subject only to applicable laws and |
# regulations governing limitations on product liability. |
# |
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
# PART OF THIS FILE AT ALL TIMES. |
# |
################################################################################ |
|
# Tx Core Period Constraint. This constraint can be modified, and is |
# valid as long as it is met after place and route. |
NET "CLKA" TNM_NET = "CLKA"; |
|
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; |
|
################################################################################ |
/mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_prod.vhd
0,0 → 1,270
|
|
|
|
|
|
|
|
-------------------------------------------------------------------------------- |
-- |
-- BLK MEM GEN v7.1 Core - Top-level wrapper |
-- |
-------------------------------------------------------------------------------- |
-- |
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. |
-- |
-- This file contains confidential and proprietary information |
-- of Xilinx, Inc. and is protected under U.S. and |
-- international copyright and other intellectual property |
-- laws. |
-- |
-- DISCLAIMER |
-- This disclaimer is not a license and does not grant any |
-- rights to the materials distributed herewith. Except as |
-- otherwise provided in a valid license issued to you by |
-- Xilinx, and to the maximum extent permitted by applicable |
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
-- (2) Xilinx shall not be liable (whether in contract or tort, |
-- including negligence, or under any other theory of |
-- liability) for any loss or damage of any kind or nature |
-- related to, arising under or in connection with these |
-- materials, including for any direct, or any indirect, |
-- special, incidental, or consequential loss or damage |
-- (including loss of data, profits, goodwill, or any type of |
-- loss or damage suffered as a result of any action brought |
-- by a third party) even if such damage or loss was |
-- reasonably foreseeable or Xilinx had been advised of the |
-- possibility of the same. |
-- |
-- CRITICAL APPLICATIONS |
-- Xilinx products are not designed or intended to be fail- |
-- safe, or for use in any application requiring fail-safe |
-- performance, such as life-support or safety devices or |
-- systems, Class III medical devices, nuclear facilities, |
-- applications related to the deployment of airbags, or any |
-- other applications that could lead to death, personal |
-- injury, or severe property or environmental damage |
-- (individually and collectively, "Critical |
-- Applications"). Customer assumes the sole risk and |
-- liability of any use of Xilinx products in Critical |
-- Applications, subject only to applicable laws and |
-- regulations governing limitations on product liability. |
-- |
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
-- PART OF THIS FILE AT ALL TIMES. |
-- |
-------------------------------------------------------------------------------- |
-- |
-- Filename: blockMemory_prod.vhd |
-- |
-- Description: |
-- This is the top-level BMG wrapper (over BMG core). |
-- |
-------------------------------------------------------------------------------- |
-- Author: IP Solutions Division |
-- |
-- History: August 31, 2005 - First Release |
-------------------------------------------------------------------------------- |
-- |
-- Configured Core Parameter Values: |
-- (Refer to the SIM Parameters table in the datasheet for more information on |
-- the these parameters.) |
-- C_FAMILY : spartan3e |
-- C_XDEVICEFAMILY : spartan3e |
-- C_INTERFACE_TYPE : 0 |
-- C_ENABLE_32BIT_ADDRESS : 0 |
-- C_AXI_TYPE : 1 |
-- C_AXI_SLAVE_TYPE : 0 |
-- C_AXI_ID_WIDTH : 4 |
-- C_MEM_TYPE : 0 |
-- C_BYTE_SIZE : 9 |
-- C_ALGORITHM : 0 |
-- C_PRIM_TYPE : 6 |
-- C_LOAD_INIT_FILE : 0 |
-- C_INIT_FILE_NAME : no_coe_file_loaded |
-- C_USE_DEFAULT_DATA : 0 |
-- C_DEFAULT_DATA : 0 |
-- C_RST_TYPE : SYNC |
-- C_HAS_RSTA : 1 |
-- C_RST_PRIORITY_A : CE |
-- C_RSTRAM_A : 0 |
-- C_INITA_VAL : 0 |
-- C_HAS_ENA : 0 |
-- C_HAS_REGCEA : 0 |
-- C_USE_BYTE_WEA : 0 |
-- C_WEA_WIDTH : 1 |
-- C_WRITE_MODE_A : READ_FIRST |
-- C_WRITE_WIDTH_A : 32 |
-- C_READ_WIDTH_A : 32 |
-- C_WRITE_DEPTH_A : 16 |
-- C_READ_DEPTH_A : 16 |
-- C_ADDRA_WIDTH : 4 |
-- C_HAS_RSTB : 0 |
-- C_RST_PRIORITY_B : CE |
-- C_RSTRAM_B : 0 |
-- C_INITB_VAL : 0 |
-- C_HAS_ENB : 0 |
-- C_HAS_REGCEB : 0 |
-- C_USE_BYTE_WEB : 0 |
-- C_WEB_WIDTH : 1 |
-- C_WRITE_MODE_B : WRITE_FIRST |
-- C_WRITE_WIDTH_B : 32 |
-- C_READ_WIDTH_B : 32 |
-- C_WRITE_DEPTH_B : 16 |
-- C_READ_DEPTH_B : 16 |
-- C_ADDRB_WIDTH : 4 |
-- C_HAS_MEM_OUTPUT_REGS_A : 0 |
-- C_HAS_MEM_OUTPUT_REGS_B : 0 |
-- C_HAS_MUX_OUTPUT_REGS_A : 0 |
-- C_HAS_MUX_OUTPUT_REGS_B : 0 |
-- C_HAS_SOFTECC_INPUT_REGS_A : 0 |
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 |
-- C_MUX_PIPELINE_STAGES : 0 |
-- C_USE_ECC : 0 |
-- C_USE_SOFTECC : 0 |
-- C_HAS_INJECTERR : 0 |
-- C_SIM_COLLISION_CHECK : ALL |
-- C_COMMON_CLK : 0 |
-- C_DISABLE_WARN_BHV_COLL : 0 |
-- C_DISABLE_WARN_BHV_RANGE : 0 |
|
-------------------------------------------------------------------------------- |
-- Library Declarations |
-------------------------------------------------------------------------------- |
|
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.STD_LOGIC_ARITH.ALL; |
USE IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
LIBRARY UNISIM; |
USE UNISIM.VCOMPONENTS.ALL; |
|
-------------------------------------------------------------------------------- |
-- Entity Declaration |
-------------------------------------------------------------------------------- |
ENTITY blockMemory_prod IS |
PORT ( |
--Port A |
CLKA : IN STD_LOGIC; |
RSTA : IN STD_LOGIC; --opt port |
ENA : IN STD_LOGIC; --optional port |
REGCEA : IN STD_LOGIC; --optional port |
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
--Port B |
CLKB : IN STD_LOGIC; |
RSTB : IN STD_LOGIC; --opt port |
ENB : IN STD_LOGIC; --optional port |
REGCEB : IN STD_LOGIC; --optional port |
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
--ECC |
INJECTSBITERR : IN STD_LOGIC; --optional port |
INJECTDBITERR : IN STD_LOGIC; --optional port |
SBITERR : OUT STD_LOGIC; --optional port |
DBITERR : OUT STD_LOGIC; --optional port |
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port |
-- AXI BMG Input and Output Port Declarations |
|
-- AXI Global Signals |
S_ACLK : IN STD_LOGIC; |
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
S_AXI_AWVALID : IN STD_LOGIC; |
S_AXI_AWREADY : OUT STD_LOGIC; |
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
S_AXI_WLAST : IN STD_LOGIC; |
S_AXI_WVALID : IN STD_LOGIC; |
S_AXI_WREADY : OUT STD_LOGIC; |
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); |
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
S_AXI_BVALID : OUT STD_LOGIC; |
S_AXI_BREADY : IN STD_LOGIC; |
|
-- AXI Full/Lite Slave Read (Write side) |
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
S_AXI_ARVALID : IN STD_LOGIC; |
S_AXI_ARREADY : OUT STD_LOGIC; |
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); |
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
S_AXI_RLAST : OUT STD_LOGIC; |
S_AXI_RVALID : OUT STD_LOGIC; |
S_AXI_RREADY : IN STD_LOGIC; |
|
-- AXI Full/Lite Sideband Signals |
S_AXI_INJECTSBITERR : IN STD_LOGIC; |
S_AXI_INJECTDBITERR : IN STD_LOGIC; |
S_AXI_SBITERR : OUT STD_LOGIC; |
S_AXI_DBITERR : OUT STD_LOGIC; |
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
S_ARESETN : IN STD_LOGIC |
|
|
); |
|
END blockMemory_prod; |
|
|
ARCHITECTURE xilinx OF blockMemory_prod IS |
|
COMPONENT blockMemory_exdes IS |
PORT ( |
--Port A |
RSTA : IN STD_LOGIC; --opt port |
|
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
CLKA : IN STD_LOGIC |
|
|
|
|
); |
END COMPONENT; |
|
BEGIN |
|
bmg0 : blockMemory_exdes |
PORT MAP ( |
--Port A |
RSTA => RSTA, |
|
WEA => WEA, |
ADDRA => ADDRA, |
|
DINA => DINA, |
|
DOUTA => DOUTA, |
|
CLKA => CLKA |
|
|
|
); |
END xilinx; |
/mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_exdes.xdc
0,0 → 1,54
################################################################################ |
# |
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. |
# |
# This file contains confidential and proprietary information |
# of Xilinx, Inc. and is protected under U.S. and |
# international copyright and other intellectual property |
# laws. |
# |
# DISCLAIMER |
# This disclaimer is not a license and does not grant any |
# rights to the materials distributed herewith. Except as |
# otherwise provided in a valid license issued to you by |
# Xilinx, and to the maximum extent permitted by applicable |
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
# (2) Xilinx shall not be liable (whether in contract or tort, |
# including negligence, or under any other theory of |
# liability) for any loss or damage of any kind or nature |
# related to, arising under or in connection with these |
# materials, including for any direct, or any indirect, |
# special, incidental, or consequential loss or damage |
# (including loss of data, profits, goodwill, or any type of |
# loss or damage suffered as a result of any action brought |
# by a third party) even if such damage or loss was |
# reasonably foreseeable or Xilinx had been advised of the |
# possibility of the same. |
# |
# CRITICAL APPLICATIONS |
# Xilinx products are not designed or intended to be fail- |
# safe, or for use in any application requiring fail-safe |
# performance, such as life-support or safety devices or |
# systems, Class III medical devices, nuclear facilities, |
# applications related to the deployment of airbags, or any |
# other applications that could lead to death, personal |
# injury, or severe property or environmental damage |
# (individually and collectively, "Critical |
# Applications"). Customer assumes the sole risk and |
# liability of any use of Xilinx products in Critical |
# Applications, subject only to applicable laws and |
# regulations governing limitations on product liability. |
# |
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
# PART OF THIS FILE AT ALL TIMES. |
# |
################################################################################ |
|
# Core Period Constraint. This constraint can be modified, and is |
# valid as long as it is met after place and route. |
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] |
################################################################################ |
/mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_exdes.vhd
0,0 → 1,166
|
|
|
|
|
|
|
-------------------------------------------------------------------------------- |
-- |
-- BLK MEM GEN v7.1 Core - Top-level core wrapper |
-- |
-------------------------------------------------------------------------------- |
-- |
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. |
-- |
-- This file contains confidential and proprietary information |
-- of Xilinx, Inc. and is protected under U.S. and |
-- international copyright and other intellectual property |
-- laws. |
-- |
-- DISCLAIMER |
-- This disclaimer is not a license and does not grant any |
-- rights to the materials distributed herewith. Except as |
-- otherwise provided in a valid license issued to you by |
-- Xilinx, and to the maximum extent permitted by applicable |
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
-- (2) Xilinx shall not be liable (whether in contract or tort, |
-- including negligence, or under any other theory of |
-- liability) for any loss or damage of any kind or nature |
-- related to, arising under or in connection with these |
-- materials, including for any direct, or any indirect, |
-- special, incidental, or consequential loss or damage |
-- (including loss of data, profits, goodwill, or any type of |
-- loss or damage suffered as a result of any action brought |
-- by a third party) even if such damage or loss was |
-- reasonably foreseeable or Xilinx had been advised of the |
-- possibility of the same. |
-- |
-- CRITICAL APPLICATIONS |
-- Xilinx products are not designed or intended to be fail- |
-- safe, or for use in any application requiring fail-safe |
-- performance, such as life-support or safety devices or |
-- systems, Class III medical devices, nuclear facilities, |
-- applications related to the deployment of airbags, or any |
-- other applications that could lead to death, personal |
-- injury, or severe property or environmental damage |
-- (individually and collectively, "Critical |
-- Applications"). Customer assumes the sole risk and |
-- liability of any use of Xilinx products in Critical |
-- Applications, subject only to applicable laws and |
-- regulations governing limitations on product liability. |
-- |
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
-- PART OF THIS FILE AT ALL TIMES. |
|
-------------------------------------------------------------------------------- |
-- |
-- Filename: blockMemory_exdes.vhd |
-- |
-- Description: |
-- This is the actual BMG core wrapper. |
-- |
-------------------------------------------------------------------------------- |
-- Author: IP Solutions Division |
-- |
-- History: August 31, 2005 - First Release |
-------------------------------------------------------------------------------- |
-- |
-------------------------------------------------------------------------------- |
-- Library Declarations |
-------------------------------------------------------------------------------- |
|
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.STD_LOGIC_ARITH.ALL; |
USE IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
LIBRARY UNISIM; |
USE UNISIM.VCOMPONENTS.ALL; |
|
-------------------------------------------------------------------------------- |
-- Entity Declaration |
-------------------------------------------------------------------------------- |
ENTITY blockMemory_exdes IS |
PORT ( |
--Inputs - Port A |
RSTA : IN STD_LOGIC; --opt port |
|
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
CLKA : IN STD_LOGIC |
|
|
); |
|
END blockMemory_exdes; |
|
|
ARCHITECTURE xilinx OF blockMemory_exdes IS |
|
COMPONENT BUFG IS |
PORT ( |
I : IN STD_ULOGIC; |
O : OUT STD_ULOGIC |
); |
END COMPONENT; |
|
COMPONENT blockMemory IS |
PORT ( |
--Port A |
RSTA : IN STD_LOGIC; --opt port |
|
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
CLKA : IN STD_LOGIC |
|
|
|
); |
END COMPONENT; |
|
SIGNAL CLKA_buf : STD_LOGIC; |
SIGNAL CLKB_buf : STD_LOGIC; |
SIGNAL S_ACLK_buf : STD_LOGIC; |
|
BEGIN |
|
bufg_A : BUFG |
PORT MAP ( |
I => CLKA, |
O => CLKA_buf |
); |
|
|
|
bmg0 : blockMemory |
PORT MAP ( |
--Port A |
RSTA => RSTA, |
|
WEA => WEA, |
ADDRA => ADDRA, |
|
DINA => DINA, |
|
DOUTA => DOUTA, |
|
CLKA => CLKA_buf |
|
|
); |
|
END xilinx; |
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/random.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/random.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/random.vhd (revision 5)
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+-- Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+ GENERIC ( WIDTH : INTEGER := 32;
+ SEED : INTEGER :=2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+ PROCESS(CLK)
+ VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ VARIABLE TEMP : STD_LOGIC := '0';
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ ELSE
+ IF(EN = '1') THEN
+ TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+ RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+ RAND_TEMP(0) := TEMP;
+ END IF;
+ END IF;
+ END IF;
+ RANDOM_NUM <= RAND_TEMP;
+ END PROCESS;
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/vcs_session.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/vcs_session.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/vcs_session.tcl (revision 5)
@@ -0,0 +1,83 @@
+
+
+
+
+
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG core Demo Testbench
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+# This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+ gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create blockMemory_Group
+gui_list_add_group -id Wave.1 {blockMemory_Group}
+
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simcmds.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simcmds.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simcmds.tcl (revision 5)
@@ -0,0 +1,63 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+
+
+wcfg new
+isim set radix hex
+wave add /blockMemory_tb/status
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA
+run all
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.bat (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_ncsim.sv
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_ncsim.sv (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_ncsim.sv (revision 5)
@@ -0,0 +1,21 @@
+
+
+
+
+
+
+
+
+
+window new WaveWindow -name "Waves for BMG Example Design"
+waveform using "Waves for BMG Example Design"
+
+ waveform add -signals /blockMemory_tb/status
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+console submit -using simulator -wait no "run"
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/ucli_commands.key
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/ucli_commands.key (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/ucli_commands.key (revision 5)
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add blockMemory_tb
+run
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.sh (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_ncsim.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_ncsim.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_ncsim.sh (revision 5)
@@ -0,0 +1,70 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+
+mkdir work
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+ncvhdl -v93 -work work ../../../blockMemory.vhd \
+ ../../example_design/blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work ../random.vhd
+ncvhdl -v93 -work work ../data_gen.vhd
+ncvhdl -v93 -work work ../addr_gen.vhd
+ncvhdl -v93 -work work ../checker.vhd
+ncvhdl -v93 -work work ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work ../blockMemory_synth.vhd
+ncvhdl -v93 -work work ../blockMemory_tb.vhd
+
+echo "Elaborating Design"
+ncelab -access +rwc work.blockMemory_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.blockMemory_tb
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_vcs.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_vcs.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_vcs.sh (revision 5)
@@ -0,0 +1,69 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhdlan ../../../blockMemory.vhd
+vhdlan ../../example_design/blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan ../bmg_tb_pkg.vhd
+vhdlan ../random.vhd
+vhdlan ../data_gen.vhd
+vhdlan ../addr_gen.vhd
+vhdlan ../checker.vhd
+vhdlan ../bmg_stim_gen.vhd
+vhdlan ../blockMemory_synth.vhd
+vhdlan ../blockMemory_tb.vhd
+
+echo "Elaborating Design"
+vcs +vcs+lic+wait -debug blockMemory_tb
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_isim.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_isim.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_isim.bat (revision 5)
@@ -0,0 +1,68 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+::
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+::
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+::
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+::
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::--------------------------------------------------------------------------------
+
+
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhpcomp -work work ..\..\..\blockMemory.vhd
+vhpcomp -work work ..\..\example_design\blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work ..\bmg_tb_pkg.vhd
+vhpcomp -work work ..\random.vhd
+vhpcomp -work work ..\data_gen.vhd
+vhpcomp -work work ..\addr_gen.vhd
+vhpcomp -work work ..\checker.vhd
+vhpcomp -work work ..\bmg_stim_gen.vhd
+vhpcomp -work work ..\blockMemory_synth.vhd
+vhpcomp -work work ..\blockMemory_tb.vhd
+
+fuse work.blockMemory_tb -L unisims -L xilinxcorelib -o blockMemory_tb.exe
+
+
+.\blockMemory_tb.exe -gui -tclbatch simcmds.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_mti.do (revision 5)
@@ -0,0 +1,36 @@
+
+
+
+
+
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+ add wave -noupdate /blockMemory_tb/status
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.do (revision 5)
@@ -0,0 +1,74 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+ vlib work
+vmap work work
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vcom -work work ../../../blockMemory.vhd \
+ ../../example_design/blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work ../bmg_tb_pkg.vhd
+vcom -work work ../random.vhd
+vcom -work work ../data_gen.vhd
+vcom -work work ../addr_gen.vhd
+vcom -work work ../checker.vhd
+vcom -work work ../bmg_stim_gen.vhd
+vcom -work work ../blockMemory_synth.vhd
+vcom -work work ../blockMemory_tb.vhd
+
+vsim -novopt -t ps -L XilinxCoreLib -L unisim work.blockMemory_tb
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/data_gen.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/data_gen.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/data_gen.vhd (revision 5)
@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Data Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: data_gen.vhd
+--
+-- Description:
+-- Data Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY DATA_GEN IS
+ GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
+ DOUT_WIDTH : INTEGER := 32;
+ DATA_PART_CNT : INTEGER := 1;
+ SEED : INTEGER := 2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END DATA_GEN;
+
+ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
+ CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
+ SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+ SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
+ SIGNAL LOCAL_CNT : INTEGER :=1;
+ SIGNAL DATA_GEN_I : STD_LOGIC :='0';
+BEGIN
+
+ LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
+ DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
+ DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE (CLK)) THEN
+ IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
+ LOCAL_CNT <=1;
+ ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
+ IF(LOCAL_CNT = 1) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+ RAND_GEN_INST:ENTITY work.RANDOM
+ GENERIC MAP(
+ WIDTH => 8,
+ SEED => (SEED+N)
+ )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DATA_GEN_I,
+ RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
+ );
+ END GENERATE RAND_GEN;
+
+END ARCHITECTURE;
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/addr_gen.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/addr_gen.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/addr_gen.vhd (revision 5)
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+-- Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+ GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
+ RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+ RST_INC : INTEGER := 0);
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ LOAD :IN STD_LOGIC;
+ LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
+ ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
+ );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+ SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+ ADDR_OUT <= ADDR_TEMP;
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ IF(EN='1') THEN
+ IF(LOAD='1') THEN
+ ADDR_TEMP <=LOAD_VALUE;
+ ELSE
+ IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ ADDR_TEMP <= ADDR_TEMP + '1';
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/checker.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/checker.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/checker.vhd (revision 5)
@@ -0,0 +1,161 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Checker
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: checker.vhd
+--
+-- Description:
+-- Checker
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY CHECKER IS
+ GENERIC ( WRITE_WIDTH : INTEGER :=32;
+ READ_WIDTH : INTEGER :=32
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
+ STATUS : OUT STD_LOGIC:= '0'
+ );
+END CHECKER;
+
+ARCHITECTURE CHECKER_ARCH OF CHECKER IS
+ SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL EN_R : STD_LOGIC := '0';
+ SIGNAL EN_2R : STD_LOGIC := '0';
+--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
+--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
+--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
+ CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
+ CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
+ SIGNAL ERR_HOLD : STD_LOGIC :='0';
+ SIGNAL ERR_DET : STD_LOGIC :='0';
+BEGIN
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST= '1') THEN
+ EN_R <= '0';
+ EN_2R <= '0';
+ DATA_IN_R <= (OTHERS=>'0');
+ ELSE
+ EN_R <= EN;
+ EN_2R <= EN_R;
+ DATA_IN_R <= DATA_IN;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
+ DOUT_WIDTH => READ_WIDTH,
+ DATA_PART_CNT => DATA_PART_CNT,
+ SEED => 2
+ )
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ EN => EN_2R,
+ DATA_OUT => EXPECTED_DATA
+ );
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(EN_2R='1') THEN
+ IF(EXPECTED_DATA = DATA_IN_R) THEN
+ ERR_DET<='0';
+ ELSE
+ ERR_DET<= '1';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLK,RST)
+ BEGIN
+ IF(RST='1') THEN
+ ERR_HOLD <= '0';
+ ELSIF(RISING_EDGE(CLK)) THEN
+ ERR_HOLD <= ERR_HOLD OR ERR_DET ;
+ END IF;
+ END PROCESS;
+
+ STATUS <= ERR_HOLD;
+
+END ARCHITECTURE;
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/vcs_session.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/vcs_session.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/vcs_session.tcl (revision 5)
@@ -0,0 +1,83 @@
+
+
+
+
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG Generator v8.4 Core Demo Testbench
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+# This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+ gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create blockMemory_Group
+gui_list_add_group -id Wave.1 {blockMemory_Group}
+
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simcmds.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simcmds.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simcmds.tcl (revision 5)
@@ -0,0 +1,63 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+
+
+wcfg new
+isim set radix hex
+wave add /blockMemory_tb/status
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA
+run all
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.bat (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_ncsim.sv
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_ncsim.sv (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_ncsim.sv (revision 5)
@@ -0,0 +1,20 @@
+
+
+
+
+
+
+
+
+window new WaveWindow -name "Waves for BMG Example Design"
+waveform using "Waves for BMG Example Design"
+
+
+ waveform add -signals /blockMemory_tb/status
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+console submit -using simulator -wait no "run"
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/ucli_commands.key
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/ucli_commands.key (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/ucli_commands.key (revision 5)
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add blockMemory_tb
+run
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.sh (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_ncsim.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_ncsim.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_ncsim.sh (revision 5)
@@ -0,0 +1,78 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+mkdir work
+
+
+ncvhdl -v93 -work work ../../implement/results/routed.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work ../random.vhd
+ncvhdl -v93 -work work ../data_gen.vhd
+ncvhdl -v93 -work work ../addr_gen.vhd
+ncvhdl -v93 -work work ../checker.vhd
+ncvhdl -v93 -work work ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work ../blockMemory_synth.vhd
+ncvhdl -v93 -work work ../blockMemory_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :blockMemory_synth_inst:BMG_PORT,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+
+echo "Elaborating Design"
+ncelab -access +rwc -sdf_cmd_file sdf.cmd $work.blockMemory_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.blockMemory_tb
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_vcs.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_vcs.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_vcs.sh (revision 5)
@@ -0,0 +1,70 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhdlan ../../implement/results/routed.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan ../bmg_tb_pkg.vhd
+vhdlan ../random.vhd
+vhdlan ../data_gen.vhd
+vhdlan ../addr_gen.vhd
+vhdlan ../checker.vhd
+vhdlan ../bmg_stim_gen.vhd
+vhdlan ../blockMemory_synth.vhd
+vhdlan ../blockMemory_tb.vhd
+
+
+echo "Elaborating Design"
+vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_isim.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_isim.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_isim.bat (revision 5)
@@ -0,0 +1,67 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+::
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+::
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+::
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+::
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::--------------------------------------------------------------------------------
+
+
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhpcomp -work work ..\..\implement\results\routed.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work ..\bmg_tb_pkg.vhd
+vhpcomp -work work ..\random.vhd
+vhpcomp -work work ..\data_gen.vhd
+vhpcomp -work work ..\addr_gen.vhd
+vhpcomp -work work ..\checker.vhd
+vhpcomp -work work ..\bmg_stim_gen.vhd
+vhpcomp -work work ..\blockMemory_synth.vhd
+vhpcomp -work work ..\blockMemory_tb.vhd
+
+
+ fuse -L simprim work.blockMemory_tb -o blockMemory_tb.exe
+
+.\blockMemory_tb.exe -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_mti.do (revision 5)
@@ -0,0 +1,36 @@
+
+
+
+
+
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+
+ add wave -noupdate /blockMemory_tb/status
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.do (revision 5)
@@ -0,0 +1,75 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+
+vlib work
+vmap work work
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vcom -work work ../../implement/results/routed.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work ../bmg_tb_pkg.vhd
+vcom -work work ../random.vhd
+vcom -work work ../data_gen.vhd
+vcom -work work ../addr_gen.vhd
+vcom -work work ../checker.vhd
+vcom -work work ../bmg_stim_gen.vhd
+vcom -work work ../blockMemory_synth.vhd
+vcom -work work ../blockMemory_tb.vhd
+
+ vsim -novopt -t ps -L simprim +transport_int_delays -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=../../implement/results/routed.sdf $work.blockMemory_tb -novopt
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_synth.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_synth.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_synth.vhd (revision 5)
@@ -0,0 +1,289 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: blockMemory_synth.vhd
+--
+-- Description:
+-- Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY blockMemory_synth IS
+PORT(
+ CLK_IN : IN STD_LOGIC;
+ RESET_IN : IN STD_LOGIC;
+ STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
+ );
+END ENTITY;
+
+ARCHITECTURE blockMemory_synth_ARCH OF blockMemory_synth IS
+
+
+COMPONENT blockMemory_exdes
+ PORT (
+ --Inputs - Port A
+ RSTA : IN STD_LOGIC; --opt port
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ CLKA : IN STD_LOGIC
+
+
+ );
+
+END COMPONENT;
+
+
+ SIGNAL CLKA: STD_LOGIC := '0';
+ SIGNAL RSTA: STD_LOGIC := '0';
+ SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL CHECKER_EN : STD_LOGIC:='0';
+ SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+ SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+ SIGNAL clk_in_i: STD_LOGIC;
+
+ SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+ SIGNAL ITER_R0 : STD_LOGIC := '0';
+ SIGNAL ITER_R1 : STD_LOGIC := '0';
+ SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+ SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+ BEGIN
+
+-- clk_buf: bufg
+-- PORT map(
+-- i => CLK_IN,
+-- o => clk_in_i
+-- );
+ clk_in_i <= CLK_IN;
+ CLKA <= clk_in_i;
+
+ RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+ PROCESS(clk_in_i)
+ BEGIN
+ IF(RISING_EDGE(clk_in_i)) THEN
+ RESET_SYNC_R1 <= RESET_IN;
+ RESET_SYNC_R2 <= RESET_SYNC_R1;
+ RESET_SYNC_R3 <= RESET_SYNC_R2;
+ END IF;
+ END PROCESS;
+
+
+PROCESS(CLKA)
+BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ISSUE_FLAG_STATUS<= (OTHERS => '0');
+ ELSE
+ ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+ END IF;
+ END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+ BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
+ GENERIC MAP (
+ WRITE_WIDTH => 32,
+ READ_WIDTH => 32 )
+ PORT MAP (
+ CLK => CLKA,
+ RST => RSTA,
+ EN => CHECKER_EN_R,
+ DATA_IN => DOUTA,
+ STATUS => ISSUE_FLAG(0)
+ );
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RSTA='1') THEN
+ CHECKER_EN_R <= '0';
+ ELSE
+ CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+ PORT MAP(
+ CLK => clk_in_i,
+ RST => RSTA,
+ ADDRA => ADDRA,
+ DINA => DINA,
+ WEA => WEA,
+ CHECK_DATA => CHECKER_EN
+ );
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STATUS(8) <= '0';
+ iter_r2 <= '0';
+ iter_r1 <= '0';
+ iter_r0 <= '0';
+ ELSE
+ STATUS(8) <= iter_r2;
+ iter_r2 <= iter_r1;
+ iter_r1 <= iter_r0;
+ iter_r0 <= STIMULUS_FLOW(8);
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STIMULUS_FLOW <= (OTHERS => '0');
+ ELSIF(WEA(0)='1') THEN
+ STIMULUS_FLOW <= STIMULUS_FLOW+1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ WEA_R <= (OTHERS=>'0') AFTER 50 ns;
+ DINA_R <= (OTHERS=>'0') AFTER 50 ns;
+
+
+ ELSE
+ WEA_R <= WEA AFTER 50 ns;
+ DINA_R <= DINA AFTER 50 ns;
+
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+ ELSE
+ ADDRA_R <= ADDRA AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_PORT: blockMemory_exdes PORT MAP (
+ --Port A
+ RSTA => RSTA,
+ WEA => WEA_R,
+ ADDRA => ADDRA_R,
+ DINA => DINA_R,
+ DOUTA => DOUTA,
+ CLKA => CLKA
+
+ );
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_tb.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_tb.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_tb.vhd (revision 5)
@@ -0,0 +1,129 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: blockMemory_tb.vhd
+-- Description:
+-- Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY blockMemory_tb IS
+END ENTITY;
+
+
+ARCHITECTURE blockMemory_tb_ARCH OF blockMemory_tb IS
+ SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL CLK : STD_LOGIC := '1';
+ SIGNAL RESET : STD_LOGIC;
+
+ BEGIN
+
+
+ CLK_GEN: PROCESS BEGIN
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ END PROCESS;
+
+ RST_GEN: PROCESS BEGIN
+ RESET <= '1';
+ WAIT FOR 1000 NS;
+ RESET <= '0';
+ WAIT;
+ END PROCESS;
+
+
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+-- ASSERT FALSE
+-- REPORT "END SIMULATION TIME REACHED"
+-- SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+ WAIT UNTIL STATUS(8)='1';
+ IF( STATUS(7 downto 0)/="0") THEN
+ ASSERT false
+ REPORT "Simulation Failed"
+ SEVERITY FAILURE;
+ ELSE
+ ASSERT false
+ REPORT "Simulation Complete"
+ SEVERITY FAILURE;
+ END IF;
+END PROCESS;
+
+ blockMemory_synth_inst:ENTITY work.blockMemory_synth
+ PORT MAP(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+ STATUS => STATUS
+ );
+
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_stim_gen.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_stim_gen.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_stim_gen.vhd (revision 5)
@@ -0,0 +1,243 @@
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Stimulus Generator For Single Port Ram
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+-- Stimulus Generation For SRAM
+-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
+-- simulation ends
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC_SRAM IS
+ PORT(
+ Q : OUT STD_LOGIC;
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ D : IN STD_LOGIC
+ );
+END REGISTER_LOGIC_SRAM;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
+ SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+ Q <= Q_O;
+ FF_BEH: PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST ='1') THEN
+ Q_O <= '0';
+ ELSE
+ Q_O <= D;
+ END IF;
+ END IF;
+ END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
+ CHECK_DATA: OUT STD_LOGIC:='0'
+ );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+ CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
+ SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DO_WRITE : STD_LOGIC := '0';
+ SIGNAL DO_READ : STD_LOGIC := '0';
+ SIGNAL COUNT_NO : INTEGER :=0;
+ SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
+BEGIN
+ WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
+ READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
+ ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
+ DINA <= DINA_INT ;
+
+ CHECK_DATA <= DO_READ;
+
+RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 16
+ )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DO_READ,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => READ_ADDR
+ );
+
+WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 16 )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DO_WRITE,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => WRITE_ADDR
+ );
+
+WR_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP (
+ DATA_GEN_WIDTH => 32,
+ DOUT_WIDTH => 32,
+ DATA_PART_CNT => DATA_PART_CNT_A,
+ SEED => 2
+ )
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ EN => DO_WRITE,
+ DATA_OUT => DINA_INT
+ );
+
+WR_RD_PROCESS: PROCESS (CLK)
+BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ DO_WRITE <= '0';
+ DO_READ <= '0';
+ COUNT_NO <= 0 ;
+ ELSIF(COUNT_NO < 4) THEN
+ DO_WRITE <= '1';
+ DO_READ <= '0';
+ COUNT_NO <= COUNT_NO + 1;
+ ELSIF(COUNT_NO< 8) THEN
+ DO_WRITE <= '0';
+ DO_READ <= '1';
+ COUNT_NO <= COUNT_NO + 1;
+ ELSIF(COUNT_NO=8) THEN
+ DO_WRITE <= '0';
+ DO_READ <= '0';
+ COUNT_NO <= 0 ;
+ END IF;
+ END IF;
+END PROCESS;
+
+BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
+BEGIN
+ DFF_RIGHT: IF I=0 GENERATE
+ BEGIN
+ SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
+ PORT MAP(
+ Q => DO_READ_REG(0),
+ CLK => CLK,
+ RST => RST,
+ D => DO_READ
+ );
+ END GENERATE DFF_RIGHT;
+ DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
+ BEGIN
+ SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
+ PORT MAP(
+ Q => DO_READ_REG(I),
+ CLK => CLK,
+ RST => RST,
+ D => DO_READ_REG(I-1)
+ );
+ END GENERATE DFF_OTHERS;
+END GENERATE BEGIN_SHIFT_REG;
+
+ WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
+
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_tb_pkg.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_tb_pkg.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_tb_pkg.vhd (revision 5)
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Testbench Package
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+-- BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER;
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE DIV : INTEGER;
+ BEGIN
+ DIV := DATA_VALUE/DIVISOR;
+ IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+ DIV := DIV+1;
+ END IF;
+ RETURN DIV;
+ END DIVROUNDUP;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE : STD_LOGIC)
+ RETURN STD_LOGIC IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE RETVAL : INTEGER := 0;
+ BEGIN
+ IF CONDITION=FALSE THEN
+ RETVAL:=FALSE_CASE;
+ ELSE
+ RETVAL:=TRUE_CASE;
+ END IF;
+ RETURN RETVAL;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE : STRING)
+ RETURN STRING IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ -------------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE WIDTH : INTEGER := 0;
+ VARIABLE CNT : INTEGER := 1;
+ BEGIN
+ IF (DATA_VALUE <= 1) THEN
+ WIDTH := 1;
+ ELSE
+ WHILE (CNT < DATA_VALUE) LOOP
+ WIDTH := WIDTH + 1;
+ CNT := CNT *2;
+ END LOOP;
+ END IF;
+ RETURN WIDTH;
+ END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (revision 5)
@@ -0,0 +1,237 @@
+
+
+blk_mem_gen_v7_1_vinfo
+
+
+
+
+ Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.1 + Release: ISE 14.1 / Vivado 2012.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE + 2.2 Vivado +3. Supported Devices + 3.1 ISE + 3.2 Vivado +4. Resolved Issues + 4.1 ISE + 4.2 Vivado +5. Known Issues + 5.1 ISE + 5.2 Vivado +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 +solution. For the latest core updates, see the product page at: + + www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + + 2.2 Vivado + + - 2012.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + +................................................................................ +3. SUPPORTED DEVICES + + + 3.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 3.2 Vivado + All 7 Series devices + Zynq-7000 devices + + +................................................................................ +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.1: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ +5. KNOWN ISSUES + + + 5.1 ISE + + The following are known issues for v7.1 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + + +................................................................................ +6. TECHNICAL SUPPORT + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + ++ + Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== --- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf (nonexistent) +++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/blk_mem_gen_v7_1_readme.txt
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/blk_mem_gen_v7_1_readme.txt (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/blk_mem_gen_v7_1_readme.txt (revision 5)
@@ -0,0 +1,226 @@
+ Core name: Xilinx LogiCORE Block Memory Generator
+ Version: 7.1
+ Release: ISE 14.1 / Vivado 2012.1
+ Release Date: April 24, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+ 2.1 ISE
+ 2.2 Vivado
+3. Supported Devices
+ 3.1 ISE
+ 3.2 Vivado
+4. Resolved Issues
+ 4.1 ISE
+ 4.2 Vivado
+5. Known Issues
+ 5.1 ISE
+ 5.2 Vivado
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+................................................................................
+2. NEW FEATURES
+
+
+ 2.1 ISE
+
+ - ISE 14.1 software support
+ - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,
+ and Automotive Zynq device support
+
+
+ 2.2 Vivado
+
+ - 2012.1 software support
+ - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,
+ and Automotive Zynq device support
+
+
+................................................................................
+3. SUPPORTED DEVICES
+
+
+ 3.1 ISE
+
+ The following device families are supported by the core for this release.
+
+ All 7 Series devices
+ Zynq-7000 devices
+ All Virtex-6 devices
+ All Spartan-6 devices
+ All Virtex-5 devices
+ All Spartan-3 devices
+ All Virtex-4 devices
+
+
+ 3.2 Vivado
+ All 7 Series devices
+ Zynq-7000 devices
+
+
+................................................................................
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.1:
+
+ 4.1 ISE
+
+
+ 4.2 Vivado
+
+
+................................................................................
+5. KNOWN ISSUES
+
+
+ 5.1 ISE
+
+ The following are known issues for v7.1 of this core at time of release:
+
+ 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
+ Work around: The user must review the possible scenarios that causes the collission and revise
+ their design to avoid those situations.
+ - CR588505
+
+ Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
+ Write Mode = Read First in conjunction with asynchronous clocking
+
+ 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+
+ 3. Core does not generate for large memories. Depending on the
+ machine the ISE CORE Generator software runs on, the maximum size of the memory that
+ can be generated will vary. For example, a Dual Pentium-4 server
+ with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+ - CR 415768
+ - AR 24034
+
+
+ 5.2 Vivado
+
+ The most recent information, including known issues, workarounds, and resolutions for
+ this version is provided in the IP Release Notes User Guide located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+
+................................................................................
+6. TECHNICAL SUPPORT
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY
+
+Date By Version Description
+================================================================================
+04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
+06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
+07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
+03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
+12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
+ Device support; Automotive Spartan 3A
+ DSP device support
+09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
+06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
+04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
+09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
+03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
+10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
+07/2007 Xilinx, Inc. 2.5 Revised to v2.5
+04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
+02/2007 Xilinx, Inc. 2.4 Revised to v2.4
+11/2006 Xilinx, Inc. 2.3 Revised to v2.3
+09/2006 Xilinx, Inc. 2.2 Revised to v2.2
+06/2006 Xilinx, Inc. 2.1 Revised to v2.1
+01/2006 Xilinx, Inc. 1.1 Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved.
+
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
+ injury, or severe property or environmental damage
+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
+ liability of any use of Xilinx products in Critical
+ Applications, subject only to applicable laws and
+ regulations governing limitations on product liability.
+
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.bat (revision 5)
@@ -0,0 +1,48 @@
+
+
+
+
+
+
+
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy blockMemory_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\blockMemory.ngc results\
+
+
+rem Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\blockMemory_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes
+
+echo 'Running map'
+map blockMemory_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.tcl (revision 5)
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc3s500efg320-5
+set projName blockMemory
+set design blockMemory
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module blockMemory_exdes
+add_files -norecurse {../../example_design/blockMemory_exdes.vhd}
+add_files -norecurse {./blockMemory.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc}
+set_property top blockMemory_exdes [get_property srcset [current_run]]
+synth_design
+opt_design
+place_design
+route_design
+write_sdf -rename_top_module blockMemory_exdes -file routed.sdf
+write_vhdl -mode sim routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.bat (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\blockMemory.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.sh (revision 5)
@@ -0,0 +1,48 @@
+
+
+
+
+
+
+
+
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp blockMemory_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../blockMemory.ngc results/
+
+# Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/blockMemory_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes
+
+echo 'Running map'
+map blockMemory_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.scr
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.scr (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.scr (revision 5)
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent blockMemory_exdes
+-p xc3s500e-fg320-5
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn blockMemory_exdes
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.bat (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\blockMemory.ngc .
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.sh (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../blockMemory.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.prj
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.prj (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.prj (revision 5)
@@ -0,0 +1 @@
+work ../example_design/blockMemory_exdes.vhd
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.sh (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../blockMemory.ngc .
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.tcl (revision 5)
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc3s500efg320-5
+set projName blockMemory
+set design blockMemory
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module blockMemory_exdes
+add_files -norecurse {../../example_design/blockMemory_exdes.vhd}
+add_files -norecurse {./blockMemory.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc}
+set_property top blockMemory_exdes [get_property srcset [current_run]]
+synth_design
+opt_design
+place_design
+route_design
+write_sdf -rename_top_module blockMemory_exdes -file routed.sdf
+write_vhdl -mode sim routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.v
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.v (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.v (revision 5)
@@ -0,0 +1,180 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used solely *
+* for design, simulation, implementation and creation of design files *
+* limited to Xilinx devices or technologies. Use with non-Xilinx *
+* devices or technologies is expressly prohibited and immediately *
+* terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
+* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
+* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
+* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
+* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
+* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
+* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
+* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
+* PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support appliances, *
+* devices, or systems. Use in such applications are expressly *
+* prohibited. *
+* *
+* (c) Copyright 1995-2013 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// You must compile the wrapper file blockMemory.v when simulating
+// the core, blockMemory. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module blockMemory(
+ clka,
+ rsta,
+ wea,
+ addra,
+ dina,
+ douta
+);
+
+input clka;
+input rsta;
+input [0 : 0] wea;
+input [3 : 0] addra;
+input [511 : 0] dina;
+output [511 : 0] douta;
+
+// synthesis translate_off
+
+ BLK_MEM_GEN_V7_1 #(
+ .C_ADDRA_WIDTH(4),
+ .C_ADDRB_WIDTH(4),
+ .C_ALGORITHM(0),
+ .C_AXI_ID_WIDTH(4),
+ .C_AXI_SLAVE_TYPE(0),
+ .C_AXI_TYPE(1),
+ .C_BYTE_SIZE(9),
+ .C_COMMON_CLK(0),
+ .C_DEFAULT_DATA("0"),
+ .C_DISABLE_WARN_BHV_COLL(0),
+ .C_DISABLE_WARN_BHV_RANGE(0),
+ .C_ENABLE_32BIT_ADDRESS(0),
+ .C_FAMILY("spartan3"),
+ .C_HAS_AXI_ID(0),
+ .C_HAS_ENA(0),
+ .C_HAS_ENB(0),
+ .C_HAS_INJECTERR(0),
+ .C_HAS_MEM_OUTPUT_REGS_A(0),
+ .C_HAS_MEM_OUTPUT_REGS_B(0),
+ .C_HAS_MUX_OUTPUT_REGS_A(0),
+ .C_HAS_MUX_OUTPUT_REGS_B(0),
+ .C_HAS_REGCEA(0),
+ .C_HAS_REGCEB(0),
+ .C_HAS_RSTA(1),
+ .C_HAS_RSTB(0),
+ .C_HAS_SOFTECC_INPUT_REGS_A(0),
+ .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+ .C_INIT_FILE_NAME("no_coe_file_loaded"),
+ .C_INITA_VAL("0"),
+ .C_INITB_VAL("0"),
+ .C_INTERFACE_TYPE(0),
+ .C_LOAD_INIT_FILE(0),
+ .C_MEM_TYPE(0),
+ .C_MUX_PIPELINE_STAGES(0),
+ .C_PRIM_TYPE(6),
+ .C_READ_DEPTH_A(16),
+ .C_READ_DEPTH_B(16),
+ .C_READ_WIDTH_A(512),
+ .C_READ_WIDTH_B(512),
+ .C_RST_PRIORITY_A("CE"),
+ .C_RST_PRIORITY_B("CE"),
+ .C_RST_TYPE("SYNC"),
+ .C_RSTRAM_A(0),
+ .C_RSTRAM_B(0),
+ .C_SIM_COLLISION_CHECK("ALL"),
+ .C_USE_BYTE_WEA(0),
+ .C_USE_BYTE_WEB(0),
+ .C_USE_DEFAULT_DATA(0),
+ .C_USE_ECC(0),
+ .C_USE_SOFTECC(0),
+ .C_WEA_WIDTH(1),
+ .C_WEB_WIDTH(1),
+ .C_WRITE_DEPTH_A(16),
+ .C_WRITE_DEPTH_B(16),
+ .C_WRITE_MODE_A("READ_FIRST"),
+ .C_WRITE_MODE_B("WRITE_FIRST"),
+ .C_WRITE_WIDTH_A(512),
+ .C_WRITE_WIDTH_B(512),
+ .C_XDEVICEFAMILY("spartan3e")
+ )
+ inst (
+ .CLKA(clka),
+ .RSTA(rsta),
+ .WEA(wea),
+ .ADDRA(addra),
+ .DINA(dina),
+ .DOUTA(douta),
+ .ENA(),
+ .REGCEA(),
+ .CLKB(),
+ .RSTB(),
+ .ENB(),
+ .REGCEB(),
+ .WEB(),
+ .ADDRB(),
+ .DINB(),
+ .DOUTB(),
+ .INJECTSBITERR(),
+ .INJECTDBITERR(),
+ .SBITERR(),
+ .DBITERR(),
+ .RDADDRECC(),
+ .S_ACLK(),
+ .S_ARESETN(),
+ .S_AXI_AWID(),
+ .S_AXI_AWADDR(),
+ .S_AXI_AWLEN(),
+ .S_AXI_AWSIZE(),
+ .S_AXI_AWBURST(),
+ .S_AXI_AWVALID(),
+ .S_AXI_AWREADY(),
+ .S_AXI_WDATA(),
+ .S_AXI_WSTRB(),
+ .S_AXI_WLAST(),
+ .S_AXI_WVALID(),
+ .S_AXI_WREADY(),
+ .S_AXI_BID(),
+ .S_AXI_BRESP(),
+ .S_AXI_BVALID(),
+ .S_AXI_BREADY(),
+ .S_AXI_ARID(),
+ .S_AXI_ARADDR(),
+ .S_AXI_ARLEN(),
+ .S_AXI_ARSIZE(),
+ .S_AXI_ARBURST(),
+ .S_AXI_ARVALID(),
+ .S_AXI_ARREADY(),
+ .S_AXI_RID(),
+ .S_AXI_RDATA(),
+ .S_AXI_RRESP(),
+ .S_AXI_RLAST(),
+ .S_AXI_RVALID(),
+ .S_AXI_RREADY(),
+ .S_AXI_INJECTSBITERR(),
+ .S_AXI_INJECTDBITERR(),
+ .S_AXI_SBITERR(),
+ .S_AXI_DBITERR(),
+ .S_AXI_RDADDRECC()
+ );
+
+// synthesis translate_on
+
+endmodule
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ncf
===================================================================
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ngc
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ngc (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ngc (revision 5)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$37g44<,[o}e~g`n;"2*73>(-80!?0123456382:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789;87<4FNQWW>WC@KLK7<7>11292>LHW]]0YIJMJB=294;76380BB][[:SQWE96=87;:7<4FNQWW>WUSJ5:1<3??;08JJUSS2~oj0=4?>0087701877586;2996D@_UU8gmkg;;80;2<=4338LQQVR\3NDM1=>:1<27>552F__\XZ5DN@?74<768?0??4@UURVP?BH]]K7?<4?>07877e90w067mom8>=#:1397>LHW]]0JHI\N<283:44<<3CE\XZ5AEFQF95=87;:794FNQWW>AOWI591<3?>;58JJUSS2MC[N1=50?33?10>586?2>1CXZ_UU8Q@DBCZLIH0>4?>008=?OIX\^1MIJ]A=:94;75300BB][[:@FGVG:?29437LJKR@>3:==FLMXJ0<07;@FGVD:56h1JHI\N<283:==FLMXJ0>07;@FGVD:3611JHI\N<4<;?DBCZH6=255NDEPB828f3HNO^L27:1<;?DBCZH63255NDEPA858?3HNO^O2>>99B@ATE4;4j7LJKRC>0>58?3HNO^O2<>99B@ATE4=437LJKRC>6:==FLMXI0;07;@FGVG:06h1JHI\M<983:==FLMXI050<;@NO53=EEDUBBKAPAEFQAVUXZHDLI55MUR]JJCI6:2ICINEPLHAFJVCX\PZN86MCK148GIM609<0OAE=7178GIM5P11H@F0OAEN5:AOOD703JF@M1H@FO>D968GIME=2IGGO?:;BNHG43EKCM\THDXFDD78GIMAP11H@FHW192:?FIJE@^_II?;;BMQAZABFLXJXDAA_HLEK2=DZLK_II94DCKWAWT13MCJ0=08;EKB8469?2NBM1?>>69GMD:6:7=0HDO312<4?AOF48>5;6JFA=36:2=CAH6::394DHC?52803MCJ0<617:FJE97>6?1OEL2>>69GMD:587=0HDO320<4?AOF4;85;6JFA=00:2=CAH698394DHC?60803MCJ0?817:FJE9406>1OEL2=8?58@LG;:04=7IGN<3<4?AOF4::556JFA=12>5803MCJ0>?16:FJE959>2NBM1:16:FJE939>2NBM1816:FJE919>2NBM1616:FJE9?9>2NBN1>17:FJF9776>1OEO2>1?58@LD;9;4<7IGM<01=3>BNJ5;?2:5KIC>21;169GMG:617<0HDL31?58@LD;:94<7IGM<33=3>BNJ5892:5KIC>17;1908;EKA8739?2NBN1<9>69GMG:5?7=0HDL329<4?AOE4;35:6JFB=0=3>BNJ59;245KIC>05?69?2NBN1=>>79GMG:46?1OEO2;>79GMG:26?1OEO29>79GMG:06?1OEO27>79GMG:>6>1OECO30?:8@LHF48:546JFN@>25;>BNFH6:9364DHLB840902NBBL2>7?:8@LHF482546JFN@>2=;199GMKG;:<437IGAA=05:==CAGK7>:07;EKME94?611OECO328<4?AOII58546JFN@>04;g?50?:8@LHF4:;5;6JFN@>0:2=CAGK78394DHLB80803MCEM1817:FJJD:06>1OECO38?58@LHF404<7IGAB=2=<>BNFK6:<364DHLA847902NBBO2>2?:8@LHE489546JFNC>20;>720HD@M<05=<>BNFK6:4364DHLA84?9?2NBBO2>>99GMKD;:9437IGAB=02:==CAGH7>?07;EKMF944611OECL325<;?AOIJ58>255KIO@?638?3MCEN1<8>99GMKD;:1437IGAB=0::2=CAGH7>364DHLA8669i2NBBO2<1;2=<>BNFK68=394DHLA86803MCEN1:17:FJJG:26>1OECL36?58@LHE4>4<7IGAB=:=3>BNFK622:5KIQC?4;13:2=CAYH7=394DHRA878>3MC[N1=50?58@LVE4:4=7IAN<1<4?AIF48:5;6J@A=32:2=CGH6:>394DNC?56803MEJ0<:17:FLE9726>1OCL2>6?58@JG;9>4<7IAN<0:=3>BHI5;22;5KO@>2:2=CGH69<394DNC?64803MEJ0?<17:FLE9446>1OCL2=4?58@JG;:<4<7IAN<34=3>BHI58<2:5KO@>1<;1409;EMB87803MEJ0>>19:FLE956294<7IAN<23=2>BHI595:6J@A=6=2>BHI5?5:6J@A=4=2>BHI5=5:6J@A=:=2>BHI535:6J@B=2=3>BHJ5;;2:5KOC>25;169GKG:6=7=0HBL317<4?AIE48=5;6J@B=3;:2=CGK6:5384DN@?5;1=08;EMA8779?2NDN1<=>69GKG:5;7=0HBL325<4?AIE4;?5;6J@B=05:2=CGK69;394DN@?6=803MEI0?716:FLF949?2NDN1=?>89GKG:493:5;6J@B=12:3=CGK682;5KOC>7:3=CGK6>2;5KOC>5:3=CGK6<2;5KOC>;:3=CGK622:5KOQC?4;13:2=CGYH7=394DNRA878>3ME[N1=50?58@JVE4:437IAZT@>3:<=CG\^J0<>19:FLQQG;98427IAZT@>26;?89GKPRF48>556J@UUC?508>3ME^XL2>6?;8@JSSI5;<245KOTVB84>912NDYYO318<;?AIR\H6:245KOTVB876912NDYYO320<:?AIR\H69>374DNWWE944601OCXZN<36==>BH]]K7>806;EMVPD:5>730HB[[A=04:<=CG\^J0?619:FLQQG;:0437IAZT@>1:<=CG\^J0>>1b:FLQQG;;80;245KOTVB867902NDYYO33?:8@JSSI5>546J@UUC?1;>BH]]K75364DNWWF96912NDYYL311<:?AIR\K6:=374DNWWF975601OCXZM<01==>BH]]H7=906;EMVPG:6=730HB[[B=35:<=CG\^I0<919:FLQQD;91427IAZTC>2=;>15;?89GKPRE4;9556J@UU@?618>3ME^XO2=5?;8@JSSJ58=245KOTVA871912NDYYL329<:?AIR\K695364DNWWF94912NDYYL33119:FLQQD;;8437IAZTC>0:==CG\^I0907;EMVPG:2611OCXZM<7<;?AIR\K6<255KOTVA8=8?3ME^XO26>29FJD511BBDZ__154?LHN\V:;;6GAIU]352=NF@^T94IOKW[5503@DBXR>;7:KMMQY7=>1BBDZP0758MKOSW9=<7D@FT^2;3>OIA]U;5:5FNHV\4D11BBDZP1758MKOSW8=<7D@FT^3;3>OIA]U:5:5FNHV\5D1D69JJLRX9L=0ECG[_0D4?LHN\V8;;6GAIU]152=NF@^T>?94IOKW[7503@DBXR<;7:KMMQY5=>1BBDZP2758MKOSW;=<7D@FT^0;3>OIA]U95:5FNHV\6D11BBDZP3758MKOSW:=<7D@FT^1;3>OIA]U85:5FNHV\7D1L8;HLJPZ5D?2CEEYQIW\@GBVHQ_RHOJPLPB[VDLO<5_8:R-6=~cWE>0\L\[a:RJJZDR[@NSn6^FN^@VWKGJM?1[_IAAEd9QEHD6>VY8:R]<6b9Q@DBCZLIH0=0l;SFB@ATBKJ6:2n5]D@FGV@ED4;4n7_JNDEPFGF:4294h7_JNDEPFGF:46h1YILJPFHPPPg=UMNINM1>50?;8V@ADMH6;2o5]EFAFF96=8730^HILEC>3:<=U[]K7<7>17:PPPD:7601Y_YL30;2=3>TT\K6;2:5\BHVFVW763ZBYIJQJXUPBGQYIOJo0_E\JG^OJJZUNRL;87^GB_BMOHLUNGGUHDHMD6:QLQWEB?2YYZLBPA69PVSGKWK>0_^\N4:QPVG0<[]K_Y^:4TXRF04=R8&rxxRlck^ofiZabflxjxb| gocwmsceen$emygye^`ooZkbeVmnb"xnlhf-gvruk2_XI_QYIRKAH@5<^JI27[GJW^VZT@5<_LK=7ZKN<1<5?RCF484=7ZKN<3<;?RCF4:0;2;5XE@>0:6=PMK<0[HL30?48S@D;97<0[HL32?:8S@D;;3:5:6YJB=1=g>QUA]OTABJJ_@a8SWOSMVGDHHQM1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF6:ZPPIOE?2RXXRIAD69[WQYQKJh0TRM@RD]JJCI13QniSDji;Yfk[Utne_oydaa119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk5gcl{k7>3o4aefqe95=8720mij}a=1=5==edbUfi`Qheo]dakcuajUhy|>6:`ooZkbeVmnbR~}il]tmaro9k1i`fQbel]dakYwz`gT{opdp\w6`0naePmdo\c`hX~>U:Su}{129ahnYjmdUbb}{{_cnlgn733kf`S`kb_nwwtprXjeehgo5mlnahI`khzp>n:6lcobiNahiuq%hggRcjm^efjZp0W8&poRokdsc\slbs`4>'oRokds`\slbs`4>'oRocgnpjpmk:8%iTmugPie]tmaro5=&hSlvf_rnbr`Ysqyo6$jUhc`c`n^aoo86+kVnnjl{ct^fbpd;7$jUoe~omld]tewhXja|Tobbc=1.`[aotikfnSzo}n^`krZtffno6#c^jbwZoiblii|20-a\lduXelgTcxzuu]qabuXi4:'oRfns^ofiZir|ySkhs^`>4)eX`hyTaxvPotvsqqYumnyTm0>#c^jbwZkrpVe~x}{{_sgdwZd:8%iTdl}Prde`ad;7$jUcm~Q}efaff86+kVbjR||t`?2(fYoizUyyl20-a\lduX{flinmPiorvpZtbozUj1="l_icp[via|lihSb{{ptv\v`atWk7; nQfnhv\bljbWgkfi0``_bmf[cokmVfdmikk,b]jjlrfWkg1="l_hljpgYqie7; nQfnugqbdebW}s{i0>#c^nleaYnf`~Tjdbj=1.`[hcjW}s{i0>#c^ov|ZvnxlfbbhQ|t`efw86+kVzye`Q{yqg>2)eXzlkoSikti]b940+kVxnmiQkeqvk[g;6>%iT~hok_vkgpmYf5:8'oR|jae]tmaroWk78>!mPrrv\twohz`~rSl3LE-a\vvrXx{cd~dzv_c?@A)eXzz~Txt~j=R[MG)eXzz~ym`Qn=1.`[wuszhgTn0>#c^qjiZehdecxeb`Pcig`o8GKD%iTy~kPbxvf[rcf59&hSx}j_c{waZqbj4:'oR{|e^ffbdsk|Vnjxl3?,b]vw`Ybkj7; nQzsd]pkcrbkj7; nQxe`]tmaro58&hSzkm_vkgpm;6$jU|~dzj_egspmYf58<'oRy}iug\``vs`Vh6=;"l_vpjp`YjgmoTm0\JAE]EMWUS$jU|~dzj_lmgaZd:_[C_IRHFRRV/gZqua}oT{dj{h^c>77*dW~xbxhQxievk[g;4:%iTtikyibgeehokq4y{mznn2g~5c=edfi`Ahc`rx.ahnYjmdUlicQy7^3/x23:==cagk7==07;ekme976611oeco313<;?aoii5;8255kioc?518?3mcem1?:>99gmkg;9?437igaa=34:==cagk7=507;ekme97>6>1oeco31?:8`lhf4;:546jfn`>15;>bnfh699364dhlb870902nbbl2=7?:8`lhf4;2546jfn`>1=;169gmkg;=7=0hd`n<7<4?aoii5=5;6jfn`>;:2=cagk75364dnwwe96912ndyyo311<:?air|h6:=374dnwwe975601ocxzn<01==>bh}}k7=906;emvpd:6=730hb{{a=35:<=cg|~j0<919:flqqg;91427iazt`>2=;>15;?89gkprf4;9556j`uuc?618>3me~xl2=5?;8`jssi58=245kotvb871912ndyyo329<:?air|h695364dnwwe94912ndyyo33119:flqqg;;8437iazt`>0:==cg|~j0907;emvpd:2611ocxzn<7<;?air|h6<255kotvb8=8?3me~xl26>99mcfdraen97ca=8:pbiiihxR:V"ob.s-p7Zhhagc"ob/rrqeh(uid>0~~zn8:ufe96=87<0{ho30?CDu4?82JKt??>:G87>4}T=909<<4>c6827610j00:nlok{o3eb?7n6?>>:0a4>454?>h26=i57?macd8`776290:60:?>98b882fdd43^:hk4?:082>1g|[<:1>=?51b595650?k31=oom3:&2a<<6k91]=kk52zw2g4<63|;h>7>4}%3`733k8:=7>54681>1>|@8o<7)?j5;025>\413>p57?m:d827?{#9oi1>=j4$2c9645<,=l1><<4$0fg>4=#9mi1>=<4i37`>5<#9jk1>8l4n0a:>5=5<#9jk1>=84n0a:>4=5<#9jk1>=84n0a:>6=5<#9jk1>?j4n0a:>4=5<#9jk1>?j4n0a:>6=5<#9jk1>?j4n0a:>0=5<#9jk1>?j4n0a:>2=5<#9jk1>?j4n0a:><=5<#9jk1>?j4n0a:>g=5<#9jk1>?j4n0a:>a=5<#9jk1>?j4n0a:>c=4;h02e?6=,8ij6?2:9j64>=83.:ol4=2e9m5f?=9:10e??8:18'5fg=:;n0b3:1(76g=3483>!7di389h6`>c8822>=n::>1<7*>c`816a=i9j31=:54i310>5<#9jk1>?j4n0a:>4><3`88>7>5$0ab>74c3g;h57?6;:k174<72-;hm7<=d:l2g<<6i21b>>>50;&2gd<5:m1e=n751c98m74a290/=no523f8j4e>28i07d<=b;29 4ef2;8o7c?l9;3g?>o5:90;6)?la;01`>h6k00:i65f20794?"6kh09>i5a1b;95c=5<m6=4+1bc961c5<#9jk1>9k4n0a:>4=i6=4+1bc961c5<#9jk1>9k4n0a:>6=26=4+1bc961c5<#9jk1>9k4n0a:>0=<6=4+1bc961c5<#9jk1>9k4n0a:>2=>6=4+1bc961c5<#9jk1>9k4n0a:><=86=4+1bc961c5<#9jk1>9k4n0a:>g=;6=4+1bc961c5<#9jk1>9k4n0a:>a=5<#9jk1>9k4n0a:>c=4;n00f?6=,8ij6?:j;o3`=?7632e9?l4?:%3`e?43m2d:o44>2:9l66?=83.:ol4=4d9m5f?=9:10c?=7:18'5fg=:=o0b76a=5783>!7di38?i6`>c8822>=h:1<7*>c`810`=i9j31=:54o377>5<#9jk1>9k4n0a:>4><3f8>?7>5$0ab>72b3g;h57?6;:m117<72-;hm7<;e:l2g<<6i21d>8?50;&2gd<528i07b<;c;29 4ef2;>n7c?l9;3g?>i5<80;6)?la;07a>h6k00:i65`22494?"6kh098h5a1b;95c=:183!7b=3;n46F>f89K5`13n1=<4>2;3f>x"40380e2910e2810e2:10e?;50;&2gd<5<2d:o44?;:k17?6=,8ij6?:4n0a:>4=c`810>h6k00976g=1;29 4ef2;>0b5$0ab>dec881?>of03:1(2:10el950;&2gd0=c`8bg>h6k00=76gn4;29 4ef2hi0b7>5$0ab>dec88b?>of83:1(2k10e4k50;&2gda=c`8bg>h6k00n76g6b;29 4ef2hi0b;:k:6=,8ij6lm4n0a:>44<3`3<6=4+1bc9ef=i9j31=>54i8494?"6kh0jo6`>c8820>=n1<0;6)?la;c`?k7d13;>76gm4;29 4ef2hi0b10eo<50;&2gd8:9jf4<72-;hm7ol;o3`=?7>32ci<7>5$0ab>de5<#9jk1mn5a1b;95g=c`8bg>h6k00:o65fa`83>!7di3kh7c?l9;3g?>o>n3:1(28o07d7;:18'5fg=ij1e=n751g98m4bf290/=no51e;8j4e>2910e2910e0b2;10e:18'5fg=9o>0b5$0ab>7`c881?>o5k3:1(2:10enk50;&2gd4=c`8``>h6k00976gl9;29 4ef2jn0b=83.:ol4ld:l2g<<332ch;7>5$0ab>fbc885?>od=3:1(2>10en:50;&2gd<=c`8``>h6k00j76gl1;29 4ef2jn0b5$0ab>fbc88f?>oek3:1(2o10eol50;&2gd0:9jfd<72-;hm7mk;o3`=?7632ci57>5$0ab>fb5<#9jk1oi5a1b;956=c`8``>h6k00:865fb783>!7di3io7c?l9;36?>oc=3:1(28<07dj;:18'5fg=km1e=n751698ma5=83.:ol4ld:l2g<<6021bh?4?:%3`e?ec3g;h57?6;:kg5?6=,8ij6nj4n0a:>4g<3`n;6=4+1bc9ga=i9j31=o54ibd94?"6kh0hh6`>c882g>=nkk0;6)?la;ag?k7d13;o76gl0;29 4ef2jn0b32e:?44?:%3`e?73<2d:o44n;:m27=<72-;hm7?;4:l2g<0:9l567=83.:ol4>459m5f?=9810c<=?:18'5fg=9=>0b2d83>!7di3;?86`>c8820>=h9;n1<7*>c`8201=i9j31=854o06`>5<#9jk1=9:4n0a:>40<3f;?n7>5$0ab>4233g;h57?8;:m20d<72-;hm7?;4:l2g<<6021d=9750;&2gd<6<=1e=n751898k42?290/=no51568j4e>28k07b?;7;29 4ef28>?7c?l9;3a?>i60;6)?la;370>h6k00:o65`15094?"6kh0:895a1b;95a=32e:9l4?:%3`e?71=2d:o44n;:m21<<72-;hm7?95:l2g<4?:%3`e?71=2d:o44>0:9l504=83.:ol4>649m5f?=9810c<;>:18'5fg=9??0b4g83>!7di3;=96`>c8820>=h9=o1<7*>c`8220=i9j31=854o04g>5<#9jk1=;;4n0a:>40<3f;=o7>5$0ab>4023g;h57?8;:m22g<72-;hm7?95:l2g<<6021d=;o50;&2gd<6><1e=n751898k40>290/=no51778j4e>28k07b?98;29 4ef28<>7c?l9;3a?>i6>>0;6)?la;351>h6k00:o65`17194?"6kh0::85a1b;95a=51;294~"6m<0:i55G1g;8L4c03f;h:7>5;|`2bd<7280;6=u+1d79527<@8l27E?j7:m235<722wi>8750;cb>5<7s-;n97?lc:J2b<=O9l=0V>75az3e>76=9>0:47?l:0f9e?d=n3;;6p*>c4811==#9>8186*>7287?!70<3>0(<9::59'520=<2.:;:4;;%342<,8=2695+16c90>"6?k0?7)?8c;68 41c2=1/=:k54:&23c<33-;3<7:4$0:2>1=#918186*>8287?!7?<3>0(<6::59'5=0=<2.:4:4;;%3;2<,822695+19c90>"60k0?7)?7c;68 4>c2=1/=5k54:&21=#908186*>9287?!7><3>0(<7::59'5<0=<2.:5:4;;%3:2<,832695+18c90>"61k0?7)?6c;68 4?c2=1/=4k54:&2=c<33-;j<7:4$0c2>1=#9h8186*>a287?!7f<3>0("6ik0?7)?nc;68 4gc2=1/=lk54:&2ec<33-;i<7:4$0`2>1=#9k8186*>b287?!7e<3>0("6jk087)?ke;14?!7b8390(:29'5c0=9m80(50;9j6g<72-;hm7!7di38j7c?l9;08?l40290/=no52`9m5f?=;21b>;4?:%3`e?4f3g;h57:4;h06>5<#9jk1>l5a1b;91>=n::0;6)?la;0b?k7d13<07d<=:18'5fg=:h1e=n757:9j64<72-;hm7<3`9=6=4+1bc970=i9j31<65f3583>!7di39>7c?l9;38?l54290/=no5349m5f?=:21b??4?:%3`e?523g;h57=4;h12>5<#9jk1?85a1b;90>=n;90;6)?la;16?k7d13?07d!7di3290/=no56`9m5f?=921b::4?:%3`e?0f3g;h57<4;h45>5<#9jk1:l5a1b;97>=n><0;6)?la;4b?k7d13>07d8;:18'5fg=>h1e=n755:9j26<72-;hm78n;o3`=?0<3`<96=4+1bc92d=i9j31;65f6083>!7di35<#9jk1:l5a1b;9f>=n=j0;6)?la;4b?k7d13i07d;m:18'5fg=>h1e=n75d:9j1d<72-;hm78n;o3`=?c<3`?26=4+1bc92d=i9j31j65f5983>!7di3o2?3:1(28;07d;9:18'5fg=>h1e=n751398m03=83.:ol49a:l2g<<6;21b994?:%3`e?0f3g;h57?;;:k67?6=,8ij6;o4n0a:>43<3`=96=4+1bc92d=i9j31=;54i6394?"6kh0=m6`>c8823>=n?90;6)?la;4b?k7d13;376g9f;29 4ef2?k0bb:9j2f<72-;hm78n;o3`=?7d32c=47>5$0ab>3g5<#9jk1:l5a1b;95`=c`85e>h6k00:j65f8b83>!7di32i7c?l9;28?l>f290/=no58c9m5f?=921b454?:%3`e?>e3g;h57<4;h:4>5<#9jk14o5a1b;97>=n0?0;6)?la;:a?k7d13>07d6::18'5fg=0k1e=n755:9j<1<72-;hm76m;o3`=?0<3`286=4+1bc9!7di32i7c?l9;:8?l>6290/=no58c9m5f?=121b4=4?:%3`e?>e3g;h57o4;h5e>5<#9jk14o5a1b;9f>=n?m0;6)?la;:a?k7d13i07d9l:18'5fg=0k1e=n75d:9j3g<72-;hm76m;o3`=?c<3`=j6=4+1bc9!7di32i7c?l9;33?>o003:1(28;07d98:18'5fg=0k1e=n751398m20=83.:ol47b:l2g<<6;21b;84?:%3`e?>e3g;h57?;;:k40?6=,8ij65l4n0a:>43<3`386=4+1bc9c8823>=n180;6)?la;:a?k7d13;376g60;29 4ef21h0ba290/=no58c9m5f?=9h10e5k50;&2gdb:9j5$0ab>=d5<#9jk14o5a1b;95`=91<7*>c`8;f>h6k00:j65fd`83>!7di3n27c?l9;28?lb?290/=no5d89m5f?=921bh:4?:%3`e?b>3g;h57<4;hf5>5<#9jk1h45a1b;97>=nlo0;6)?la;ff?k7d13:07djk:18'5fg=ll1e=n751:9j`f<72-;hm7jj;o3`=?4<3`ni6=4+1bc9``=i9j31?65`f883>!7di3l37c?l9;28?j`0290/=no5f99m5f?=921dj84?:%3`e?`?3g;h57<4;nd7>5<#9jk1j55a1b;97>=hn:0;6)?la;d;?k7d13>07bh=:18'5fg=n11e=n755:9lb4<72-;hm7h7;o3`=?0<3fl;6=4+1bc9b==i9j31;65`eg83>!7di3l37c?l9;:8?jcb290/=no5f99m5f?=121dii4?:%3`e?`?3g;h57o4;ng`>5<#9jk1j55a1b;9f>=hmh0;6)?la;d;?k7d13i07bk6:18'5fg=n11e=n75d:9la=<72-;hm7h7;o3`=?c<3fo<6=4+1bc9b==i9j31j65`e783>!7di3l37c?l9;33?>ib=3:1(28;07bk;:18'5fg=n11e=n751398k`5=83.:ol4i8:l2g<<6;21di?4?:%3`e?`?3g;h57?;;:mf5?6=,8ij6k64n0a:>43<3f;;<7>5$0ab>c>5<#9jk1j55a1b;952=c`8e<>h6k00:465`fe83>!7di3l37c?l9;3:?>iak3:1(28k07bhm:18'5fg=n11e=n751c98kcg=83.:ol4i8:l2g<<6k21dj;4?:%3`e?`?3g;h57?k;:mff?6=,8ij6k64n0a:>4c<3fo;6=4+1bc9b==i9j31=k54o005>5<#9jk1=?;4n0a:>5=5<#9jk1=?;4n0a:>7=54o03b>5<#9jk1=<74n0a:>5=5<#9jk1=<74n0a:>7=6=4+1bc954?54o037>5<#9jk1=<74n0a:>1=5<#9jk1=<74n0a:>3=5<#9jk1=<74n0a:>==5<#9jk1=<74n0a:>d=5<#9jk1=<74n0a:>f=5<#9jk1=<74n0a:>`=5<#9jk1=<74n0a:>46<3f;;:7>5$0ab>47>3g;h57?>;:m240<72-;hm7?>9:l2g<<6:21d==:50;&2gd<6901e=n751298k464290/=no510;8j4e>28>07b??2;29 4ef28;27c?l9;36?>i6:80;6)?la;32=>h6k00::65`13294?"6kh0:=45a1b;952=32e:=i4?:%3`e?7612d:o44>a:9l54e=83.:ol4>189m5f?=9k10c0b83>!7di3;:56`>c882a>=h99;1<7*>c`825<=i9j31=k54o00a>5<#9jk1=?o4n0a:>5=5<#9jk1=?o4n0a:>7=54}r3g6=;rT:h55224;95`4<5;?264cf348>57?i0:p60<72:qU>85224;963=::<31?<5rs3194?5|V;901?;6:378973>2::0q~<=:180[45348>57<<;<06=?4b3ty9=7>53z\15>;5=009>63=5881`>{tim0;6?uQae9>60?=0?1vll50;0xZdd<5;?265;4}rc:>5<5sWk270<:9;:7?xuf03:1>vPn8:?11<;2wxm:4?:3y]e2=::<31;i5rs`494?4|Vh<01?;6:6a8yvg22909wSo:;<06=?1e3tyj87>52z\b0>;5=007}Yi:16>875749~wd4=838pRl<4=37:>222130q~7l:181[?d348>579j;|q:f?6=:rT2n63=58847>{t1h0;6?uQ9`9>60?=><1v4750;0xZ<5;?26;:4}r;;>5<5sW3370<:9;40?xu>?3:1>vP67:?11<<1:2wx5;4?:3y]=3=::<319n5rs8794?4|V0?01?;6:4`8yvd32909wSl;;<06=?3f3tyi?7>52z\a7>;5=00>56s|b383>7}Yj;16>875559~wg7=838pRo?4=37:>052?20q~7i:181[?a348>57;k;|q:0?6=:rT2863=58866>{t<80;6>uQ409>60?=<816>875479~w40b2908wS?9e:?11<<6>l16>87517d8yv73=3:1>vP>449>60?=98>0q~?;3;296~X6<:16>8751018yv7393:1>vP>409>60?=9880q~?;0;296~X6<916>8751038yv74n3:1>vP>3g9>60?=99h0q~?87511c8yv74l3:1>vP>3e9>60?=9930q~?87511:8yv74j3:1>vP>3c9>60?=9990q~?8751108yv7413:1>vP>389>60?=9;;0q~?<8;296~X6;116>8751328yv74>3:1>vP>379>60?=98h0q~?<5;296~X6;<16>8751058yv74<3:1>vP>359>60?=99i0q~?<3;296~X6;:16>8751138yv74:3:1>vP>339>60?=n:1v<=>:181[749279944i2:p566=838pR<=?;<06=?`63ty:>k4?:3y]57`<5;?26k>4}r31a?6=:rT:>h5224;9ad=z{88o6=4={_31`>;5=00n56s|15a94?4|V8>h70<:9;g;?xu62l=0q~?;a;296~X6875e39~w42>2909wS?;9:?11<57??0:p511=838pR<:8;<06=?`a3ty:8;4?:3y]510<5;?26ko4}r376?6=:rT:8?5224;9b3=z{89<6=4={_303>;5=00nn6s|13a94?4|V88h70<:9;g3?xu6k:0;6?u21g`95f0<5;?26?m4}r72>5<20r7:jl4>719]14=Y9mh0R;_3`b>X6kl1U=nj4=37:>3b<5;?26;k4=37:>3`<5;?26:>4=37:>a0<5;?268;4=37:>00<5;?26894=37:>0><5;?26i94=37:>0c<5;?268h4=37:>36<5;?26;?4=37:>a><5;?26;84=37:>31<5;?26;74=37:>3d<5;?26io4=37:>=c<5;?265h4=37:><6<5;?264?4=37:>ad<5;?26:84=37:>21<5;?26:64=37:>2?<5;?26im4=37:>2`<5;?265>4=37:>=7<5;?265<4=37:>ab<5;?26594=37:>=><5;?265o4=37:>=e<5;?26ih4=37:>71<5;?26><4=37:>7><5;?26>=4=37:>7?<5;?26>:4=37:>7d<5;?26>84^06g?842138:7S?:8:\226=Y9?=0R<87;_35=>X6>h1U=;l4^04`?[71l2T:8h5Q15d8Z4373W;>=6P>539]505X6=k1U=8m4^07g?[72m2T:9k5Q1728Z4063W;=>6P>659]5304?:5y>5cd=9j<013;o:63>e7822`=z{;9=6=4={_002>;6m?0:>n5rs362>5<5sW8?=63>e78272=z{;>h6=4={_07g>;6m?0:8?5rs373>5<5sW8><63>e78203=z{;?:6=4={_065>;6m?0:8:5rs371>5<5sW8>>63>e7820==z{;?86=4={_067>;6m?0:845rs377>5<5sW8>863>e7820d=z{;?>6=4={_061>;6m?0:8o5rs375>5<5sW8>:63>e7820f=z{;9<6=4={_003>;6m?0:>i5rs31;>5<5sW88463>e7826`=z{;926=4={_00=>;6m?0:>k5rs31b>5<5sW88m63>e78275=z{;9i6=4={_00f>;6m?0:?<5rs31`>5<5sW88o63>e78277=z{;9o6=4={_00`>;6m?0:?>5rs31f>5<5sW88i63>e78271=z{;9m6=4={_00b>;6m?0:?85rs363>5<5sW8?<63>e78273=z{;>96=4={_076>;6m?0:?55rs360>5<5sW8??63>e7827<=z{;>?6=4={_070>;6m?0:?l5rs366>5<5sW8?963>e7827g=z{;>=6=4={_072>;6m?0:?n5rs364>5<5sW8?;63>e7827a=z{;>36=4={_07<>;6m?0:?h5rs36:>5<5sW8?563>e7827c=z{;>j6=4={_07e>;6m?0:8=5rs36a>5<5sW8?n63>e78204=z{;>o6=4={_07`>;6m?0:8>5rs36e>5<5sW8?j63>e78200=z{;;?6=4={_020>;6m?0?=6s|20794?4|V;;>70?j6;;7?xu5:90;6?uQ232894c120l0q~<=b;296~X5:k16=h85a`9~w74a2909wS<=f:?2a3>>50;0xZ75734;n:7oi;|q174<72;qU>>?4=0g5>g67>52z\177=:9l<1n<5rs310>5<5sW88?63>e78a6>{t::>1<73h87p}=3483>7}Y::?013:1>vP=179>5`0=1<1v??8:181[46?27:i;466:p64>=838pR??7;<3f2??03ty9=44?:3y]64?<58o=6464}r02e?6=:rT9=l521d49=<=z{;;i6=4={_02f>;6m?02m6s|20a94?4|V;;h70?j6;;a?xu59m0;6?uQ20f894c120i0q~<>e;296~X59l16=h859e9~w77a2909wS<>f:?2a3<>m2wx>??50;0xZ74634;n:7o?;|q167<72;qU>?<4=0g5>d752z\166=:9l<1m?5rs307>5<5sW89863>e78b7>{t:;?1<73k?7p}=2783>7}Y:;<01vP=269>5`0=i?1v?<7:181[45027:i;4n7:p67?=838pR?<6;<3f2?g?3ty9>l4?:3y]67g<58o=6l74}r01g?6=:rT9>n521d49eg=z{;8n6=4={_01a>;6m?0jh6s|21194?4|V;:870?j6;02?xu58=0;6?uQ216894c12;80q~5;296~X58<16=h85229~w7602909wS7:?2a3<5=2wx>8m50;7xZ73d34;n:7?jf:?2a3<6mm16=h851da894c128oi7p}=5`83>7}Y:vF>e69~j4`62909wE?j7:m5c4=838pD5<5sA;n;6sa1g494?4|@8o<7p`>f683>7}O9l=0qc?i8;296~N6m>1vb52zJ2a2=zf8lo6=4={I3f3>{i9oo1<7vF>e69~j7662909wE?j7:m654=838pD5<5sA;n;6sa21494?4|@8o<7p`=0683>7}O9l=0qc8;296~N6m>1vb?>6:181M7b?2we>=o50;0xL4c03td952zJ2a2=zf;:o6=4={I3f3>{i:9o1<7vF>e69~j7762909wE?j7:m644=838pD5<5sA;n;6sa20494?4|@8o<7p`=1683>7}O9l=0qc<>8;296~N6m>1vb??6:181M7b?2we>52zJ2a2=zf;;o6=4={I3f3>{i:8o1<7vF>e69~j7462909wE?j7:m674=838pD5<5sA;n;6sa23494?4|@8o<7p`=2683>7}O9l=0qc<=8;296~N6m>1vb?<6:181M7b?2we>?o50;0xL4c03td9>o4?:3yK5`152zJ2a2=zf;8o6=4={I3f3>{i:;o1<7vF>e69~j7562909wE?j7:m664=838pD5<5sA;n;6sa1da94?7|@8o<7p`>ee83>4}O9l=0qpsr@AAx6=6=::
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgp
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgp (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgp (revision 5)
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc3s500e
+SET devicefamily = spartan3e
+SET flowvendor = Other
+SET package = fg320
+SET speedgrade = -5
+SET verilogsim = false
+SET vhdlsim = true
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.sym
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.sym (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.sym (revision 5)
@@ -0,0 +1,27 @@
+
+
+ BLOCK
+ 2015-2-1T11:33:56
+
+
+
+
+
+
+
+ blockMemory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/xlnx_auto_0_xdb
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/xlnx_auto_0_xdb (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/xlnx_auto_0_xdb (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/xlnx_auto_0_xdb
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/gen_blockMemory.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/gen_blockMemory.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/gen_blockMemory.tcl (revision 5)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator regen command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_regen "blockMemory" xc3s500e-5fg320 VHDL CURRENT ]
+
+if { $result == 0 } {
+ puts "Core Generator regen command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator regen command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator regen cancelled."
+}
+exit $result
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/pn_parser.xmsgs
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/pn_parser.xmsgs (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/pn_parser.xmsgs (revision 5)
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/cg.xmsgs
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/cg.xmsgs (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/cg.xmsgs (revision 5)
@@ -0,0 +1,30 @@
+
+
+
+Generating IP...
+
+
+A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten.
+
+
+A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten.
+
+
+Component blk_mem_gen_v7_1 does not have a valid model name for VHDL synthesis
+
+
+Pre-processing HDL files for 'blockMemory'...
+
+
+Finished generation of ASY schematic symbol.
+
+
+Finished FLIST file generation.
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/blockMemory.lso
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/blockMemory.lso (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/blockMemory.lso (revision 5)
@@ -0,0 +1 @@
+work
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/pn_parser.xmsgs
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/pn_parser.xmsgs (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/pn_parser.xmsgs (revision 5)
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/xst.xmsgs
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/xst.xmsgs (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/xst.xmsgs (revision 5)
@@ -0,0 +1,412 @@
+
+
+
+Message file "usenglish/ip.msg " wasn't found.
+
+
+0 : (0 ,0 ) : 72 x256 u:32
+
+
+0 : (0 ,0 ) : 72 x256 u:32
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns FALSE .
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns FALSE .
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Range is empty (null range)
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Assignment ignored
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Range is empty (null range)
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Assignment ignored
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Range is empty (null range)
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Assignment ignored
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 370: Net <doutb_i[71] > does not have a driver.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 429: Net <dina_pad[71] > does not have a driver.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 433: Net <dinb_pad[71] > does not have a driver.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE .
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns FALSE .
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <doutb > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <rdaddrecc > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_bid > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_bresp > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_rid > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_rdata > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_rresp > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_rdaddrecc > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <sbiterr > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <dbiterr > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_awready > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_wready > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_bvalid > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_arready > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_rlast > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_rvalid > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_sbiterr > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd " line 161 : Output port <s_axi_dbiterr > of the instance <U0 > is unconnected or connected to loadless signal.
+
+
+Input <S_AXI_AWID > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_AWADDR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_AWLEN > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_AWSIZE > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_AWBURST > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_WDATA > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_WSTRB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_ARID > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_ARADDR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_ARLEN > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_ARSIZE > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_ARBURST > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AClk > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_ARESETN > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_AWVALID > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_WLAST > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_WVALID > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_BREADY > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_ARVALID > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_RREADY > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_INJECTSBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <S_AXI_INJECTDBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Signal 'S_AXI_BID ', unconnected in block 'blk_mem_gen_v7_1_xst ', is tied to its initial value (0000 ).
+
+
+Signal <S_AXI_BRESP > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal 'S_AXI_RID ', unconnected in block 'blk_mem_gen_v7_1_xst ', is tied to its initial value (0000 ).
+
+
+Signal <S_AXI_RDATA > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_RRESP > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_RDADDRECC > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_AWREADY > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_WREADY > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_BVALID > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_ARREADY > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_RLAST > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_RVALID > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_SBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <S_AXI_DBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Input <WEB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <ADDRB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <DINB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <ENA > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <REGCEA > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <CLKB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <RSTB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <ENB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <REGCEB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <INJECTDBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <INJECTSBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Signal <INJECTDBITERR_I > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <INJECTSBITERR_I > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Input <REGCEA > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <WEA<3:1> > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <REGCEB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <WEB<3:1> > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <INJECTSBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <INJECTDBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd " line 1343 : Output port <SBITERR > of the instance <ramloop[0].ram.r > is unconnected or connected to loadless signal.
+
+
+"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd " line 1343 : Output port <DBITERR > of the instance <ramloop[0].ram.r > is unconnected or connected to loadless signal.
+
+
+Signal <RDADDRECC > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <SBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <DBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Input <INJECTSBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <INJECTDBITERR > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Signal 'dina_pad<71:67> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<62:58> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<53:49> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<44:40> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<35:31> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<26:22> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<17:13> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dina_pad<8:4> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<71:67> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<62:58> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<53:49> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<44:40> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<35:31> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<26:22> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<17:13> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal 'dinb_pad<8:4> ', unconnected in block 'blk_mem_gen_prim_width ', is tied to its initial value (00000 ).
+
+
+Signal <SBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <DBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Input <ADDRB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <DINB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <REGCEA > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <CLKB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <ENB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <REGCEB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <WEB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Signal 'doutb_i ', unconnected in block 'blk_mem_gen_prim_wrapper_s3 ', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000 ).
+
+
+Input <DOUTB_I > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <RDADDRECC_I > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <CLKB > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <SBITERR_I > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Input <DBITERR_I > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+
+
+Signal <RDADDRECC > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <SBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+Signal <DBITERR > is used but never assigned. This sourceless signal will be automatically connected to value GND .
+
+
+HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+
+
+You have chosen to run a version of XST which is not the default solution
+for the specified device family. You are free to use it in order to take
+advantage of its enhanced HDL parsing/elaboration capabilities. However,
+please be aware that you may be impacted by language support differences.
+This version may also result in circuit performance and device utilization
+differences for your particular design. You can always revert back to the
+default XST solution by setting the "use_new_parser" option to value "no"
+on the XST command line or in the XST process properties panel.
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/tmp
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_flist.txt
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_flist.txt (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_flist.txt (revision 5)
@@ -0,0 +1,60 @@
+# Output products list for
+_xmsgs\pn_parser.xmsgs
+blockMemory.asy
+blockMemory.gise
+blockMemory.ngc
+blockMemory.sym
+blockMemory.vhd
+blockMemory.vho
+blockMemory.xco
+blockMemory.xise
+blockMemory\blk_mem_gen_v7_1_readme.txt
+blockMemory\doc\blk_mem_gen_ds512.pdf
+blockMemory\doc\blk_mem_gen_v7_1_vinfo.html
+blockMemory\example_design\blockMemory_exdes.ucf
+blockMemory\example_design\blockMemory_exdes.vhd
+blockMemory\example_design\blockMemory_exdes.xdc
+blockMemory\example_design\blockMemory_prod.vhd
+blockMemory\implement\implement.bat
+blockMemory\implement\implement.sh
+blockMemory\implement\planAhead_ise.bat
+blockMemory\implement\planAhead_ise.sh
+blockMemory\implement\planAhead_ise.tcl
+blockMemory\implement\planAhead_rdn.bat
+blockMemory\implement\planAhead_rdn.sh
+blockMemory\implement\planAhead_rdn.tcl
+blockMemory\implement\xst.prj
+blockMemory\implement\xst.scr
+blockMemory\simulation\addr_gen.vhd
+blockMemory\simulation\blockMemory_synth.vhd
+blockMemory\simulation\blockMemory_tb.vhd
+blockMemory\simulation\bmg_stim_gen.vhd
+blockMemory\simulation\bmg_tb_pkg.vhd
+blockMemory\simulation\checker.vhd
+blockMemory\simulation\data_gen.vhd
+blockMemory\simulation\functional\simcmds.tcl
+blockMemory\simulation\functional\simulate_isim.bat
+blockMemory\simulation\functional\simulate_mti.bat
+blockMemory\simulation\functional\simulate_mti.do
+blockMemory\simulation\functional\simulate_mti.sh
+blockMemory\simulation\functional\simulate_ncsim.sh
+blockMemory\simulation\functional\simulate_vcs.sh
+blockMemory\simulation\functional\ucli_commands.key
+blockMemory\simulation\functional\vcs_session.tcl
+blockMemory\simulation\functional\wave_mti.do
+blockMemory\simulation\functional\wave_ncsim.sv
+blockMemory\simulation\random.vhd
+blockMemory\simulation\timing\simcmds.tcl
+blockMemory\simulation\timing\simulate_isim.bat
+blockMemory\simulation\timing\simulate_mti.bat
+blockMemory\simulation\timing\simulate_mti.do
+blockMemory\simulation\timing\simulate_mti.sh
+blockMemory\simulation\timing\simulate_ncsim.sh
+blockMemory\simulation\timing\simulate_vcs.sh
+blockMemory\simulation\timing\ucli_commands.key
+blockMemory\simulation\timing\vcs_session.tcl
+blockMemory\simulation\timing\wave_mti.do
+blockMemory\simulation\timing\wave_ncsim.sv
+blockMemory_flist.txt
+blockMemory_xmdf.tcl
+summary.log
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.log
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.log (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.log (revision 5)
@@ -0,0 +1,63 @@
+INFO:sim:172 - Generating IP...
+Applying current project options...
+Finished applying current project options.
+WARNING:sim - A core named 'blockMemory' already exists in the project. Output
+ products for this core may be overwritten.
+Resolving generics for 'blockMemory'...
+WARNING:sim - A core named 'blockMemory' already exists in the project. Output
+ products for this core may be overwritten.
+Applying external generics to 'blockMemory'...
+Delivering associated files for 'blockMemory'...
+WARNING:sim - Component blk_mem_gen_v7_1 does not have a valid model name for
+ VHDL synthesis
+Delivering EJava files for 'blockMemory'...
+Generating implementation netlist for 'blockMemory'...
+INFO:sim - Pre-processing HDL files for 'blockMemory'...
+Running synthesis for 'blockMemory'
+Running ngcbuild...
+Writing VHO instantiation template for 'blockMemory'...
+Writing VHDL behavioral simulation model for 'blockMemory'...
+Generating ASY schematic symbol...
+INFO:sim:949 - Finished generation of ASY schematic symbol.
+Generating SYM schematic symbol for 'blockMemory'...
+Generating metadata file...
+Generating ISE project...
+XCO file found: blockMemory.xco
+XMDF file found: blockMemory_xmdf.tcl
+Adding E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.asy -view all -origin_type imported
+Adding E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.ngc -view all -origin_type created
+Checking file "E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.ngc" for project device match ...
+File "E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.ngc" device information matches project device.
+Adding E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.sym -view all -origin_type imported
+Adding E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.vhd -view all -origin_type created
+INFO:HDLCompiler:1061 - Parsing VHDL file "E:/spent i
+ praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp
+ /_cg/blockMemory.vhd" into library work
+INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
+Adding E:/spent i
+praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
+g/blockMemory.vho -view all -origin_type imported
+INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
+ Please set the new top explicitly by running the "project set top" command.
+ To re-calculate the new top automatically, set the "Auto Implementation Top"
+ property to true.
+Top level has been set to "/blockMemory"
+Generating README file...
+Generating FLIST file...
+INFO:sim:948 - Finished FLIST file generation.
+Launching README viewer...
+Moving files to output directory...
+Finished moving files to output directory
+Wrote CGP file for project 'blockMemory'.
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd (revision 5)
@@ -0,0 +1,144 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2015 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file blockMemory.vhd when simulating
+-- the core, blockMemory. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY blockMemory IS
+ PORT (
+ clka : IN STD_LOGIC;
+ rsta : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+END blockMemory;
+
+ARCHITECTURE blockMemory_a OF blockMemory IS
+-- synthesis translate_off
+COMPONENT wrapped_blockMemory
+ PORT (
+ clka : IN STD_LOGIC;
+ rsta : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_blockMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_1(behavioral)
+ GENERIC MAP (
+ c_addra_width => 4,
+ c_addrb_width => 4,
+ c_algorithm => 0,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan3",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 1,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 0,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 6,
+ c_read_depth_a => 16,
+ c_read_depth_b => 16,
+ c_read_width_a => 32,
+ c_read_width_b => 32,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 0,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 16,
+ c_write_depth_b => 16,
+ c_write_mode_a => "READ_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 32,
+ c_write_width_b => 32,
+ c_xdevicefamily => "spartan3e"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_blockMemory
+ PORT MAP (
+ clka => clka,
+ rsta => rsta,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ douta => douta
+ );
+-- synthesis translate_on
+
+END blockMemory_a;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/edit_blockMemory.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/edit_blockMemory.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/edit_blockMemory.tcl (revision 5)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "blockMemory" xc3s500e-5fg320 VHDL ]
+
+if { $result == 0 } {
+ puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator edit cancelled."
+}
+exit $result
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.gise
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.gise (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.gise (revision 5)
@@ -0,0 +1,49 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_beh.cgp
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_beh.cgp (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_beh.cgp (revision 5)
@@ -0,0 +1,22 @@
+# Date: Sat Dec 22 01:24:09 2012
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc3s500e
+SET devicefamily = spartan3e
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg320
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = false
+SET vhdlsim = true
+SET workingdirectory = .\tmp\
+
+# CRC: 46f7aa00
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.veo
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.veo (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.veo (revision 5)
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used solely *
+* for design, simulation, implementation and creation of design files *
+* limited to Xilinx devices or technologies. Use with non-Xilinx *
+* devices or technologies is expressly prohibited and immediately *
+* terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
+* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
+* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
+* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
+* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
+* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
+* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
+* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
+* PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support appliances, *
+* devices, or systems. Use in such applications are expressly *
+* prohibited. *
+* *
+* (c) Copyright 1995-2013 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+
+/*******************************************************************************
+* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 *
+* *
+* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
+* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
+* direct drop-in replacement. It should be used in all new Xilinx *
+* designs. The core supports RAM and ROM functions over a wide range of *
+* widths and depths. Use this core to generate block memories with *
+* symmetric or asymmetric read and write port widths, as well as cores *
+* which can perform simultaneous write operations to separate *
+* locations, and simultaneous read operations from the same location. *
+* For more information on differences in interface and feature support *
+* between this core and the Dual Port Block Memory and Single Port *
+* Block Memory LogiCOREs, please consult the data sheet. *
+*******************************************************************************/
+
+// Interfaces:
+// AXI_SLAVE_S_AXI
+// AXI_SLAVE
+// AXILite_SLAVE_S_AXI
+// AXILite_SLAVE
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+blockMemory your_instance_name (
+ .clka(clka), // input clka
+ .rsta(rsta), // input rsta
+ .wea(wea), // input [0 : 0] wea
+ .addra(addra), // input [3 : 0] addra
+ .dina(dina), // input [511 : 0] dina
+ .douta(douta) // output [511 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file blockMemory.v when simulating
+// the core, blockMemory. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.xco
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.xco (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.xco (revision 5)
@@ -0,0 +1,106 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sun Feb 01 11:31:51 2015
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:blk_mem_gen:7.1
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc3s500e
+SET devicefamily = spartan3e
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg320
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.1
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Fixed_Primitives
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=blockMemory
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET memory_type=Single_Port_RAM
+CSET operating_mode_a=READ_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=50
+CSET primitive=256x72
+CSET read_width_a=32
+CSET read_width_b=32
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=true
+CSET use_rstb_pin=false
+CSET write_depth_a=16
+CSET write_width_a=32
+CSET write_width_b=32
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-01T17:17:26Z
+# END Extra information
+GENERATE
+# CRC: 442de25c
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/summary.log
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/summary.log (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/summary.log (revision 5)
@@ -0,0 +1,18 @@
+
+User Configuration
+-------------------------------------
+Algorithm : Fixed_Primitives
+Memory Type : Single_Port_RAM
+Port A Read Width : 32
+Port A Write Width : 32
+Memory Depth : 16
+--------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs) : 1
+--------------------------------------------------------------
+Clock A Frequency : 100
+Port A Enable Rate : 100
+Port A Write Rate : 50
+----------------------------------------------------------
+Estimated Power for IP : 8.073006 mW
+----------------------------------------------------------
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgc
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgc (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgc (revision 5)
@@ -0,0 +1,725 @@
+
+
+ xilinx.com
+ project
+ coregen
+ 1.0
+
+
+ blockMemory
+
+
+ blockMemory
+ Native
+ AXI4_Full
+ Memory_Slave
+ false
+ 4
+ Single_Port_RAM
+ false
+ No_ECC
+ false
+ false
+ false
+ Single_Bit_Error_Injection
+ false
+ 9
+ Fixed_Primitives
+ 256x72
+ false
+ 64
+ 16
+ 64
+ READ_FIRST
+ Always_Enabled
+ 64
+ 64
+ WRITE_FIRST
+ Always_Enabled
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 0
+ false
+ no_coe_file_loaded
+ false
+ 0
+ true
+ false
+ CE
+ 0
+ false
+ false
+ CE
+ 0
+ SYNC
+ false
+ 100
+ 50
+ 100
+ 50
+ 100
+ 100
+ ALL
+ false
+ false
+ spartan3
+ spartan3e
+ E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_cg/
+ 0
+ 1
+ 0
+ 0
+ 4
+ 0
+ 9
+ 0
+ 6
+ 0
+ no_coe_file_loaded
+ 0
+ 0
+ SYNC
+ 1
+ CE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ READ_FIRST
+ 64
+ 64
+ 16
+ 16
+ 4
+ 0
+ CE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ WRITE_FIRST
+ 64
+ 64
+ 16
+ 16
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ALL
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+ coregen
+ ./
+ ./tmp/
+ ./tmp/_cg/
+
+
+ xc3s500e
+ spartan3e
+ fg320
+ -5
+
+
+ BusFormatAngleBracketNotRipped
+ VHDL
+ true
+ Other
+ false
+ false
+ false
+ Ngc
+ false
+
+
+ Behavioral
+ VHDL
+ false
+
+
+ 2012-05-01+17:17
+
+
+
+
+ customization_generator
+
+ ./summary.log
+ unknown
+ Sun Feb 01 11:01:05 GMT 2015
+ 0x276B8704
+ generationID_4013899584
+
+
+
+ model_parameter_resolution_generator
+
+ ./summary.log
+ unknown
+ Sun Feb 01 11:01:18 GMT 2015
+ 0x276B8704
+ generationID_4013899584
+
+
+
+ ip_xco_generator
+
+ ./blockMemory.xco
+ xco
+ Sun Feb 01 11:01:19 GMT 2015
+ 0xB3588484
+ generationID_4013899584
+
+
+
+ associated_files_generator
+
+ ./blockMemory/blk_mem_gen_v7_1_readme.txt
+ ignore
+ txt
+ Sat Jul 21 06:09:39 GMT 2012
+ 0xD29D9619
+ generationID_4013899584
+
+
+ ./blockMemory/doc/blk_mem_gen_ds512.pdf
+ ignore
+ pdf
+ Sat Jul 21 06:09:39 GMT 2012
+ 0xC67523A8
+ generationID_4013899584
+
+
+ ./blockMemory/doc/blk_mem_gen_v7_1_vinfo.html
+ ignore
+ unknown
+ Sat Jul 21 06:09:39 GMT 2012
+ 0x19E371FD
+ generationID_4013899584
+
+
+
+ ejava_generator
+
+ ./blockMemory/example_design/blockMemory_exdes.ucf
+ ignore
+ ucf
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xC44C6B6D
+ generationID_4013899584
+
+
+ ./blockMemory/example_design/blockMemory_exdes.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xC531B9D3
+ generationID_4013899584
+
+
+ ./blockMemory/example_design/blockMemory_exdes.xdc
+ ignore
+ xdc
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x7684D6D4
+ generationID_4013899584
+
+
+ ./blockMemory/example_design/blockMemory_prod.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xBCC35C04
+ generationID_4013899584
+
+
+ ./blockMemory/implement/implement.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x73DC98D0
+ generationID_4013899584
+
+
+ ./blockMemory/implement/implement.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xDA8C5F63
+ generationID_4013899584
+
+
+ ./blockMemory/implement/planAhead_ise.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xAB675294
+ generationID_4013899584
+
+
+ ./blockMemory/implement/planAhead_ise.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x2CC3322B
+ generationID_4013899584
+
+
+ ./blockMemory/implement/planAhead_ise.tcl
+ ignore
+ tcl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xE0D499D8
+ generationID_4013899584
+
+
+ ./blockMemory/implement/planAhead_rdn.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xF18BE2F0
+ generationID_4013899584
+
+
+ ./blockMemory/implement/planAhead_rdn.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x762F824F
+ generationID_4013899584
+
+
+ ./blockMemory/implement/planAhead_rdn.tcl
+ ignore
+ tcl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xE0D499D8
+ generationID_4013899584
+
+
+ ./blockMemory/implement/xst.prj
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x49531A1B
+ generationID_4013899584
+
+
+ ./blockMemory/implement/xst.scr
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x0ACE6523
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/addr_gen.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xC4BD0686
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/blockMemory_synth.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x242B5734
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/blockMemory_tb.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x403EDE43
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/bmg_stim_gen.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xB51AD3DA
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/bmg_tb_pkg.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x888E222F
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/checker.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x165912E8
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/data_gen.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xAAF37274
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simcmds.tcl
+ ignore
+ tcl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x32EA978C
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simulate_isim.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x5732BCC0
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simulate_mti.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x86EA5D67
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simulate_mti.do
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xFFDC1F87
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simulate_mti.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x86EA5D67
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simulate_ncsim.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x7DAF5A7C
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/simulate_vcs.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x0377E85E
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/ucli_commands.key
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x124DD850
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/vcs_session.tcl
+ ignore
+ tcl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x65C492A4
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/wave_mti.do
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xD1AE9DBA
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/functional/wave_ncsim.sv
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xFA4242CF
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/random.vhd
+ ignore
+ vhdl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x63A1BAB3
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simcmds.tcl
+ ignore
+ tcl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x32EA978C
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simulate_isim.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x4934A6A9
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simulate_mti.bat
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x86EA5D67
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simulate_mti.do
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x73AA9BB8
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simulate_mti.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x86EA5D67
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simulate_ncsim.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xFBC651DC
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/simulate_vcs.sh
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x4D9140C3
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/ucli_commands.key
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x124DD850
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/vcs_session.tcl
+ ignore
+ tcl
+ Sun Feb 01 11:01:22 GMT 2015
+ 0xB2A5A6F2
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/wave_mti.do
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x9F72A3C7
+ generationID_4013899584
+
+
+ ./blockMemory/simulation/timing/wave_ncsim.sv
+ ignore
+ unknown
+ Sun Feb 01 11:01:22 GMT 2015
+ 0x3E2BD0E3
+ generationID_4013899584
+
+
+
+ ngc_netlist_generator
+
+ ./blockMemory.ngc
+ ngc
+ Sun Feb 01 11:03:12 GMT 2015
+ 0xB01C4161
+ generationID_4013899584
+
+
+
+ obfuscate_netlist_generator
+
+
+ padded_implementation_netlist_generator
+
+
+ instantiation_template_generator
+
+ ./blockMemory.vho
+ vho
+ Sun Feb 01 11:03:15 GMT 2015
+ 0x533BD793
+ generationID_4013899584
+
+
+
+ structural_simulation_model_generator
+
+ ./blockMemory.vhd
+ vhdl
+ Sun Feb 01 11:03:16 GMT 2015
+ 0x4F617396
+ generationID_4013899584
+
+
+
+ asy_generator
+
+ ./blockMemory.asy
+ asy
+ Sun Feb 01 11:03:25 GMT 2015
+ 0xD23467E4
+ generationID_4013899584
+
+
+ ./summary.log
+ unknown
+ Sun Feb 01 11:03:25 GMT 2015
+ 0x276B8704
+ generationID_4013899584
+
+
+
+ xmdf_generator
+
+ ./blockMemory_xmdf.tcl
+ tclXmdf
+ tcl
+ Sun Feb 01 11:03:25 GMT 2015
+ 0x0F84EBAC
+ generationID_4013899584
+
+
+
+ ise_generator
+
+ ./_xmsgs/pn_parser.xmsgs
+ ignore
+ unknown
+ Sun Feb 01 11:03:38 GMT 2015
+ 0x8B9E9C83
+ generationID_4013899584
+
+
+ ./blockMemory.gise
+ ignore
+ gise
+ Sun Feb 01 11:03:38 GMT 2015
+ 0x12517467
+ generationID_4013899584
+
+
+ ./blockMemory.xise
+ ignore
+ xise
+ Sun Feb 01 11:03:38 GMT 2015
+ 0xBEBA0475
+ generationID_4013899584
+
+
+
+ deliver_readme_generator
+
+
+ flist_generator
+
+ ./blockMemory_flist.txt
+ ignore
+ txtFlist
+ txt
+ Sun Feb 01 11:03:39 GMT 2015
+ 0x56F501F4
+ generationID_4013899584
+
+
+
+ view_readme_generator
+
+
+
+
+
+
+
+
+ coregen
+ ./
+ ./tmp/
+ ./tmp/_cg/
+
+
+ xc3s500e
+ spartan3e
+ fg320
+ -5
+
+
+ BusFormatAngleBracketNotRipped
+ VHDL
+ true
+ Other
+ false
+ false
+ false
+ Ngc
+ false
+
+
+ Behavioral
+ VHDL
+ false
+
+
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.asy
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.asy (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.asy (revision 5)
@@ -0,0 +1,29 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 blockMemory
+RECTANGLE Normal 32 32 544 1376
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName addra[3:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName dina[31:0]
+PINATTR Polarity IN
+LINE Wide 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wea[0:0]
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rsta
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName douta[31:0]
+PINATTR Polarity OUT
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vho
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vho (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vho (revision 5)
@@ -0,0 +1,89 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2015 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 --
+-- --
+-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port --
+-- Block Memory and Single Port Block Memory LogiCOREs, but is not a --
+-- direct drop-in replacement. It should be used in all new Xilinx --
+-- designs. The core supports RAM and ROM functions over a wide range of --
+-- widths and depths. Use this core to generate block memories with --
+-- symmetric or asymmetric read and write port widths, as well as cores --
+-- which can perform simultaneous write operations to separate --
+-- locations, and simultaneous read operations from the same location. --
+-- For more information on differences in interface and feature support --
+-- between this core and the Dual Port Block Memory and Single Port --
+-- Block Memory LogiCOREs, please consult the data sheet. --
+--------------------------------------------------------------------------------
+
+-- Interfaces:
+-- AXI_SLAVE_S_AXI
+-- AXI_SLAVE
+-- AXILite_SLAVE_S_AXI
+-- AXILite_SLAVE
+-- BRAM_PORTA
+-- BRAM_PORTA
+-- BRAM_PORTB
+-- BRAM_PORTB
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT blockMemory
+ PORT (
+ clka : IN STD_LOGIC;
+ rsta : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : blockMemory
+ PORT MAP (
+ clka => clka,
+ rsta => rsta,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ douta => douta
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file blockMemory.vhd when simulating
+-- the core, blockMemory. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32 (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32 (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory32
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_xmdf.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_xmdf.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_xmdf.tcl (revision 5)
@@ -0,0 +1,263 @@
+# The package naming convention is _xmdf
+package provide blockMemory_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is _xmdf
+namespace eval ::blockMemory_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::blockMemory_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation:
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name blockMemory
+}
+# ::blockMemory_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::blockMemory_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/blk_mem_gen_v7_1_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_ds512.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_v7_1_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_prod.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/addr_gen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_synth.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_tb.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_stim_gen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_tb_pkg.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/checker.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/data_gen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/random.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blockMemory
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_prod.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_prod.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_prod.vhd (revision 5)
@@ -0,0 +1,270 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: blockMemory_prod.vhd
+--
+-- Description:
+-- This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+-- C_FAMILY : spartan3e
+-- C_XDEVICEFAMILY : spartan3e
+-- C_INTERFACE_TYPE : 0
+-- C_ENABLE_32BIT_ADDRESS : 0
+-- C_AXI_TYPE : 1
+-- C_AXI_SLAVE_TYPE : 0
+-- C_AXI_ID_WIDTH : 4
+-- C_MEM_TYPE : 0
+-- C_BYTE_SIZE : 9
+-- C_ALGORITHM : 0
+-- C_PRIM_TYPE : 6
+-- C_LOAD_INIT_FILE : 0
+-- C_INIT_FILE_NAME : no_coe_file_loaded
+-- C_USE_DEFAULT_DATA : 0
+-- C_DEFAULT_DATA : 0
+-- C_RST_TYPE : SYNC
+-- C_HAS_RSTA : 1
+-- C_RST_PRIORITY_A : CE
+-- C_RSTRAM_A : 0
+-- C_INITA_VAL : 0
+-- C_HAS_ENA : 0
+-- C_HAS_REGCEA : 0
+-- C_USE_BYTE_WEA : 0
+-- C_WEA_WIDTH : 1
+-- C_WRITE_MODE_A : READ_FIRST
+-- C_WRITE_WIDTH_A : 512
+-- C_READ_WIDTH_A : 512
+-- C_WRITE_DEPTH_A : 16
+-- C_READ_DEPTH_A : 16
+-- C_ADDRA_WIDTH : 4
+-- C_HAS_RSTB : 0
+-- C_RST_PRIORITY_B : CE
+-- C_RSTRAM_B : 0
+-- C_INITB_VAL : 0
+-- C_HAS_ENB : 0
+-- C_HAS_REGCEB : 0
+-- C_USE_BYTE_WEB : 0
+-- C_WEB_WIDTH : 1
+-- C_WRITE_MODE_B : WRITE_FIRST
+-- C_WRITE_WIDTH_B : 512
+-- C_READ_WIDTH_B : 512
+-- C_WRITE_DEPTH_B : 16
+-- C_READ_DEPTH_B : 16
+-- C_ADDRB_WIDTH : 4
+-- C_HAS_MEM_OUTPUT_REGS_A : 0
+-- C_HAS_MEM_OUTPUT_REGS_B : 0
+-- C_HAS_MUX_OUTPUT_REGS_A : 0
+-- C_HAS_MUX_OUTPUT_REGS_B : 0
+-- C_HAS_SOFTECC_INPUT_REGS_A : 0
+-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
+-- C_MUX_PIPELINE_STAGES : 0
+-- C_USE_ECC : 0
+-- C_USE_SOFTECC : 0
+-- C_HAS_INJECTERR : 0
+-- C_SIM_COLLISION_CHECK : ALL
+-- C_COMMON_CLK : 0
+-- C_DISABLE_WARN_BHV_COLL : 0
+-- C_DISABLE_WARN_BHV_RANGE : 0
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY blockMemory_prod IS
+ PORT (
+ --Port A
+ CLKA : IN STD_LOGIC;
+ RSTA : IN STD_LOGIC; --opt port
+ ENA : IN STD_LOGIC; --optional port
+ REGCEA : IN STD_LOGIC; --optional port
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+ DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ --Port B
+ CLKB : IN STD_LOGIC;
+ RSTB : IN STD_LOGIC; --opt port
+ ENB : IN STD_LOGIC; --optional port
+ REGCEB : IN STD_LOGIC; --optional port
+ WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ DINB : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ --ECC
+ INJECTSBITERR : IN STD_LOGIC; --optional port
+ INJECTDBITERR : IN STD_LOGIC; --optional port
+ SBITERR : OUT STD_LOGIC; --optional port
+ DBITERR : OUT STD_LOGIC; --optional port
+ RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+ -- AXI Global Signals
+ S_ACLK : IN STD_LOGIC;
+ S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_AWVALID : IN STD_LOGIC;
+ S_AXI_AWREADY : OUT STD_LOGIC;
+ S_AXI_WDATA : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+ S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ S_AXI_WLAST : IN STD_LOGIC;
+ S_AXI_WVALID : IN STD_LOGIC;
+ S_AXI_WREADY : OUT STD_LOGIC;
+ S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
+ S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_BVALID : OUT STD_LOGIC;
+ S_AXI_BREADY : IN STD_LOGIC;
+
+ -- AXI Full/Lite Slave Read (Write side)
+ S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_ARVALID : IN STD_LOGIC;
+ S_AXI_ARREADY : OUT STD_LOGIC;
+ S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
+ S_AXI_RDATA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+ S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_RLAST : OUT STD_LOGIC;
+ S_AXI_RVALID : OUT STD_LOGIC;
+ S_AXI_RREADY : IN STD_LOGIC;
+
+ -- AXI Full/Lite Sideband Signals
+ S_AXI_INJECTSBITERR : IN STD_LOGIC;
+ S_AXI_INJECTDBITERR : IN STD_LOGIC;
+ S_AXI_SBITERR : OUT STD_LOGIC;
+ S_AXI_DBITERR : OUT STD_LOGIC;
+ S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_ARESETN : IN STD_LOGIC
+
+
+ );
+
+END blockMemory_prod;
+
+
+ARCHITECTURE xilinx OF blockMemory_prod IS
+
+ COMPONENT blockMemory_exdes IS
+ PORT (
+ --Port A
+ RSTA : IN STD_LOGIC; --opt port
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ CLKA : IN STD_LOGIC
+
+
+
+
+ );
+ END COMPONENT;
+
+BEGIN
+
+ bmg0 : blockMemory_exdes
+ PORT MAP (
+ --Port A
+ RSTA => RSTA,
+
+ WEA => WEA,
+ ADDRA => ADDRA,
+
+ DINA => DINA,
+
+ DOUTA => DOUTA,
+
+ CLKA => CLKA
+
+
+
+ );
+END xilinx;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.ucf
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.ucf (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.ucf (revision 5)
@@ -0,0 +1,57 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA" TNM_NET = "CLKA";
+
+TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
+
+################################################################################
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.xdc
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.xdc (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.xdc (revision 5)
@@ -0,0 +1,54 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
+################################################################################
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.vhd (revision 5)
@@ -0,0 +1,166 @@
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: blockMemory_exdes.vhd
+--
+-- Description:
+-- This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY blockMemory_exdes IS
+ PORT (
+ --Inputs - Port A
+ RSTA : IN STD_LOGIC; --opt port
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+ CLKA : IN STD_LOGIC
+
+
+ );
+
+END blockMemory_exdes;
+
+
+ARCHITECTURE xilinx OF blockMemory_exdes IS
+
+ COMPONENT BUFG IS
+ PORT (
+ I : IN STD_ULOGIC;
+ O : OUT STD_ULOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT blockMemory IS
+ PORT (
+ --Port A
+ RSTA : IN STD_LOGIC; --opt port
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+
+ CLKA : IN STD_LOGIC
+
+
+
+ );
+ END COMPONENT;
+
+ SIGNAL CLKA_buf : STD_LOGIC;
+ SIGNAL CLKB_buf : STD_LOGIC;
+ SIGNAL S_ACLK_buf : STD_LOGIC;
+
+BEGIN
+
+ bufg_A : BUFG
+ PORT MAP (
+ I => CLKA,
+ O => CLKA_buf
+ );
+
+
+
+ bmg0 : blockMemory
+ PORT MAP (
+ --Port A
+ RSTA => RSTA,
+
+ WEA => WEA,
+ ADDRA => ADDRA,
+
+ DINA => DINA,
+
+ DOUTA => DOUTA,
+
+ CLKA => CLKA_buf
+
+
+ );
+
+END xilinx;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/random.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/random.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/random.vhd (revision 5)
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+-- Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+ GENERIC ( WIDTH : INTEGER := 32;
+ SEED : INTEGER :=2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+ PROCESS(CLK)
+ VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ VARIABLE TEMP : STD_LOGIC := '0';
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ ELSE
+ IF(EN = '1') THEN
+ TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+ RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+ RAND_TEMP(0) := TEMP;
+ END IF;
+ END IF;
+ END IF;
+ RANDOM_NUM <= RAND_TEMP;
+ END PROCESS;
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/vcs_session.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/vcs_session.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/vcs_session.tcl (revision 5)
@@ -0,0 +1,83 @@
+
+
+
+
+
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG core Demo Testbench
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+# This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+ gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create blockMemory_Group
+gui_list_add_group -id Wave.1 {blockMemory_Group}
+
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simcmds.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simcmds.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simcmds.tcl (revision 5)
@@ -0,0 +1,63 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+
+
+wcfg new
+isim set radix hex
+wave add /blockMemory_tb/status
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA
+run all
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.bat (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_ncsim.sv
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_ncsim.sv (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_ncsim.sv (revision 5)
@@ -0,0 +1,21 @@
+
+
+
+
+
+
+
+
+
+window new WaveWindow -name "Waves for BMG Example Design"
+waveform using "Waves for BMG Example Design"
+
+ waveform add -signals /blockMemory_tb/status
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+console submit -using simulator -wait no "run"
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/ucli_commands.key
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/ucli_commands.key (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/ucli_commands.key (revision 5)
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add blockMemory_tb
+run
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.sh (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_ncsim.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_ncsim.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_ncsim.sh (revision 5)
@@ -0,0 +1,70 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+
+mkdir work
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+ncvhdl -v93 -work work ../../../blockMemory.vhd \
+ ../../example_design/blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work ../random.vhd
+ncvhdl -v93 -work work ../data_gen.vhd
+ncvhdl -v93 -work work ../addr_gen.vhd
+ncvhdl -v93 -work work ../checker.vhd
+ncvhdl -v93 -work work ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work ../blockMemory_synth.vhd
+ncvhdl -v93 -work work ../blockMemory_tb.vhd
+
+echo "Elaborating Design"
+ncelab -access +rwc work.blockMemory_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.blockMemory_tb
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_vcs.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_vcs.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_vcs.sh (revision 5)
@@ -0,0 +1,69 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhdlan ../../../blockMemory.vhd
+vhdlan ../../example_design/blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan ../bmg_tb_pkg.vhd
+vhdlan ../random.vhd
+vhdlan ../data_gen.vhd
+vhdlan ../addr_gen.vhd
+vhdlan ../checker.vhd
+vhdlan ../bmg_stim_gen.vhd
+vhdlan ../blockMemory_synth.vhd
+vhdlan ../blockMemory_tb.vhd
+
+echo "Elaborating Design"
+vcs +vcs+lic+wait -debug blockMemory_tb
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_isim.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_isim.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_isim.bat (revision 5)
@@ -0,0 +1,68 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+::
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+::
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+::
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+::
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::--------------------------------------------------------------------------------
+
+
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhpcomp -work work ..\..\..\blockMemory.vhd
+vhpcomp -work work ..\..\example_design\blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work ..\bmg_tb_pkg.vhd
+vhpcomp -work work ..\random.vhd
+vhpcomp -work work ..\data_gen.vhd
+vhpcomp -work work ..\addr_gen.vhd
+vhpcomp -work work ..\checker.vhd
+vhpcomp -work work ..\bmg_stim_gen.vhd
+vhpcomp -work work ..\blockMemory_synth.vhd
+vhpcomp -work work ..\blockMemory_tb.vhd
+
+fuse work.blockMemory_tb -L unisims -L xilinxcorelib -o blockMemory_tb.exe
+
+
+.\blockMemory_tb.exe -gui -tclbatch simcmds.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_mti.do (revision 5)
@@ -0,0 +1,36 @@
+
+
+
+
+
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+ add wave -noupdate /blockMemory_tb/status
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.do (revision 5)
@@ -0,0 +1,74 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+ vlib work
+vmap work work
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vcom -work work ../../../blockMemory.vhd \
+ ../../example_design/blockMemory_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work ../bmg_tb_pkg.vhd
+vcom -work work ../random.vhd
+vcom -work work ../data_gen.vhd
+vcom -work work ../addr_gen.vhd
+vcom -work work ../checker.vhd
+vcom -work work ../bmg_stim_gen.vhd
+vcom -work work ../blockMemory_synth.vhd
+vcom -work work ../blockMemory_tb.vhd
+
+vsim -novopt -t ps -L XilinxCoreLib -L unisim work.blockMemory_tb
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/data_gen.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/data_gen.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/data_gen.vhd (revision 5)
@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Data Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: data_gen.vhd
+--
+-- Description:
+-- Data Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY DATA_GEN IS
+ GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
+ DOUT_WIDTH : INTEGER := 32;
+ DATA_PART_CNT : INTEGER := 1;
+ SEED : INTEGER := 2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END DATA_GEN;
+
+ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
+ CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
+ SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+ SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
+ SIGNAL LOCAL_CNT : INTEGER :=1;
+ SIGNAL DATA_GEN_I : STD_LOGIC :='0';
+BEGIN
+
+ LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
+ DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
+ DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE (CLK)) THEN
+ IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
+ LOCAL_CNT <=1;
+ ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
+ IF(LOCAL_CNT = 1) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+ RAND_GEN_INST:ENTITY work.RANDOM
+ GENERIC MAP(
+ WIDTH => 8,
+ SEED => (SEED+N)
+ )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DATA_GEN_I,
+ RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
+ );
+ END GENERATE RAND_GEN;
+
+END ARCHITECTURE;
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/addr_gen.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/addr_gen.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/addr_gen.vhd (revision 5)
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+-- Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+ GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
+ RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+ RST_INC : INTEGER := 0);
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ LOAD :IN STD_LOGIC;
+ LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
+ ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
+ );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+ SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+ ADDR_OUT <= ADDR_TEMP;
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ IF(EN='1') THEN
+ IF(LOAD='1') THEN
+ ADDR_TEMP <=LOAD_VALUE;
+ ELSE
+ IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ ADDR_TEMP <= ADDR_TEMP + '1';
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/checker.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/checker.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/checker.vhd (revision 5)
@@ -0,0 +1,161 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Checker
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: checker.vhd
+--
+-- Description:
+-- Checker
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY CHECKER IS
+ GENERIC ( WRITE_WIDTH : INTEGER :=32;
+ READ_WIDTH : INTEGER :=32
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
+ STATUS : OUT STD_LOGIC:= '0'
+ );
+END CHECKER;
+
+ARCHITECTURE CHECKER_ARCH OF CHECKER IS
+ SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL EN_R : STD_LOGIC := '0';
+ SIGNAL EN_2R : STD_LOGIC := '0';
+--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
+--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
+--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
+ CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
+ CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
+ SIGNAL ERR_HOLD : STD_LOGIC :='0';
+ SIGNAL ERR_DET : STD_LOGIC :='0';
+BEGIN
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST= '1') THEN
+ EN_R <= '0';
+ EN_2R <= '0';
+ DATA_IN_R <= (OTHERS=>'0');
+ ELSE
+ EN_R <= EN;
+ EN_2R <= EN_R;
+ DATA_IN_R <= DATA_IN;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
+ DOUT_WIDTH => READ_WIDTH,
+ DATA_PART_CNT => DATA_PART_CNT,
+ SEED => 2
+ )
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ EN => EN_2R,
+ DATA_OUT => EXPECTED_DATA
+ );
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(EN_2R='1') THEN
+ IF(EXPECTED_DATA = DATA_IN_R) THEN
+ ERR_DET<='0';
+ ELSE
+ ERR_DET<= '1';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLK,RST)
+ BEGIN
+ IF(RST='1') THEN
+ ERR_HOLD <= '0';
+ ELSIF(RISING_EDGE(CLK)) THEN
+ ERR_HOLD <= ERR_HOLD OR ERR_DET ;
+ END IF;
+ END PROCESS;
+
+ STATUS <= ERR_HOLD;
+
+END ARCHITECTURE;
+
+
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/vcs_session.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/vcs_session.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/vcs_session.tcl (revision 5)
@@ -0,0 +1,83 @@
+
+
+
+
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG Generator v8.4 Core Demo Testbench
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+# This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+ gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create blockMemory_Group
+gui_list_add_group -id Wave.1 {blockMemory_Group}
+
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simcmds.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simcmds.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simcmds.tcl (revision 5)
@@ -0,0 +1,63 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+
+
+wcfg new
+isim set radix hex
+wave add /blockMemory_tb/status
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA
+ wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA
+run all
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.bat (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_ncsim.sv
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_ncsim.sv (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_ncsim.sv (revision 5)
@@ -0,0 +1,20 @@
+
+
+
+
+
+
+
+
+window new WaveWindow -name "Waves for BMG Example Design"
+waveform using "Waves for BMG Example Design"
+
+
+ waveform add -signals /blockMemory_tb/status
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+console submit -using simulator -wait no "run"
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/ucli_commands.key
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/ucli_commands.key (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/ucli_commands.key (revision 5)
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add blockMemory_tb
+run
+quit
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.sh (revision 5)
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_ncsim.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_ncsim.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_ncsim.sh (revision 5)
@@ -0,0 +1,78 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+mkdir work
+
+
+ncvhdl -v93 -work work ../../implement/results/routed.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work ../random.vhd
+ncvhdl -v93 -work work ../data_gen.vhd
+ncvhdl -v93 -work work ../addr_gen.vhd
+ncvhdl -v93 -work work ../checker.vhd
+ncvhdl -v93 -work work ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work ../blockMemory_synth.vhd
+ncvhdl -v93 -work work ../blockMemory_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :blockMemory_synth_inst:BMG_PORT,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+
+echo "Elaborating Design"
+ncelab -access +rwc -sdf_cmd_file sdf.cmd $work.blockMemory_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.blockMemory_tb
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_vcs.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_vcs.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_vcs.sh (revision 5)
@@ -0,0 +1,70 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhdlan ../../implement/results/routed.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan ../bmg_tb_pkg.vhd
+vhdlan ../random.vhd
+vhdlan ../data_gen.vhd
+vhdlan ../addr_gen.vhd
+vhdlan ../checker.vhd
+vhdlan ../bmg_stim_gen.vhd
+vhdlan ../blockMemory_synth.vhd
+vhdlan ../blockMemory_tb.vhd
+
+
+echo "Elaborating Design"
+vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_isim.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_isim.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_isim.bat (revision 5)
@@ -0,0 +1,67 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+::
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+::
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+::
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+::
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::--------------------------------------------------------------------------------
+
+
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vhpcomp -work work ..\..\implement\results\routed.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work ..\bmg_tb_pkg.vhd
+vhpcomp -work work ..\random.vhd
+vhpcomp -work work ..\data_gen.vhd
+vhpcomp -work work ..\addr_gen.vhd
+vhpcomp -work work ..\checker.vhd
+vhpcomp -work work ..\bmg_stim_gen.vhd
+vhpcomp -work work ..\blockMemory_synth.vhd
+vhpcomp -work work ..\blockMemory_tb.vhd
+
+
+ fuse -L simprim work.blockMemory_tb -o blockMemory_tb.exe
+
+.\blockMemory_tb.exe -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_mti.do (revision 5)
@@ -0,0 +1,36 @@
+
+
+
+
+
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+
+ add wave -noupdate /blockMemory_tb/status
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA
+ add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.do
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.do (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.do (revision 5)
@@ -0,0 +1,75 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+
+vlib work
+vmap work work
+
+echo "Compiling Core VHDL UNISIM/Behavioral model"
+vcom -work work ../../implement/results/routed.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work ../bmg_tb_pkg.vhd
+vcom -work work ../random.vhd
+vcom -work work ../data_gen.vhd
+vcom -work work ../addr_gen.vhd
+vcom -work work ../checker.vhd
+vcom -work work ../bmg_stim_gen.vhd
+vcom -work work ../blockMemory_synth.vhd
+vcom -work work ../blockMemory_tb.vhd
+
+ vsim -novopt -t ps -L simprim +transport_int_delays -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=../../implement/results/routed.sdf $work.blockMemory_tb -novopt
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_tb.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_tb.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_tb.vhd (revision 5)
@@ -0,0 +1,129 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: blockMemory_tb.vhd
+-- Description:
+-- Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY blockMemory_tb IS
+END ENTITY;
+
+
+ARCHITECTURE blockMemory_tb_ARCH OF blockMemory_tb IS
+ SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL CLK : STD_LOGIC := '1';
+ SIGNAL RESET : STD_LOGIC;
+
+ BEGIN
+
+
+ CLK_GEN: PROCESS BEGIN
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ END PROCESS;
+
+ RST_GEN: PROCESS BEGIN
+ RESET <= '1';
+ WAIT FOR 1000 NS;
+ RESET <= '0';
+ WAIT;
+ END PROCESS;
+
+
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+-- ASSERT FALSE
+-- REPORT "END SIMULATION TIME REACHED"
+-- SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+ WAIT UNTIL STATUS(8)='1';
+ IF( STATUS(7 downto 0)/="0") THEN
+ ASSERT false
+ REPORT "Simulation Failed"
+ SEVERITY FAILURE;
+ ELSE
+ ASSERT false
+ REPORT "Simulation Complete"
+ SEVERITY FAILURE;
+ END IF;
+END PROCESS;
+
+ blockMemory_synth_inst:ENTITY work.blockMemory_synth
+ PORT MAP(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+ STATUS => STATUS
+ );
+
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_synth.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_synth.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_synth.vhd (revision 5)
@@ -0,0 +1,289 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: blockMemory_synth.vhd
+--
+-- Description:
+-- Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY blockMemory_synth IS
+PORT(
+ CLK_IN : IN STD_LOGIC;
+ RESET_IN : IN STD_LOGIC;
+ STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
+ );
+END ENTITY;
+
+ARCHITECTURE blockMemory_synth_ARCH OF blockMemory_synth IS
+
+
+COMPONENT blockMemory_exdes
+ PORT (
+ --Inputs - Port A
+ RSTA : IN STD_LOGIC; --opt port
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+ DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+ CLKA : IN STD_LOGIC
+
+
+ );
+
+END COMPONENT;
+
+
+ SIGNAL CLKA: STD_LOGIC := '0';
+ SIGNAL RSTA: STD_LOGIC := '0';
+ SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA: STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA_R: STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DOUTA: STD_LOGIC_VECTOR(511 DOWNTO 0);
+ SIGNAL CHECKER_EN : STD_LOGIC:='0';
+ SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+ SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+ SIGNAL clk_in_i: STD_LOGIC;
+
+ SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+ SIGNAL ITER_R0 : STD_LOGIC := '0';
+ SIGNAL ITER_R1 : STD_LOGIC := '0';
+ SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+ SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+ BEGIN
+
+-- clk_buf: bufg
+-- PORT map(
+-- i => CLK_IN,
+-- o => clk_in_i
+-- );
+ clk_in_i <= CLK_IN;
+ CLKA <= clk_in_i;
+
+ RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+ PROCESS(clk_in_i)
+ BEGIN
+ IF(RISING_EDGE(clk_in_i)) THEN
+ RESET_SYNC_R1 <= RESET_IN;
+ RESET_SYNC_R2 <= RESET_SYNC_R1;
+ RESET_SYNC_R3 <= RESET_SYNC_R2;
+ END IF;
+ END PROCESS;
+
+
+PROCESS(CLKA)
+BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ISSUE_FLAG_STATUS<= (OTHERS => '0');
+ ELSE
+ ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+ END IF;
+ END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+ BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
+ GENERIC MAP (
+ WRITE_WIDTH => 512,
+ READ_WIDTH => 512 )
+ PORT MAP (
+ CLK => CLKA,
+ RST => RSTA,
+ EN => CHECKER_EN_R,
+ DATA_IN => DOUTA,
+ STATUS => ISSUE_FLAG(0)
+ );
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RSTA='1') THEN
+ CHECKER_EN_R <= '0';
+ ELSE
+ CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+ PORT MAP(
+ CLK => clk_in_i,
+ RST => RSTA,
+ ADDRA => ADDRA,
+ DINA => DINA,
+ WEA => WEA,
+ CHECK_DATA => CHECKER_EN
+ );
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STATUS(8) <= '0';
+ iter_r2 <= '0';
+ iter_r1 <= '0';
+ iter_r0 <= '0';
+ ELSE
+ STATUS(8) <= iter_r2;
+ iter_r2 <= iter_r1;
+ iter_r1 <= iter_r0;
+ iter_r0 <= STIMULUS_FLOW(8);
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STIMULUS_FLOW <= (OTHERS => '0');
+ ELSIF(WEA(0)='1') THEN
+ STIMULUS_FLOW <= STIMULUS_FLOW+1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ WEA_R <= (OTHERS=>'0') AFTER 50 ns;
+ DINA_R <= (OTHERS=>'0') AFTER 50 ns;
+
+
+ ELSE
+ WEA_R <= WEA AFTER 50 ns;
+ DINA_R <= DINA AFTER 50 ns;
+
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+ ELSE
+ ADDRA_R <= ADDRA AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_PORT: blockMemory_exdes PORT MAP (
+ --Port A
+ RSTA => RSTA,
+ WEA => WEA_R,
+ ADDRA => ADDRA_R,
+ DINA => DINA_R,
+ DOUTA => DOUTA,
+ CLKA => CLKA
+
+ );
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_stim_gen.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_stim_gen.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_stim_gen.vhd (revision 5)
@@ -0,0 +1,243 @@
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Stimulus Generator For Single Port Ram
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+-- Stimulus Generation For SRAM
+-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
+-- simulation ends
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC_SRAM IS
+ PORT(
+ Q : OUT STD_LOGIC;
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ D : IN STD_LOGIC
+ );
+END REGISTER_LOGIC_SRAM;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
+ SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+ Q <= Q_O;
+ FF_BEH: PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST ='1') THEN
+ Q_O <= '0';
+ ELSE
+ Q_O <= D;
+ END IF;
+ END IF;
+ END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ DINA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0');
+ WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
+ CHECK_DATA: OUT STD_LOGIC:='0'
+ );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+ CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(512,512);
+ SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA_INT : STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DO_WRITE : STD_LOGIC := '0';
+ SIGNAL DO_READ : STD_LOGIC := '0';
+ SIGNAL COUNT_NO : INTEGER :=0;
+ SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
+BEGIN
+ WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
+ READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
+ ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
+ DINA <= DINA_INT ;
+
+ CHECK_DATA <= DO_READ;
+
+RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 16
+ )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DO_READ,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => READ_ADDR
+ );
+
+WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 16 )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DO_WRITE,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => WRITE_ADDR
+ );
+
+WR_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP (
+ DATA_GEN_WIDTH => 512,
+ DOUT_WIDTH => 512,
+ DATA_PART_CNT => DATA_PART_CNT_A,
+ SEED => 2
+ )
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ EN => DO_WRITE,
+ DATA_OUT => DINA_INT
+ );
+
+WR_RD_PROCESS: PROCESS (CLK)
+BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ DO_WRITE <= '0';
+ DO_READ <= '0';
+ COUNT_NO <= 0 ;
+ ELSIF(COUNT_NO < 4) THEN
+ DO_WRITE <= '1';
+ DO_READ <= '0';
+ COUNT_NO <= COUNT_NO + 1;
+ ELSIF(COUNT_NO< 8) THEN
+ DO_WRITE <= '0';
+ DO_READ <= '1';
+ COUNT_NO <= COUNT_NO + 1;
+ ELSIF(COUNT_NO=8) THEN
+ DO_WRITE <= '0';
+ DO_READ <= '0';
+ COUNT_NO <= 0 ;
+ END IF;
+ END IF;
+END PROCESS;
+
+BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
+BEGIN
+ DFF_RIGHT: IF I=0 GENERATE
+ BEGIN
+ SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
+ PORT MAP(
+ Q => DO_READ_REG(0),
+ CLK => CLK,
+ RST => RST,
+ D => DO_READ
+ );
+ END GENERATE DFF_RIGHT;
+ DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
+ BEGIN
+ SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
+ PORT MAP(
+ Q => DO_READ_REG(I),
+ CLK => CLK,
+ RST => RST,
+ D => DO_READ_REG(I-1)
+ );
+ END GENERATE DFF_OTHERS;
+END GENERATE BEGIN_SHIFT_REG;
+
+ WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
+
+END ARCHITECTURE;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_tb_pkg.vhd
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_tb_pkg.vhd (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_tb_pkg.vhd (revision 5)
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_1 Core - Testbench Package
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+-- BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER;
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE DIV : INTEGER;
+ BEGIN
+ DIV := DATA_VALUE/DIVISOR;
+ IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+ DIV := DIV+1;
+ END IF;
+ RETURN DIV;
+ END DIVROUNDUP;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE : STD_LOGIC)
+ RETURN STD_LOGIC IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE RETVAL : INTEGER := 0;
+ BEGIN
+ IF CONDITION=FALSE THEN
+ RETVAL:=FALSE_CASE;
+ ELSE
+ RETVAL:=TRUE_CASE;
+ END IF;
+ RETURN RETVAL;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE : STRING)
+ RETURN STRING IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ -------------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE WIDTH : INTEGER := 0;
+ VARIABLE CNT : INTEGER := 1;
+ BEGIN
+ IF (DATA_VALUE <= 1) THEN
+ WIDTH := 1;
+ ELSE
+ WHILE (CNT < DATA_VALUE) LOOP
+ WIDTH := WIDTH + 1;
+ CNT := CNT *2;
+ END LOOP;
+ END IF;
+ RETURN WIDTH;
+ END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (revision 5)
@@ -0,0 +1,237 @@
+
+
+blk_mem_gen_v7_1_vinfo
+
+
+
+
+ Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.1 + Release: ISE 14.1 / Vivado 2012.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE + 2.2 Vivado +3. Supported Devices + 3.1 ISE + 3.2 Vivado +4. Resolved Issues + 4.1 ISE + 4.2 Vivado +5. Known Issues + 5.1 ISE + 5.2 Vivado +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 +solution. For the latest core updates, see the product page at: + + www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + + 2.2 Vivado + + - 2012.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + +................................................................................ +3. SUPPORTED DEVICES + + + 3.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 3.2 Vivado + All 7 Series devices + Zynq-7000 devices + + +................................................................................ +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.1: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ +5. KNOWN ISSUES + + + 5.1 ISE + + The following are known issues for v7.1 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + + +................................................................................ +6. TECHNICAL SUPPORT + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + ++ + Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== --- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf (nonexistent) +++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/blk_mem_gen_v7_1_readme.txt
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/blk_mem_gen_v7_1_readme.txt (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/blk_mem_gen_v7_1_readme.txt (revision 5)
@@ -0,0 +1,226 @@
+ Core name: Xilinx LogiCORE Block Memory Generator
+ Version: 7.1
+ Release: ISE 14.1 / Vivado 2012.1
+ Release Date: April 24, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+ 2.1 ISE
+ 2.2 Vivado
+3. Supported Devices
+ 3.1 ISE
+ 3.2 Vivado
+4. Resolved Issues
+ 4.1 ISE
+ 4.2 Vivado
+5. Known Issues
+ 5.1 ISE
+ 5.2 Vivado
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+................................................................................
+2. NEW FEATURES
+
+
+ 2.1 ISE
+
+ - ISE 14.1 software support
+ - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,
+ and Automotive Zynq device support
+
+
+ 2.2 Vivado
+
+ - 2012.1 software support
+ - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,
+ and Automotive Zynq device support
+
+
+................................................................................
+3. SUPPORTED DEVICES
+
+
+ 3.1 ISE
+
+ The following device families are supported by the core for this release.
+
+ All 7 Series devices
+ Zynq-7000 devices
+ All Virtex-6 devices
+ All Spartan-6 devices
+ All Virtex-5 devices
+ All Spartan-3 devices
+ All Virtex-4 devices
+
+
+ 3.2 Vivado
+ All 7 Series devices
+ Zynq-7000 devices
+
+
+................................................................................
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.1:
+
+ 4.1 ISE
+
+
+ 4.2 Vivado
+
+
+................................................................................
+5. KNOWN ISSUES
+
+
+ 5.1 ISE
+
+ The following are known issues for v7.1 of this core at time of release:
+
+ 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
+ Work around: The user must review the possible scenarios that causes the collission and revise
+ their design to avoid those situations.
+ - CR588505
+
+ Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
+ Write Mode = Read First in conjunction with asynchronous clocking
+
+ 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+
+ 3. Core does not generate for large memories. Depending on the
+ machine the ISE CORE Generator software runs on, the maximum size of the memory that
+ can be generated will vary. For example, a Dual Pentium-4 server
+ with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+ - CR 415768
+ - AR 24034
+
+
+ 5.2 Vivado
+
+ The most recent information, including known issues, workarounds, and resolutions for
+ this version is provided in the IP Release Notes User Guide located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+
+................................................................................
+6. TECHNICAL SUPPORT
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY
+
+Date By Version Description
+================================================================================
+04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
+06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
+07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
+03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
+12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
+ Device support; Automotive Spartan 3A
+ DSP device support
+09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
+06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
+04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
+09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
+03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
+10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
+07/2007 Xilinx, Inc. 2.5 Revised to v2.5
+04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
+02/2007 Xilinx, Inc. 2.4 Revised to v2.4
+11/2006 Xilinx, Inc. 2.3 Revised to v2.3
+09/2006 Xilinx, Inc. 2.2 Revised to v2.2
+06/2006 Xilinx, Inc. 2.1 Revised to v2.1
+01/2006 Xilinx, Inc. 1.1 Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved.
+
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
+ injury, or severe property or environmental damage
+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
+ liability of any use of Xilinx products in Critical
+ Applications, subject only to applicable laws and
+ regulations governing limitations on product liability.
+
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
+
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.bat (revision 5)
@@ -0,0 +1,48 @@
+
+
+
+
+
+
+
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy blockMemory_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\blockMemory.ngc results\
+
+
+rem Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\blockMemory_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes
+
+echo 'Running map'
+map blockMemory_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.tcl (revision 5)
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc3s500efg320-5
+set projName blockMemory
+set design blockMemory
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module blockMemory_exdes
+add_files -norecurse {../../example_design/blockMemory_exdes.vhd}
+add_files -norecurse {./blockMemory.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc}
+set_property top blockMemory_exdes [get_property srcset [current_run]]
+synth_design
+opt_design
+place_design
+route_design
+write_sdf -rename_top_module blockMemory_exdes -file routed.sdf
+write_vhdl -mode sim routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.bat (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\blockMemory.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.sh (revision 5)
@@ -0,0 +1,48 @@
+
+
+
+
+
+
+
+
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp blockMemory_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../blockMemory.ngc results/
+
+# Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/blockMemory_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes
+
+echo 'Running map'
+map blockMemory_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.scr
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.scr (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.scr (revision 5)
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent blockMemory_exdes
+-p xc3s500e-fg320-5
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn blockMemory_exdes
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.bat
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.bat (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.bat (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\blockMemory.ngc .
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.sh (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../blockMemory.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.prj
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.prj (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.prj (revision 5)
@@ -0,0 +1 @@
+work ../example_design/blockMemory_exdes.vhd
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.sh
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.sh (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.sh (revision 5)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../blockMemory.ngc .
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.tcl
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.tcl (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.tcl (revision 5)
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc3s500efg320-5
+set projName blockMemory
+set design blockMemory
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module blockMemory_exdes
+add_files -norecurse {../../example_design/blockMemory_exdes.vhd}
+add_files -norecurse {./blockMemory.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc}
+set_property top blockMemory_exdes [get_property srcset [current_run]]
+synth_design
+opt_design
+place_design
+route_design
+write_sdf -rename_top_module blockMemory_exdes -file routed.sdf
+write_vhdl -mode sim routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory (revision 5)
mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.v
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.v (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.v (revision 5)
@@ -0,0 +1,180 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used solely *
+* for design, simulation, implementation and creation of design files *
+* limited to Xilinx devices or technologies. Use with non-Xilinx *
+* devices or technologies is expressly prohibited and immediately *
+* terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
+* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
+* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
+* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
+* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
+* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
+* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
+* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
+* PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support appliances, *
+* devices, or systems. Use in such applications are expressly *
+* prohibited. *
+* *
+* (c) Copyright 1995-2013 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// You must compile the wrapper file blockMemory.v when simulating
+// the core, blockMemory. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module blockMemory(
+ clka,
+ rsta,
+ wea,
+ addra,
+ dina,
+ douta
+);
+
+input clka;
+input rsta;
+input [0 : 0] wea;
+input [3 : 0] addra;
+input [511 : 0] dina;
+output [511 : 0] douta;
+
+// synthesis translate_off
+
+ BLK_MEM_GEN_V7_1 #(
+ .C_ADDRA_WIDTH(4),
+ .C_ADDRB_WIDTH(4),
+ .C_ALGORITHM(0),
+ .C_AXI_ID_WIDTH(4),
+ .C_AXI_SLAVE_TYPE(0),
+ .C_AXI_TYPE(1),
+ .C_BYTE_SIZE(9),
+ .C_COMMON_CLK(0),
+ .C_DEFAULT_DATA("0"),
+ .C_DISABLE_WARN_BHV_COLL(0),
+ .C_DISABLE_WARN_BHV_RANGE(0),
+ .C_ENABLE_32BIT_ADDRESS(0),
+ .C_FAMILY("spartan3"),
+ .C_HAS_AXI_ID(0),
+ .C_HAS_ENA(0),
+ .C_HAS_ENB(0),
+ .C_HAS_INJECTERR(0),
+ .C_HAS_MEM_OUTPUT_REGS_A(0),
+ .C_HAS_MEM_OUTPUT_REGS_B(0),
+ .C_HAS_MUX_OUTPUT_REGS_A(0),
+ .C_HAS_MUX_OUTPUT_REGS_B(0),
+ .C_HAS_REGCEA(0),
+ .C_HAS_REGCEB(0),
+ .C_HAS_RSTA(1),
+ .C_HAS_RSTB(0),
+ .C_HAS_SOFTECC_INPUT_REGS_A(0),
+ .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+ .C_INIT_FILE_NAME("no_coe_file_loaded"),
+ .C_INITA_VAL("0"),
+ .C_INITB_VAL("0"),
+ .C_INTERFACE_TYPE(0),
+ .C_LOAD_INIT_FILE(0),
+ .C_MEM_TYPE(0),
+ .C_MUX_PIPELINE_STAGES(0),
+ .C_PRIM_TYPE(6),
+ .C_READ_DEPTH_A(16),
+ .C_READ_DEPTH_B(16),
+ .C_READ_WIDTH_A(512),
+ .C_READ_WIDTH_B(512),
+ .C_RST_PRIORITY_A("CE"),
+ .C_RST_PRIORITY_B("CE"),
+ .C_RST_TYPE("SYNC"),
+ .C_RSTRAM_A(0),
+ .C_RSTRAM_B(0),
+ .C_SIM_COLLISION_CHECK("ALL"),
+ .C_USE_BYTE_WEA(0),
+ .C_USE_BYTE_WEB(0),
+ .C_USE_DEFAULT_DATA(0),
+ .C_USE_ECC(0),
+ .C_USE_SOFTECC(0),
+ .C_WEA_WIDTH(1),
+ .C_WEB_WIDTH(1),
+ .C_WRITE_DEPTH_A(16),
+ .C_WRITE_DEPTH_B(16),
+ .C_WRITE_MODE_A("READ_FIRST"),
+ .C_WRITE_MODE_B("WRITE_FIRST"),
+ .C_WRITE_WIDTH_A(512),
+ .C_WRITE_WIDTH_B(512),
+ .C_XDEVICEFAMILY("spartan3e")
+ )
+ inst (
+ .CLKA(clka),
+ .RSTA(rsta),
+ .WEA(wea),
+ .ADDRA(addra),
+ .DINA(dina),
+ .DOUTA(douta),
+ .ENA(),
+ .REGCEA(),
+ .CLKB(),
+ .RSTB(),
+ .ENB(),
+ .REGCEB(),
+ .WEB(),
+ .ADDRB(),
+ .DINB(),
+ .DOUTB(),
+ .INJECTSBITERR(),
+ .INJECTDBITERR(),
+ .SBITERR(),
+ .DBITERR(),
+ .RDADDRECC(),
+ .S_ACLK(),
+ .S_ARESETN(),
+ .S_AXI_AWID(),
+ .S_AXI_AWADDR(),
+ .S_AXI_AWLEN(),
+ .S_AXI_AWSIZE(),
+ .S_AXI_AWBURST(),
+ .S_AXI_AWVALID(),
+ .S_AXI_AWREADY(),
+ .S_AXI_WDATA(),
+ .S_AXI_WSTRB(),
+ .S_AXI_WLAST(),
+ .S_AXI_WVALID(),
+ .S_AXI_WREADY(),
+ .S_AXI_BID(),
+ .S_AXI_BRESP(),
+ .S_AXI_BVALID(),
+ .S_AXI_BREADY(),
+ .S_AXI_ARID(),
+ .S_AXI_ARADDR(),
+ .S_AXI_ARLEN(),
+ .S_AXI_ARSIZE(),
+ .S_AXI_ARBURST(),
+ .S_AXI_ARVALID(),
+ .S_AXI_ARREADY(),
+ .S_AXI_RID(),
+ .S_AXI_RDATA(),
+ .S_AXI_RRESP(),
+ .S_AXI_RLAST(),
+ .S_AXI_RVALID(),
+ .S_AXI_RREADY(),
+ .S_AXI_INJECTSBITERR(),
+ .S_AXI_INJECTDBITERR(),
+ .S_AXI_SBITERR(),
+ .S_AXI_DBITERR(),
+ .S_AXI_RDADDRECC()
+ );
+
+// synthesis translate_on
+
+endmodule
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ncf
===================================================================
Index: mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ngc
===================================================================
--- mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ngc (nonexistent)
+++ mod_mult_exp/trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ngc (revision 5)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$d3`44<,[o}e~g`n;"2*73>(-80!?0123456382:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789;87<4FNQWW>WC@KLK7<7>11292>LHW]]0YIJMJB=294;76380BB][[:SQWE96=87;:7<4FNQWW>WUSJ5:1<3??;08JJUSS2~oj0=4?>008770187758c3:y><=kig203)0753=0BB][[:@FGVD:4294:>6:5IORVP?GCL[H7?7>11097>LHW]]0OE]O33;2=54=32@D[YY4KIQ@?7?699;1?6D@_UU8b`atf4:0;2<<44;MVPUSS2ME[M1=50?31?10>586?2>1CXZ_UU8Q@DBCZLIH0>4?>078144=AGZ^X7JFN@>654<768?09<<5IORVP?BNFK6>=<4?>078144=AGZ^X7jfn`>654<768=09<<5OTVSQQ:1<23>36:3E^X][[:EMVPG:2980;2<945009KPRW]]0ocxzn<432>586:2?<6D@_UU8TAD:2>3:5=?5:7;KMTPR=_LH79;4?>008=?OIX\^1MIJ]A=:94;75300BB][[:@FGVG:?29437LJKR@>3:==FLMXJ0<07;@FGVD:56h1JHI\N<283:==FLMXJ0>07;@FGVD:3611JHI\N<4<;?DBCZH6=255NDEPB828f3HNO^L27:1<;?DBCZH63255NDEPA858?3HNO^O2>>99B@ATE4;4j7LJKRC>0>58?3HNO^O2<>99B@ATE4=437LJKRC>6:==FLMXI0;07;@FGVG:06h1JHI\M<983:==FLMXI050<;@NO53=EEDUBBKAPAEFQAVUXZHDLI55MUR]JJCI6:2ICINEPLHAFJVCX\PZN86MCK148GIM609<0OAE=7178GIM5P11H@F0OAEN5:AOOD703JF@M1H@FO>D968GIME=2IGGO?:;BNHG43EKCM\THDXFDD78GIMAP11H@FHW192:?FIJE@^_II?;;BMQAZABFLXJXDAA_HLEK2=DZLK_II94DCKWAWT13MCJ0=08;EKB8469?2NBM1?>>69GMD:6:7=0HDO312<4?AOF48>5;6JFA=36:2=CAH6::394DHC?52803MCJ0<617:FJE97>6?1OEL2>>69GMD:587=0HDO320<4?AOF4;85;6JFA=00:2=CAH698394DHC?60803MCJ0?817:FJE9406>1OEL2=8?58@LG;:04=7IGN<3<4?AOF4::556JFA=12>5803MCJ0>?16:FJE959>2NBM1:16:FJE939>2NBM1816:FJE919>2NBM1616:FJE9?9>2NBN1>17:FJF9776>1OEO2>1?58@LD;9;4<7IGM<01=3>BNJ5;?2:5KIC>21;169GMG:617<0HDL31?58@LD;:94<7IGM<33=3>BNJ5892:5KIC>17;1908;EKA8739?2NBN1<9>69GMG:5?7=0HDL329<4?AOE4;35:6JFB=0=3>BNJ59;245KIC>05?69?2NBN1=>>79GMG:46?1OEO2;>79GMG:26?1OEO29>79GMG:06?1OEO27>79GMG:>6>1OECO30?;8@LHF48:;245KIOC?557912NBBL2>03<:?AOII5;;?374DHLB8463601OECO3117==>BNFH6:<;06;EKME977?730HD@N<02;:<=CAGK7==718:FJJD:68730HD@N<033:<=CAGK7=19:FJJD:69;427IGAA=327;?89GMKG;98?556JFN@>2538>3MCEM1?>7?;8@LHF48;3245KIOC?54?902NBBL2>1?;8@LHF488;245KIOC?577912NBBL2>23<:?AOII5;9?374DHLB8443601OECO3137==>BNFH6:>;06;EKME975?730HD@N<00;:<=CAGK7=?718:FJJD:6:730HD@N<013:<=CAGK7=>?19:FJJD:6;;427IGAA=307;?89GMKG;9:?556JFN@>2738>3MCEM1?<7?;8@LHF4893245KIOC?56?902NBBL2>3?;8@LHF48>;245KIOC?517912NBBL2>43<:?AOII5;??374DHLB8423601OECO3157==>BNFH6:8;06;EKME973?730HD@N<06;:<=CAGK7=9718:FJJD:6<730HD@N<073:<=CAGK7=8?19:FJJD:6=;427IGAA=367;?89GMKG;9556JFN@>2138>3MCEM1?:7?;8@LHF48?3245KIOC?50?902NBBL2>5?;8@LHF48<;245KIOC?537912NBBL2>63<:?AOII5;=?374DHLB8403601OECO3177==>BNFH6::;06;EKME971?730HD@N<04;:<=CAGK7=;718:FJJD:6>730HD@N<053:<=CAGK7=:?19:FJJD:6?;427IGAA=347;?89GMKG;9>?556JFN@>2338>3MCEM1?87?;8@LHF48=3245KIOC?52?902NBBL2>7?;8@LHF482;245KIOC?5=7912NBBL2>83<:?AOII5;3?374DHLB84>3601OECO3197==>BNFH6:4;06;EKME97??730HD@N<0:;:<=CAGK7=5718:FJJD:60730HD@N<0;3:<=CAGK7=4?19:FJJD:61;427IGAA=3:7;?89GMKG;90?556JFN@>2=38>3MCEM1?67?;8@LHF4833245KIOC?5902NBBL2>9?58@LHF48427IGAA=034;?>>89GMKG;:98556JFN@>1468>3MCEM14?;8@LHF4;:>245KIOC?650912NBBL2=06<:?AOII58;4374DHLB876>611OECO321<:?AOII58:<374DHLB8776601OECO3200==>BNFH69=>06;EKME946<730HD@N<336:<=CAGK7><819:FJJD:59>427IGAA=02<;?99GMKG;:8427IGAA=014;?>89GMKG;:;8556JFN@>1668>3MCEM1<=4?;8@LHF4;8>245KIOC?670912NBBL2=26<:?AOII5894374DHLB874>611OECO323<:?AOII588<374DHLB8756601OECO3220==>BNFH69?>06;EKME944<730HD@N<316:<=CAGK7>>819:FJJD:5;>427IGAA=00<;?99GMKG;::427IGAA=074;?>89GMKG;:=8556JFN@>1068>3MCEM1<;4?;8@LHF4;>>245KIOC?610912NBBL2=46<:?AOII58?4374DHLB872>611OECO325<:?AOII58><374DHLB8736601OECO3240==>BNFH699>06;EKME942<730HD@N<376:<=CAGK7>8819:FJJD:5=>427IGAA=06<;?99GMKG;:<427IGAA=054;?>89GMKG;:?8556JFN@>1268>3MCEM1<94?;8@LHF4;<>245KIOC?630912NBBL2=66<:?AOII58=4374DHLB870>611OECO327<:?AOII58<<374DHLB8716601OECO3260==>BNFH69;>06;EKME940<730HD@N<356:<=CAGK7>:819:FJJD:5?>427IGAA=04<;?99GMKG;:>427IGAA=0;4;?>89GMKG;:18556JFN@>1<68>3MCEM1<74?;8@LHF4;2>245KIOC?6=0912NBBL2=86<:?AOII5834374DHLB87>>611OECO329<:?AOII582<374DHLB87?6601OECO3280==>BNFH695>06;EKME94><730HD@N<3;6:<=CAGK7>4819:FJJD:51>427IGAA=0:<;?99GMKG;:04<7IGAA=0==>BNFH68<=06;EKME9579730HD@N<221:<=CAGK7?==19:FJJD:48=427IGAA=131;?>9>89GMKG;;9=556JFN@>04=8>3MCEM1=?9?:8@LHF4::556JFN@>0558>3MCEM1=>1?;8@LHF4:;9245KIOC?745912NBBL2<15<:?AOII59:9374DHLB8671601OECO3305==>BNFH68=506;EKME9561720HD@N<23==>BNFH68>=06;EKME9559730HD@N<201:<=CAGK7??=19:FJJD:4:=427IGAA=111;?<9>89GMKG;;;=556JFN@>06=8>3MCEM1==9?:8@LHF4:8556JFN@>0758>3MCEM1=<1?;8@LHF4:99245KIOC?765912NBBL2<35<:?AOII5989374DHLB8651601OECO3325==>BNFH68?506;EKME9541720HD@N<21==>BNFH688=06;EKME9539730HD@N<261:<=CAGK7?9=19:FJJD:4<=427IGAA=171;?:9>89GMKG;;==556JFN@>00=8>3MCEM1=;9?:8@LHF4:>556JFN@>0158>3MCEM1=:1?;8@LHF4:?9245KIOC?705912NBBL2<55<:?AOII59>9374DHLB8631601OECO3345==>BNFH689506;EKME9521720HD@N<27==>BNFH68:=06;EKME9519730HD@N<241:<=CAGK7?;=19:FJJD:4>=427IGAA=151;?89>89GMKG;;?=556JFN@>02=8>3MCEM1=99?:8@LHF4:<556JFN@>0358>3MCEM1=81?;8@LHF4:=9245KIOC?725912NBBL2<75<:?AOII59<9374DHLB8611601OECO3365==>BNFH68;506;EKME9501720HD@N<25==>BNFH684=06;EKME95?9730HD@N<2:1:<=CAGK7?5=19:FJJD:40=427IGAA=1;1;?69>89GMKG;;1=556JFN@>0<=8>3MCEM1=79?:8@LHF4:2556JFN@>0=58>3MCEM1=61?;8@LHF4:39245KIOC?7<5912NBBL2<95<:?AOII5929374DHLB86?1601OECO3385==>BNFH685506;EKME95>1720HD@N<2;=3>BNFH68245KIOC?056912NBBL2;00<:?AOII5>;>374DHLB8164601OECO3416==>BNFH6?<806;EKME927>730HD@N<524:<=CAGK78=619:FJJD:380437IGAA=63:<=CAGK78<>19:FJJD:398427IGAA=626;?89GMKG;<8>556JFN@>7508>3MCEM1:>6?;8@LHF4=;<245KIOC?04>912NBBL2;18<;?AOII5>:245KIOC?076912NBBL2;20<:?AOII5>9>374DHLB8144601OECO3436==>BNFH6?>806;EKME925>730HD@N<504:<=CAGK78?619:FJJD:3:0437IGAA=61:<=CAGK78>>19:FJJD:3;8427IGAA=606;?89GMKG;<:>556JFN@>7708>3MCEM1:<6?;8@LHF4=9<245KIOC?06>912NBBL2;38<;?AOII5>8245KIOC?016912NBBL2;40<:?AOII5>?>374DHLB8124601OECO3456==>BNFH6?8806;EKME923>730HD@N<564:<=CAGK789619:FJJD:3<0437IGAA=67:<=CAGK788>19:FJJD:3=8427IGAA=666;?89GMKG;<<>556JFN@>7108>3MCEM1::6?;8@LHF4=?<245KIOC?00>912NBBL2;58<;?AOII5>>245KIOC?036912NBBL2;60<:?AOII5>=>374DHLB8104601OECO3476==>BNFH6?:806;EKME921>730HD@N<544:<=CAGK78;619:FJJD:3>0437IGAA=65:<=CAGK78:>19:FJJD:3?8427IGAA=646;?89GMKG;<>>556JFN@>7308>3MCEM1:86?;8@LHF4==<245KIOC?02>912NBBL2;78<;?AOII5><245KIOC?0=6912NBBL2;80<:?AOII5>3>374DHLB81>4601OECO3496==>BNFH6?4806;EKME92?>730HD@N<5:4:<=CAGK785619:FJJD:300437IGAA=6;:<=CAGK784>19:FJJD:318427IGAA=6:6;?89GMKG;<0>556JFN@>7=08>3MCEM1:66?;8@LHF4=3<245KIOC?0<>912NBBL2;98<;?AOII5>22:5KIOC?0;??>89GMKG;=9;556JFN@>6478>3MCEM1;?3?;8@LHF4<:?245KIOC?153912NBBL2:07<:?AOII5?;;374DHLB806?601OECO351;=<>BNFH6><374DHLB80776k1OECO350394;?>99GMKG;=8437IGAA=71:==CAGK79>07;EKME933611OECO354<;?AOII5?=255KIOC?128?3MCEM1;7>99GMKG;=04<7IGAA=7=<>BNFH6=<364DHLB837902NBBL292?:8@LHF4?9546JFN@>50;>720HD@N<75=<>BNFH6=4364DHLB83?9?2NBBL29>99GMKG;?9437IGAA=52:==CAGK7;?07;EKME914611OECO375<;?AOII5=>255KIOC?338?3MCEM198>99GMKG;?1437IGAA=5::2=CAGK7;364DHLB8=6902NBBL271?:8@LHF418546JFN@>;7;>BNFH63;364DHLB8=>902NBBL279?58@LHF41437IGAA=;3:==CAGK75<07;EKME9?5611OECO392<;?AOII53?255KIOC?=08?3MCEM179>99GMKG;1>437IGAA=;;:==CAGK75408;EKME9?9?2NBBO2?>89GMKD;99:556JFNC>2448>3MCEN1??2?;8@LHE48:8245KIO@?552912NBBO2>04<:?AOIJ5;;:374DHLA8460601OECL311:==>BNFK6:<407;EKMF977601OECL3102==>BNFK6:=<06;EKMF976:730HD@M<030:<=CAGH7=<:19:FJJG:69<427IGAB=322;?89GMKD;982556JFNC>25<8?3MCEN1?>>89GMKD;9;:556JFNC>2648>3MCEN1?=2?;8@LHE4888245KIO@?572912NBBO2>24<:?AOIJ5;9:374DHLA8440601OECL313:==>BNFK6:>407;EKMF975601OECL3122==>BNFK6:?<06;EKMF974:730HD@M<010:<=CAGH7=>:19:FJJG:6;<427IGAB=302;?89GMKD;9:2556JFNC>27<8?3MCEN1?<>89GMKD;9=:556JFNC>2048>3MCEN1?;2?;8@LHE48>8245KIO@?512912NBBO2>44<:?AOIJ5;?:374DHLA8420601OECL315:==>BNFK6:8407;EKMF973601OECL3142==>BNFK6:9<06;EKMF972:730HD@M<070:<=CAGH7=8:19:FJJG:6=<427IGAB=362;?89GMKD;9<2556JFNC>21<8?3MCEN1?:>89GMKD;9?:556JFNC>2248>3MCEN1?92?;8@LHE48<8245KIO@?532912NBBO2>64<:?AOIJ5;=:374DHLA8400601OECL317:==>BNFK6::407;EKMF971601OECL3162==>BNFK6:;<06;EKMF970:730HD@M<050:<=CAGH7=::19:FJJG:6?<427IGAB=342;?89GMKD;9>2556JFNC>23<8?3MCEN1?8>89GMKD;91:556JFNC>2<48>3MCEN1?72?;8@LHE4828245KIO@?5=2912NBBO2>84<:?AOIJ5;3:374DHLA84>0601OECL319:==>BNFK6:4407;EKMF97?601OECL3182==>BNFK6:5<06;EKMF97>:730HD@M<0;0:<=CAGH7=4:19:FJJG:61<427IGAB=3:2;?89GMKD;902556JFNC>2=<8?3MCEN1?6>69GMKD;9730HD@M<323:<=CAGH7>=?19:FJJG:58;427IGAB=037;?;>89GMKD;:9?556JFNC>1438>3MCEN17?;8@LHE4;:3245KIO@?65?902NBBO2=0?;8@LHE4;;;245KIO@?647912NBBO2=13<:?AOIJ58:?374DHLA8773601OECL3207==>BNFK69=;06;EKMF946?730HD@M<33;:<=CAGH7><718:FJJG:59730HD@M<303:<=CAGH7>??19:FJJG:5:;427IGAB=017;?89GMKD;:;?556JFNC>1638>3MCEN1<=7?;8@LHE4;83245KIO@?67?902NBBO2=2?;8@LHE4;9;245KIO@?667912NBBO2=33<:?AOIJ588?374DHLA8753601OECL3227==>BNFK69?;06;EKMF944?730HD@M<31;:<=CAGH7>>718:FJJG:5;730HD@M<363:<=CAGH7>9?19:FJJG:5<;427IGAB=077;?89GMKD;:=?556JFNC>1038>3MCEN1<;7?;8@LHE4;>3245KIO@?61?902NBBO2=4?;8@LHE4;?;245KIO@?607912NBBO2=53<:?AOIJ58>?374DHLA8733601OECL3247==>BNFK699;06;EKMF942?730HD@M<37;:<=CAGH7>8718:FJJG:5=730HD@M<343:<=CAGH7>;?19:FJJG:5>;427IGAB=057;?89GMKD;:??556JFNC>1238>3MCEN1<97?;8@LHE4;<3245KIO@?63?902NBBO2=6?;8@LHE4;=;245KIO@?627912NBBO2=73<:?AOIJ58374DHLA8713601OECL3267==>BNFK69;;06;EKMF940?730HD@M<35;:<=CAGH7>:718:FJJG:5?730HD@M<3:3:<=CAGH7>5?19:FJJG:50;427IGAB=0;7;?89GMKD;:1?556JFNC>1<38>3MCEN1<77?;8@LHE4;23245KIO@?6=?902NBBO2=8?;8@LHE4;3;245KIO@?6<7912NBBO2=93<:?AOIJ582?374DHLA87?3601OECL3287==>BNFK695;06;EKMF94>?730HD@M<3;;:<=CAGH7>4718:FJJG:517=0HD@M<3<:?AOIJ59;<374DHLA8666601OECL3310==>BNFK68<>06;EKMF957<730HD@M<226:<=CAGH7?=819:FJJG:48>427IGAB=13<;?>6>99GMKD;;9427IGAB=124;??>>89GMKD;;88556JFNC>0568>3MCEN1=>4?;8@LHE4:;>245KIO@?740912NBBO2<16<:?AOIJ59:4374DHLA867>611OECL330<:?AOIJ599<374DHLA8646601OECL3330==>BNFK68>>06;EKMF955<730HD@M<206:<=CAGH7??819:FJJG:4:>427IGAB=11<;?<6>99GMKD;;;427IGAB=104;?=>>89GMKD;;:8556JFNC>0768>3MCEN1=<4?;8@LHE4:9>245KIO@?760912NBBO2<36<:?AOIJ5984374DHLA865>611OECL332<:?AOIJ59?<374DHLA8626601OECL3350==>BNFK688>06;EKMF953<730HD@M<266:<=CAGH7?9819:FJJG:4<>427IGAB=17<;?:6>99GMKD;;=427IGAB=164;?;>>89GMKD;;<8556JFNC>0168>3MCEN1=:4?;8@LHE4:?>245KIO@?700912NBBO2<56<:?AOIJ59>4374DHLA863>611OECL334<:?AOIJ59=<374DHLA8606601OECL3370==>BNFK68:>06;EKMF951<730HD@M<246:<=CAGH7?;819:FJJG:4>>427IGAB=15<;?86>99GMKD;;?427IGAB=144;?9>>89GMKD;;>8556JFNC>0368>3MCEN1=84?;8@LHE4:=>245KIO@?720912NBBO2<76<:?AOIJ59<4374DHLA861>611OECL336<:?AOIJ593<374DHLA86>6601OECL3390==>BNFK684>06;EKMF95?<730HD@M<2:6:<=CAGH7?5819:FJJG:40>427IGAB=1;<;?66>99GMKD;;1427IGAB=1:4;?7>>89GMKD;;08556JFNC>0=68>3MCEN1=64?;8@LHE4:3>245KIO@?7<0912NBBO2<96<:?AOIJ5924374DHLA86?>611OECL338<4?AOIJ59556JFNC>7458>3MCEN1:?1?;8@LHE4=:9245KIO@?055912NBBO2;05<:?AOIJ5>;9374DHLA8161601OECL3415==>BNFK6?<506;EKMF9271720HD@M<52==>BNFK6?==06;EKMF9269730HD@M<531:<=CAGH78<=19:FJJG:39=427IGAB=621;?89GMKD;<8=556JFNC>75=8>3MCEN1:>9?:8@LHE4=;556JFNC>7658>3MCEN1:=1?;8@LHE4=89245KIO@?075912NBBO2;25<:?AOIJ5>99374DHLA8141601OECL3435==>BNFK6?>506;EKMF9251720HD@M<50==>BNFK6??=06;EKMF9249730HD@M<511:<=CAGH78>=19:FJJG:3;=427IGAB=601;?89GMKD;<:=556JFNC>77=8>3MCEN1:<9?:8@LHE4=9556JFNC>7058>3MCEN1:;1?;8@LHE4=>9245KIO@?015912NBBO2;45<:?AOIJ5>?9374DHLA8121601OECL3455==>BNFK6?8506;EKMF9231720HD@M<56==>BNFK6?9=06;EKMF9229730HD@M<571:<=CAGH788=19:FJJG:3==427IGAB=661;?89GMKD;<<=556JFNC>71=8>3MCEN1::9?:8@LHE4=?556JFNC>7258>3MCEN1:91?;8@LHE4=<9245KIO@?035912NBBO2;65<:?AOIJ5>=9374DHLA8101601OECL3475==>BNFK6?:506;EKMF9211720HD@M<54==>BNFK6?;=06;EKMF9209730HD@M<551:<=CAGH78:=19:FJJG:3?=427IGAB=641;?89GMKD;<>=556JFNC>73=8>3MCEN1:89?:8@LHE4==556JFNC>7<58>3MCEN1:71?;8@LHE4=29245KIO@?0=5912NBBO2;85<:?AOIJ5>39374DHLA81>1601OECL3495==>BNFK6?4506;EKMF92?1720HD@M<5:==>BNFK6?5=06;EKMF92>9730HD@M<5;1:<=CAGH784=19:FJJG:31=427IGAB=6:1;?89GMKD;<0=556JFNC>7==8>3MCEN1:69?:8@LHE4=35;6JFNC>7:<=CAGH79=>19:FJJG:288427IGAB=736;?<>89GMKD;=9>556JFNC>6408>3MCEN1;?6?;8@LHE4<:<245KIO@?15>912NBBO2:08<;?AOIJ5?;245KIO@?1469j2NBBO2:1083:<=CAGH7918:FJJG:29720HD@M<40=<>BNFK6>?364DHLA802902NBBO2:5?:8@LHE4<<546JFNC>63;>99GMKD;>:437IGAB=47:==CAGH7:807;EKMF901611OECL366<;?AOIJ5<3255KIO@?2<803MCEN1818:FJJG:08720HD@M<63=<>BNFK6<>364DHLA825902NBBO284?:8@LHE4>?546JFNC>42;>BNFK6<255KIO@?<58?3MCEN16>>99GMKD;0;437IGAB=:0:==CAGH74907;EKMF9>2611OECL387<;?AOIJ52<255KIO@?<=8?3MCEN166>69GMKD;0720HD@M<82=<>BNFK62=364DHLA8<4902NBBO263?:8@LHE40>546JFNC>:1;>?720HD@M<8:=<>BNFK625394DHLA8<803MC[M1>17:FJTD:66>1OE]O32?;8@LVF4:0;2:5KIQC?7;189GMUD;;3:5;6JFPC>0:3=CGH6;2:5KO@>24;169GKD:6<7=0HBO314<4?AIF48<5;6J@A=34:2=CGH6:4394DNC?5<813MEJ0<08;EMB8769?2NDM1<>>69GKD:5:7=0HBO322<4?AIF4;>5;6J@A=06:2=CGH69:394DNC?62803MEJ0?617:FLE94>6?1OCL2=>69GKD:48730HBO33083:2=CGH68=384DNC?7;01OCO2>3?58@JD;9=4<7IAM<07=3>BHJ5;=2:5KOC>23;12NDN1?17:FLF9476>1OCO2=1?58@JD;:;4<7IAM<31=3>BHJ58?2:5KOC>11;1;08;EMA8719?2NDN1<7>69GKG:517<0HBL32?58@JD;;9427IAM<2394;117:FLTD:66>1OC]O32?;8@JVF4:0;2:5KOQC?7;189GKUD;;3:5;6J@PC>0:==CG\^J0=0n;EMVPD:6894j7IAZT@>2448f3ME^XL2>030n;EMVPD:68=4j7IAZT@>2408f3ME^XL2>0724<8>3ME^XL2>0?c8@JSSI5;:<3o4DNWWE97697k0HB[[A=326;g3?c8@JSSI5;:83o4DNWWE976=7k0HB[[A=322;g7?c8@JSSI5;:43o4DNWWE9761730HB[[A=32:d=CG\^J0<>`9GKPRF488:2l5KOTVB84456h1OCXZN<000:d=CG\^J0<<;>`9GKPRF488>2l5KOTVB84416h1OCXZN<004:d=CG\^J0<<7>`9GKPRF4882245KOTVB8449i2NDYYO3122=e>BH]]K7=>?1a:FLQQG;9:85m6J@UUC?5659i2NDYYO3126=e>BH]]K7=>;1a:FLQQG;9:<5m6J@UUC?5619i2NDYYO312:=e>BH]]K7=>719:FLQQG;9:4j7IAZT@>2058f3ME^XL2>402018f3ME^XL2>444j7IAZT@>20=8f3ME^XL2>48<:?AIR\H6:83o4DNWWE97287k0HB[[A=365;g?3o4DNWWE972<7k0HB[[A=361;g;3o4DNWWE97207k0HB[[A=36=;?`9GKPRF48<;2l5KOTVB84066h1OCXZN<041:d=CG\^J0<8<>`9GKPRF482l5KOTVB84026h1OCXZN<045:d=CG\^J0<88>`9GKPRF48<32l5KOTVB840>601OCXZN<04=e>BH]]K7=:>1a:FLQQG;9>;5m6J@UUC?5249i2NDYYO3161=e>BH]]K7=::1a:FLQQG;9>?5m6J@UUC?5209i2NDYYO3165=e>BH]]K7=:61a:FLQQG;9>3556J@UUC?528f3ME^XL2>812<68f3ME^XL2>852<28f3ME^XL2>893o4DNWWE97>;7k0HB[[A=3:0;g?7k0HB[[A=3:<;g1468f3ME^XL2=051428f3ME^XL2=091?c8@JSSI58:>3o4DNWWE946;7k0HB[[A=020;g5?c8@JSSI58::3o4DNWWE946?7k0HB[[A=02<;g9?;8@JSSI58:2l5KOTVB87476h1OCXZN<302:d=CG\^J0?<=>`9GKPRF4;882l5KOTVB87436h1OCXZN<306:d=CG\^J0?<9>`9GKPRF4;8<2l5KOTVB874?6h1OCXZN<30::<=CG\^J0?<1a:FLQQG;:::5m6J@UUC?6679i2NDYYO3220=e>BH]]K7>>=1a:FLQQG;::>5m6J@UUC?6639i2NDYYO3224=e>BH]]K7>>91a:FLQQG;::25m6J@UUC?66?912NDYYO3221078f3ME^XL2=421038f3ME^XL2=4610;g=3o4DNWWE942:7k0HB[[A=067;g93o4DNWWE942>7k0HB[[A=063;g5374DNWWE9426h1OCXZN<343:d=CG\^J0?8>>`9GKPRF4;<92l5KOTVB87046h1OCXZN<347:d=CG\^J0?8:>`9GKPRF4;<=2l5KOTVB87006h1OCXZN<34;:d=CG\^J0?86>89GKPRF4;<5m6J@UUC?6269i2NDYYO3263=e>BH]]K7>:<1a:FLQQG;:>95m6J@UUC?6229i2NDYYO3267=e>BH]]K7>:81a:FLQQG;:>=5m6J@UUC?62>9i2NDYYO326;==>BH]]K7>:0n;EMVPD:5094j7IAZT@>1<48f3ME^XL2=830n;EMVPD:50=4j7IAZT@>1<08f3ME^XL2=871<<8>3ME^XL2=8?c8@JSSI582<3o4DNWWE94>97k0HB[[A=0:6;g=7k0HB[[A=0:2;g1730HB[[A=0::==CG\^J0?0n;EMVPD:4894j7IAZT@>0448f3ME^XL2<030n;EMVPD:48=4j7IAZT@>0408f3ME^XL2<0704<8>3ME^XL2<0?c8@JSSI59:<3o4DNWWE95697k0HB[[A=126;g3?c8@JSSI59:83o4DNWWE956=7k0HB[[A=122;g7?c8@JSSI59:43o4DNWWE9561730HB[[A=12:d=CG\^J0>>`9GKPRF4:8:2l5KOTVB86456h1OCXZN<200:d=CG\^J0><;>`9GKPRF4:8>2l5KOTVB86416h1OCXZN<204:d=CG\^J0><7>`9GKPRF4:82245KOTVB8649i2NDYYO3322=e>BH]]K7?>?1a:FLQQG;;:85m6J@UUC?7659i2NDYYO3326=e>BH]]K7?>;1a:FLQQG;;:<5m6J@UUC?7619i2NDYYO332:=e>BH]]K7?>719:FLQQG;;:4j7IAZT@>0058f3ME^XL2<400018f3ME^XL2<444j7IAZT@>00=8f3ME^XL2<48<:?AIR\H6883o4DNWWE95287k0HB[[A=165;g?3o4DNWWE952<7k0HB[[A=161;g;3o4DNWWE95207k0HB[[A=16=;?`9GKPRF4:<;2l5KOTVB86066h1OCXZN<241:d=CG\^J0>8<>`9GKPRF4:2l5KOTVB86026h1OCXZN<245:d=CG\^J0>88>`9GKPRF4:<32l5KOTVB860>601OCXZN<24=e>BH]]K7?:>1a:FLQQG;;>;5m6J@UUC?7249i2NDYYO3361=e>BH]]K7?::1a:FLQQG;;>?5m6J@UUC?7209i2NDYYO3365=e>BH]]K7?:61a:FLQQG;;>3556J@UUC?728f3ME^XL2<810<68f3ME^XL2<850<28f3ME^XL2<893o4DNWWE95>;7k0HB[[A=1:0;g?7k0HB[[A=1:<;g7468f3ME^XL2;057428f3ME^XL2;091?c8@JSSI5>:>3o4DNWWE926;7k0HB[[A=620;g5?c8@JSSI5>::3o4DNWWE926?7k0HB[[A=62<;g9?;8@JSSI5>:2l5KOTVB81476h1OCXZN<502:d=CG\^J09<=>`9GKPRF4=882l5KOTVB81436h1OCXZN<506:d=CG\^J09<9>`9GKPRF4=8<2l5KOTVB814?6h1OCXZN<50::<=CG\^J09<1a:FLQQG;<::5m6J@UUC?0679i2NDYYO3420=e>BH]]K78>=1a:FLQQG;<:>5m6J@UUC?0639i2NDYYO3424=e>BH]]K78>91a:FLQQG;<:25m6J@UUC?06?912NDYYO3427078f3ME^XL2;427038f3ME^XL2;4670;g>=3o4DNWWE922:7k0HB[[A=667;g>93o4DNWWE922>7k0HB[[A=663;g>5374DNWWE9226h1OCXZN<543:d=CG\^J098>>`9GKPRF4=<92l5KOTVB81046h1OCXZN<547:d=CG\^J098:>`9GKPRF4=<=2l5KOTVB81006h1OCXZN<54;:d=CG\^J0986>89GKPRF4=<5m6J@UUC?0269i2NDYYO3463=e>BH]]K78:<1a:FLQQG;<>95m6J@UUC?0229i2NDYYO3467=e>BH]]K78:81a:FLQQG;<>=5m6J@UUC?02>9i2NDYYO346;==>BH]]K78:0n;EMVPD:3094j7IAZT@>7<48f3ME^XL2;830n;EMVPD:30=4j7IAZT@>7<08f3ME^XL2;877<<8>3ME^XL2;8?c8@JSSI5>2<3o4DNWWE92>97k0HB[[A=6:6;g283o4DNWWE92>=7k0HB[[A=6:2;g243o4DNWWE92>1730HB[[A=6::==CG\^J090n;EMVPD:2894j7IAZT@>6448f3ME^XL2:03<>0n;EMVPD:28=4j7IAZT@>6408f3ME^XL2:07<:0n;EMVPD:2814j7IAZT@>64<8>3ME^XL2:0?c8@JSSI5?:<3m4DNWWE93693:5m6J@UUC?147912NDYYO350<:?AIR\H6>>374DNWWE934601OCXZN<46==>BH]]K79806;EMVPD:2>730HB[[A=74:<=CG\^J08619:FLQQG;=0437IAZT@>6:<=CG\^J0;>19:FLQQG;>8427IAZT@>56;?89GKPRF4?>556J@UUC?208>3ME^XL296?;8@JSSI5<<245KOTVB83>912NDYYO368<;?AIR\H6=245KOTVB826912NDYYO370<:?AIR\H6<>374DNWWE914601OCXZN<66==>BH]]K7;806;EMVPD:0>730HB[[A=54:<=CG\^J0:619:FLQQG;?0437IAZT@>4:<=CG\^J05>19:FLQQG;08427IAZT@>;6;?89GKPRF41>556J@UUC?<08>3ME^XL276?;8@JSSI52<245KOTVB8=>912NDYYO388<;?AIR\H63245KOTVB8<6912NDYYO390<:?AIR\H62>374DNWWE9?4601OCXZN<86==>BH]]K75806;EMVPD:>>730HB[[A=;4:<=CG\^J04619:FLQQG;10437IAZT@>::==CG\^I0=0n;EMVPG:6894j7IAZTC>2448f3ME^XO2>030n;EMVPG:68=4j7IAZTC>2408f3ME^XO2>0724<8>3ME^XO2>0?c8@JSSJ5;:<3o4DNWWF97697k0HB[[B=326;g3?c8@JSSJ5;:83o4DNWWF976=7k0HB[[B=322;g7?c8@JSSJ5;:43o4DNWWF9761730HB[[B=32:d=CG\^I0<>`9GKPRE488:2l5KOTVA84456h1OCXZM<000:d=CG\^I0<<;>`9GKPRE488>2l5KOTVA84416h1OCXZM<004:d=CG\^I0<<7>`9GKPRE4882245KOTVA8449i2NDYYL3122=e>BH]]H7=>?1a:FLQQD;9:85m6J@UU@?5659i2NDYYL3126=e>BH]]H7=>;1a:FLQQD;9:<5m6J@UU@?5619i2NDYYL312:=e>BH]]H7=>719:FLQQD;9:4j7IAZTC>2058f3ME^XO2>402018f3ME^XO2>444j7IAZTC>20=8f3ME^XO2>48<:?AIR\K6:83o4DNWWF97287k0HB[[B=365;g?3o4DNWWF972<7k0HB[[B=361;g;3o4DNWWF97207k0HB[[B=36=;?`9GKPRE48<;2l5KOTVA84066h1OCXZM<041:d=CG\^I0<8<>`9GKPRE482l5KOTVA84026h1OCXZM<045:d=CG\^I0<88>`9GKPRE48<32l5KOTVA840>601OCXZM<04=e>BH]]H7=:>1a:FLQQD;9>;5m6J@UU@?5249i2NDYYL3161=e>BH]]H7=::1a:FLQQD;9>?5m6J@UU@?5209i2NDYYL3165=e>BH]]H7=:61a:FLQQD;9>3556J@UU@?528f3ME^XO2>812<68f3ME^XO2>852<28f3ME^XO2>893o4DNWWF97>;7k0HB[[B=3:0;g?7k0HB[[B=3:<;g1468f3ME^XO2=051428f3ME^XO2=091?c8@JSSJ58:>3o4DNWWF946;7k0HB[[B=020;g5?c8@JSSJ58::3o4DNWWF946?7k0HB[[B=02<;g9?;8@JSSJ58:2l5KOTVA87476h1OCXZM<302:d=CG\^I0?<=>`9GKPRE4;882l5KOTVA87436h1OCXZM<306:d=CG\^I0?<9>`9GKPRE4;8<2l5KOTVA874?6h1OCXZM<30::<=CG\^I0?<1a:FLQQD;:::5m6J@UU@?6679i2NDYYL3220=e>BH]]H7>>=1a:FLQQD;::>5m6J@UU@?6639i2NDYYL3224=e>BH]]H7>>91a:FLQQD;::25m6J@UU@?66?912NDYYL3221078f3ME^XO2=421038f3ME^XO2=4610;g=3o4DNWWF942:7k0HB[[B=067;g93o4DNWWF942>7k0HB[[B=063;g5374DNWWF9426h1OCXZM<343:d=CG\^I0?8>>`9GKPRE4;<92l5KOTVA87046h1OCXZM<347:d=CG\^I0?8:>`9GKPRE4;<=2l5KOTVA87006h1OCXZM<34;:d=CG\^I0?86>89GKPRE4;<5m6J@UU@?6269i2NDYYL3263=e>BH]]H7>:<1a:FLQQD;:>95m6J@UU@?6229i2NDYYL3267=e>BH]]H7>:81a:FLQQD;:>=5m6J@UU@?62>9i2NDYYL326;==>BH]]H7>:0n;EMVPG:5094j7IAZTC>1<48f3ME^XO2=830n;EMVPG:50=4j7IAZTC>1<08f3ME^XO2=871<<8>3ME^XO2=8?c8@JSSJ582<3o4DNWWF94>97k0HB[[B=0:6;g=7k0HB[[B=0:2;g1730HB[[B=0::==CG\^I0?0n;EMVPG:4894j7IAZTC>0448f3ME^XO2<030n;EMVPG:48=4j7IAZTC>0408f3ME^XO2<0704<8>3ME^XO2<0?c8@JSSJ59:<3o4DNWWF95697k0HB[[B=126;g3?c8@JSSJ59:83o4DNWWF956=7k0HB[[B=122;g7?c8@JSSJ59:43o4DNWWF9561730HB[[B=12:d=CG\^I0>>`9GKPRE4:8:2l5KOTVA86456h1OCXZM<200:d=CG\^I0><;>`9GKPRE4:8>2l5KOTVA86416h1OCXZM<204:d=CG\^I0><7>`9GKPRE4:82245KOTVA8649i2NDYYL3322=e>BH]]H7?>?1a:FLQQD;;:85m6J@UU@?7659i2NDYYL3326=e>BH]]H7?>;1a:FLQQD;;:<5m6J@UU@?7619i2NDYYL332:=e>BH]]H7?>719:FLQQD;;:4j7IAZTC>0058f3ME^XO2<400018f3ME^XO2<444j7IAZTC>00=8f3ME^XO2<48<:?AIR\K6883o4DNWWF95287k0HB[[B=165;g?3o4DNWWF952<7k0HB[[B=161;g;3o4DNWWF95207k0HB[[B=16=;?`9GKPRE4:<;2l5KOTVA86066h1OCXZM<241:d=CG\^I0>8<>`9GKPRE4:2l5KOTVA86026h1OCXZM<245:d=CG\^I0>88>`9GKPRE4:<32l5KOTVA860>601OCXZM<24=e>BH]]H7?:>1a:FLQQD;;>;5m6J@UU@?7249i2NDYYL3361=e>BH]]H7?::1a:FLQQD;;>?5m6J@UU@?7209i2NDYYL3365=e>BH]]H7?:61a:FLQQD;;>3556J@UU@?728f3ME^XO2<810<68f3ME^XO2<850<28f3ME^XO2<893o4DNWWF95>;7k0HB[[B=1:0;g?7k0HB[[B=1:<;g7468f3ME^XO2;057428f3ME^XO2;091?c8@JSSJ5>:>3o4DNWWF926;7k0HB[[B=620;g5?c8@JSSJ5>::3o4DNWWF926?7k0HB[[B=62<;g9?;8@JSSJ5>:2l5KOTVA81476h1OCXZM<502:d=CG\^I09<=>`9GKPRE4=882l5KOTVA81436h1OCXZM<506:d=CG\^I09<9>`9GKPRE4=8<2l5KOTVA814?6h1OCXZM<50::<=CG\^I09<1a:FLQQD;<::5m6J@UU@?0679i2NDYYL3420=e>BH]]H78>=1a:FLQQD;<:>5m6J@UU@?0639i2NDYYL3424=e>BH]]H78>91a:FLQQD;<:25m6J@UU@?06?912NDYYL3427078f3ME^XO2;427038f3ME^XO2;4670;g>=3o4DNWWF922:7k0HB[[B=667;g>93o4DNWWF922>7k0HB[[B=663;g>5374DNWWF9226h1OCXZM<543:d=CG\^I098>>`9GKPRE4=<92l5KOTVA81046h1OCXZM<547:d=CG\^I098:>`9GKPRE4=<=2l5KOTVA81006h1OCXZM<54;:d=CG\^I0986>89GKPRE4=<5m6J@UU@?0269i2NDYYL3463=e>BH]]H78:<1a:FLQQD;<>95m6J@UU@?0229i2NDYYL3467=e>BH]]H78:81a:FLQQD;<>=5m6J@UU@?02>9i2NDYYL346;==>BH]]H78:0n;EMVPG:3094j7IAZTC>7<48f3ME^XO2;830n;EMVPG:30=4j7IAZTC>7<08f3ME^XO2;877<<8>3ME^XO2;8?c8@JSSJ5>2<3o4DNWWF92>97k0HB[[B=6:6;g283o4DNWWF92>=7k0HB[[B=6:2;g243o4DNWWF92>1730HB[[B=6::==CG\^I090n;EMVPG:2894j7IAZTC>6448f3ME^XO2:03<>0n;EMVPG:28=4j7IAZTC>6408f3ME^XO2:07<:0n;EMVPG:2814j7IAZTC>64<8>3ME^XO2:0?c8@JSSJ5?:<3m4DNWWF93693:5m6J@UU@?147912NDYYL350<:?AIR\K6>>374DNWWF934601OCXZM<46==>BH]]H79806;EMVPG:2>730HB[[B=74:<=CG\^I08619:FLQQD;=0437IAZTC>6:<=CG\^I0;>19:FLQQD;>8427IAZTC>56;?89GKPRE4?>556J@UU@?208>3ME^XO296?;8@JSSJ5<<245KOTVA83>912NDYYL368<;?AIR\K6=245KOTVA826912NDYYL370<:?AIR\K6<>374DNWWF914601OCXZM<66==>BH]]H7;806;EMVPG:0>730HB[[B=54:<=CG\^I0:619:FLQQD;?0437IAZTC>4:<=CG\^I05>19:FLQQD;08427IAZTC>;6;?89GKPRE41>556J@UU@?<08>3ME^XO276?;8@JSSJ52<245KOTVA8=>912NDYYL388<;?AIR\K63245KOTVA8<6912NDYYL390<:?AIR\K62>374DNWWF9?4601OCXZM<86==>BH]]H75806;EMVPG:>>730HB[[B=;4:<=CG\^I04619:FLQQD;10437IAZTC>::6=BFH90ICL>;F18CKB?3@DBX]Q?099JJLRWW9;37D@FTQ]36==NF@^[S==7;HLJPUY7<11BBDZ__17;?LHN\YU;:55FNHVS[5103@DBXR>?7:KMMQY79>1BBDZP0358MKOSW99<7D@FT^273>OIA]U;9:5FNHV\4311BBDZP1358MKOSW89<7D@FT^373>OIA]U:9:5FNHV\531969JJLRX9H=0ECG[_0@4?LHN\V;H;6GAIU]2@2=NF@^T=H94IOKW[4@03@DBXR7:KMMQY59>1BBDZP2358MKOSW;9<7D@FT^073>OIA]U99:5FNHV\631H94IOKW[7@03@DBXR=?7:KMMQY49>1BBDZP3358MKOSW:9<7D@FT^173>OIA]U89:5FNHV\73198;HLJPZ5??2CEEYQ<969JJLRX;H=0ECG[_2@4?LHN\V9H;6GAIU]0@2=NF@^T?H94IOKW[6@13@DBXRO9;HLJPZDc3@DAINZKBHVFVWbV):1roSA:4P@PWe>VNFVH^_DJWb:RJJZDR[GKFI;5_SEMMA`=UIDH::R]<6^Q02f=ULHNO^HML<1<`?WBFLMXNON2>>b9Q@DBCZLIH0?0j;SFB@ATBKJ686=0l;SFB@ATBKJ682l5]E@F\BLTT\k1YIJMJA=294;?c9QABEBJ5:1<374RDE@AG:7601Y_YO30;2=3>TT\H6;245]SU@?4?69?2XXXO2?>69PFLRBZ[;:7^F]EF]F\QTFK]UEKNk4SIPFCZKNFVYBVH?<;RKN[FIKD@YBCCQLHDAH2>UH][IN;6]]V@N\E2=TZ_KGSO:4SRPB0>UTZK<0_YO[UR68P\VB<81^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~yo6[\ES]UMVOEDL90ZNM6;WKFSZR^XL90[HO9;VGB85803^OJ0<>17:UFE9766>1\IL2>2?58S@G;9:4<7ZKN<06=3>QBI5;>2:5XE@>22;1<_LK7=:08;VGB84>9?2]NM1?6>79TAD:66>1\IL2=0?58S@G;:84<7ZKN<30=3>QBI5882:5XE@>10;1<_LK7>808;VGB8709?2]NM1<8>69TAD:507=0[HO328<5?RCF4;4<7ZKN<22=3>QBI59:2:5XE@>06;1<_LK7?>08;VGB8629?2]NM1=:>69TAD:4>7=0[HO336<4?RCF4:25;6YJA=1::3=PMH682:5XE@>74;1<_LK78<08;VGB8149?2]NM1:<>69TAD:3<7=0[HO344<4?RCF4=<5;6YJA=64:2=PMH6?4394WDC?0<813^OJ0908;VGB8069?2]NM1;>>69TAD:2:7=0[HO352<4?RCF4<>5;6YJA=76:<=PMH6>:7>17:UFE9316?1\IL2:>79TAD:16?1\IL28>79TAD:?6?1\IL26>29TAG0<_LH7<394WD@?55803^OI017:UFF9756>1\IO2>3?58S@D;9=4<7ZKM<07=3>QBJ5;=2:5XEC>23;1<_LH7=508;VGA84?9>2]NN1?17:UFF9476>1\IO2=1?58S@D;:;4<7ZKM<31=3>QBJ58?2:5XEC>11;1<_LH7>;08;VGA8719?2]NN1<7>69TAG:517<0[HL32?58S@D;;94<7ZKM<23=3>QBJ5992:5XEC>07;1<_LH7?908;VGA8639?2]NN1=9>69TAG:4?7=0[HL339<4?RCE4:35:6YJB=1=3>QBJ5>;2:5XEC>75;1<_LH78?08;VGA8159?2]NN1:;>69TAG:3=7=0[HL347<4?RCE4==5;6YJB=6;:2=PMK6?5384WD@?0;1<_LH79=08;VGA8079?2]NN1;=>69TAG:2;7=0[HL355<4?RCE4556YJB=75>5803^OI08816:UFF939>2]NN1816:UFF919>2]NN1616:UFF9?9k2]YEYKPMNFF[De<_[C_IRC@DD]A5a=_AECET VKB!2-5%US]K*;"<.NSBKJ2>^T\ECI;6V\T^EM@2=_[]U]ONl4X^ALV@YNFOE=7Ujm_Hfe?]boWYxba[k}shmm55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;Xgp<>gcl{k7<364aefqe97902koho32?c8eabui591<364aefqe959911i`fQbel]dakY`mgoyenQlsup2<>dkcVgnaRijn^rqmhYpam~cS7;cnh[hcjWnoeS}|fm^uj`qnX:820naePmdo\c`hXx{cfSzgkti]05==edbUfi`Qheo]svlkX`ndR:>8:`ooZkbeVmnbR~}il]tmaroW<;37obd_lgn[bciWyxbaRyfduj\24>:h6lck^ofiZabfVzye`Qxr`rsawYt;V?:h6lck^ofiZabfVzye`Qxr`rsawYt;V<:h6lck^ofiZabfVzye`Qxr`rsawYt;V=:h6lck^ofiZabfVzye`Qxr`rsawYt;V2m7obd_lgn[bciW}e{==5mlj]nahY`mgU};R?=c:`ooZkbeVmnbRx8_0.#\ljnfq*HC_K/Gdlfvdrhz);?"??;;cnh[hcjWnoeS{9P1^zpp452-a\v`gcW~coxeQm=431(fYu{}U{~da}iu{\e8EB$jUyyQrhmqmqXj4IN nQ}su]w}uc:[PDH nQ}supbiZg:8%iT~~z}al]a95*dWzcfSnaclhqjkkYd`li`1LBC,b]vw`Yeq}oT{ho20-a\qvcXjp~nSzkm=1.`[pubWmommxb{_ecwe86+kVxiRklc<2/gZstmVydjyklc<2/gZqbiV}bhyf21-a\s`dX`nd0?#c^uqmqcXllzdRo217.`[rtn|lUoi}zg_c?22)eX{ciRc`dd]b9WCFLVLB^^Z#c^uqmqcXefnnSo3XRHVF[COU[]&hSz|ftd]tmaroWh7>=?"l_vpjp`Ypam~cSo3:13.`[}bb~`injlcflx?ptdtsig9nqU: vs;;bnhe2=cagk7<374dhlb8467601oeco3113==>bnfh6:06;ekme977;730hd`n<027:<=cagk7==;19:fjjd:68?427igaa=333;?7>89gmkg;993546jfn`>24;?89gmkg;98;556jfn`>2578>3mcem1?>3?;8`lhf48;?245kioc?543912nbbl2>17<:?aoii5;:;374dhlb847?601oeco310;=<>bnfh6:=374dhlb8447601oeco3133==>bnfh6:>?06;ekme975;730hd`n<007:<=cagk7=?;19:fjjd:6:?427igaa=313;?89gmkg;9;3546jfn`>26;?89gmkg;9:;556jfn`>2778>3mcem1?<3?;8`lhf489?245kioc?563912nbbl2>37<:?aoii5;8;374dhlb845?601oeco312;=<>bnfh6:?374dhlb8427601oeco3153==>bnfh6:8?06;ekme973;730hd`n<067:<=cagk7=9;19:fjjd:6427igaa=373;?89gmkg;9=3546jfn`>20;?89gmkg;9<;556jfn`>2178>3mcem1?:3?;8`lhf48??245kioc?503912nbbl2>57<:?aoii5;>;374dhlb843?601oeco314;=<>bnfh6:9374dhlb8407601oeco3173==>bnfh6::?06;ekme971;730hd`n<047:<=cagk7=;;19:fjjd:6>?427igaa=353;?89gmkg;9?3546jfn`>22;?89gmkg;9>;556jfn`>2378>3mcem1?83?;8`lhf48=?245kioc?523912nbbl2>77<:?aoii5;<;374dhlb841?601oeco316;=<>bnfh6:;374dhlb84>7601oeco3193==>bnfh6:4?06;ekme97?;730hd`n<0:7:<=cagk7=5;19:fjjd:60?427igaa=3;3;?89gmkg;913546jfn`>2<;?89gmkg;90;556jfn`>2=78>3mcem1?63?;8`lhf483?245kioc?5<3912nbbl2>97<:?aoii5;2;374dhlb84??601oeco318;=<>bnfh6:5394dhlb848>3mcem10?;8`lhf4;::245kioc?654912nbbl2=02<:?aoii58;8374dhlb8762601oeco3214==>bnfh69<:06;ekme9470730hd`n<32::==cagk7>=06;ekme9468730hd`n<332:<=cagk7><<19:fjjd:59:427igaa=020;?89gmkg;:8<556jfn`>1528>3mcem1<>8?;8`lhf4;;2255kioc?648>3mcem1<=0?;8`lhf4;8:245kioc?674912nbbl2=22<:?aoii5898374dhlb8742601oeco3234==>bnfh69>:06;ekme9450730hd`n<30::==cagk7>?06;ekme9448730hd`n<312:<=cagk7>><19:fjjd:5;:427igaa=000;?89gmkg;::<556jfn`>1728>3mcem1<<8?;8`lhf4;92255kioc?668>3mcem1<;0?;8`lhf4;>:245kioc?614912nbbl2=42<:?aoii58?8374dhlb8722601oeco3254==>bnfh698:06;ekme9430730hd`n<36::==cagk7>906;ekme9428730hd`n<372:<=cagk7>8<19:fjjd:5=:427igaa=060;?89gmkg;:<<556jfn`>1128>3mcem1<:8?;8`lhf4;?2255kioc?608>3mcem1<90?;8`lhf4;<:245kioc?634912nbbl2=62<:?aoii58=8374dhlb8702601oeco3274==>bnfh69::06;ekme9410730hd`n<34::==cagk7>;06;ekme9408730hd`n<352:<=cagk7>:<19:fjjd:5?:427igaa=040;?89gmkg;:><556jfn`>1328>3mcem1<88?;8`lhf4;=2255kioc?628>3mcem1<70?;8`lhf4;2:245kioc?6=4912nbbl2=82<:?aoii5838374dhlb87>2601oeco3294==>bnfh694:06;ekme94?0730hd`n<3:::==cagk7>506;ekme94>8730hd`n<3;2:<=cagk7>4<19:fjjd:51:427igaa=0:0;?89gmkg;:0<556jfn`>1=28>3mcem1<68?;8`lhf4;32255kioc?6<803mcem1<19:fjjd:489427igaa=135;?>=>89gmkg;;99556jfn`>0418>3mcem1=?5?;8`lhf4::=245kioc?751912nbbl2<09<:?aoii59;5364dhlb866912nbbl2<11<:?aoii59:=374dhlb8675601oeco3301==>bnfh68=906;ekme956=730hd`n<235:<=cagk7?<919:fjjd:491427igaa=12=;>?19:fjjd:4:9427igaa=115;?<=>89gmkg;;;9556jfn`>0618>3mcem1==5?;8`lhf4:8=245kioc?771912nbbl2<29<:?aoii5995364dhlb864912nbbl2<31<:?aoii598=374dhlb8655601oeco3321==>bnfh68?906;ekme954=730hd`n<215:<=cagk7?>919:fjjd:4;1427igaa=10=;>=19:fjjd:4<9427igaa=175;?:=>89gmkg;;=9556jfn`>0018>3mcem1=;5?;8`lhf4:>=245kioc?711912nbbl2<49<:?aoii59?5364dhlb862912nbbl2<51<:?aoii59>=374dhlb8635601oeco3341==>bnfh689906;ekme952=730hd`n<275:<=cagk7?8919:fjjd:4=1427igaa=16=;>;19:fjjd:4>9427igaa=155;?8=>89gmkg;;?9556jfn`>0218>3mcem1=95?;8`lhf4:<=245kioc?731912nbbl2<69<:?aoii59=5364dhlb860912nbbl2<71<:?aoii59<=374dhlb8615601oeco3361==>bnfh68;906;ekme950=730hd`n<255:<=cagk7?:919:fjjd:4?1427igaa=14=;>919:fjjd:409427igaa=1;5;?6=>89gmkg;;19556jfn`>0<18>3mcem1=75?;8`lhf4:2=245kioc?7=1912nbbl2<89<:?aoii5935364dhlb86>912nbbl2<91<:?aoii592=374dhlb86?5601oeco3381==>bnfh685906;ekme95>=730hd`n<2;5:<=cagk7?4919:fjjd:411427igaa=1:=;>717:fjjd:4601oeco3412==>bnfh6?<<06;ekme927:730hd`n<520:<=cagk78=:19:fjjd:38<427igaa=632;?8>89gmkg;<92556jfn`>74<8?3mcem1:?>89gmkg;<8:556jfn`>7548>3mcem1:>2?;8`lhf4=;8245kioc?042912nbbl2;14<:?aoii5>::374dhlb8170601oeco340:==>bnfh6?=407;ekme926601oeco3432==>bnfh6?><06;ekme925:730hd`n<500:<=cagk78?:19:fjjd:3:<427igaa=612;?89gmkg;<;2556jfn`>76<8?3mcem1:=>89gmkg;<::556jfn`>7748>3mcem1:<2?;8`lhf4=98245kioc?062912nbbl2;34<:?aoii5>8:374dhlb8150601oeco342:==>bnfh6??407;ekme924601oeco3452==>bnfh6?8<06;ekme923:730hd`n<560:<=cagk789:19:fjjd:3<<427igaa=672;?89gmkg;<=2556jfn`>70<8?3mcem1:;>89gmkg;<<:556jfn`>7148>3mcem1::2?;8`lhf4=?8245kioc?002912nbbl2;54<:?aoii5>>:374dhlb8130601oeco344:==>bnfh6?9407;ekme922601oeco3472==>bnfh6?:<06;ekme921:730hd`n<540:<=cagk78;:19:fjjd:3><427igaa=652;?89gmkg;2556jfn`>72<8?3mcem1:9>89gmkg;<>:556jfn`>7348>3mcem1:82?;8`lhf4==8245kioc?022912nbbl2;74<:?aoii5><:374dhlb8110601oeco346:==>bnfh6?;407;ekme920601oeco3492==>bnfh6?4<06;ekme92?:730hd`n<5:0:<=cagk785:19:fjjd:30<427igaa=6;2;?89gmkg;<12556jfn`>7<<8?3mcem1:7>89gmkg;<0:556jfn`>7=48>3mcem1:62?;8`lhf4=38245kioc?0<2912nbbl2;94<:?aoii5>2:374dhlb81?0601oeco348:==>bnfh6?5407;ekme92>6>1oeco34?;8`lhf4<:;245kioc?157912nbbl2:03<:?aoii5?;?374dhlb8063601oeco3517==>bnfh6><;06;ekme937?730hd`n<42;:<=cagk79=718:fjjd:28730hd`n<433:g=cagk7950?;8`lhf4<;:255kioc?148?3mcem1;=>99gmkg;=:437igaa=77:==cagk79807;ekme931611oeco356<;?aoii5?3255kioc?1<803mcem1;18:fjjd:18720hd`n<73=<>bnfh6=>364dhlb835902nbbl294?:8`lhf4??546jfn`>52;>bnfh6=255kioc?358?3mcem19>>99gmkg;?;437igaa=50:==cagk7;907;ekme912611oeco377<;?aoii5=<255kioc?3=8?3mcem196>69gmkg;?720hd`n<92=<>bnfh63=364dhlb8=4902nbbl273?:8`lhf41>546jfn`>;1;>bnfh635394dhlb8=8?3mcem17?>99gmkg;18437igaa=;1:==cagk75>07;ekme9?3611oeco394<;?aoii53=255kioc?=28?3mcem177>99gmkg;104<7igaa=;=<>bh}}k7<3o4dnwwe97787k0hb{{a=335;g`9gkprf48;;2l5kotvb84766h1ocxzn<031:d=cg|~j0<>`9gkprf48;?2l5kotvb84726h1ocxzn<035:d=cg|~j08>`9gkprf48;32l5kotvb847>601ocxzn<03=e>bh}}k7=?>1a:flqqg;9;;5m6j`uuc?5749i2ndyyo3131=e>bh}}k7=?:1a:flqqg;9;?5m6j`uuc?5709i2ndyyo3135=e>bh}}k7=?61a:flqqg;9;3556j`uuc?578f3me~xl2>312768f3me~xl2>352728f3me~xl2>393o4dnwwe973;7k0hb{{a=370;g`9gkprf48?82l5kotvb84336h1ocxzn<076:d=cg|~j0<;9>`9gkprf48?<2l5kotvb843?6h1ocxzn<07::<=cg|~j0<;1a:flqqg;9?:5m6j`uuc?5379i2ndyyo3170=e>bh}}k7=;=1a:flqqg;9?>5m6j`uuc?5339i2ndyyo3174=e>bh}}k7=;91a:flqqg;9?25m6j`uuc?53?912ndyyo3172378f3me~xl2>722338f3me~xl2>7623;g7k0hb{{a=3;3;g>`9gkprf48392l5kotvb84?46h1ocxzn<0;7:d=cg|~j0<7:>`9gkprf483=2l5kotvb84?06h1ocxzn<0;;:d=cg|~j0<76>89gkprf483546j`uuc?5;g7k0hb{{a=033;g>`9gkprf4;;92l5kotvb87746h1ocxzn<337:d=cg|~j0??:>`9gkprf4;;=2l5kotvb87706h1ocxzn<33;:d=cg|~j0??6>89gkprf4;;5m6j`uuc?6769i2ndyyo3233=e>bh}}k7>?<1a:flqqg;:;95m6j`uuc?6729i2ndyyo3237=e>bh}}k7>?81a:flqqg;:;=5m6j`uuc?67>9i2ndyyo323;==>bh}}k7>?0n;emvpd:5;94j7iazt`>1748f3me~xl2=330n;emvpd:5;=4j7iazt`>1708f3me~xl2=37