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https://opencores.org/ocsvn/natalius_8bit_risc/natalius_8bit_risc/trunk
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/natalius_8bit_risc/trunk/processor_core/regfile.v
0,0 → 1,46
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:13:24 05/02/2012 |
// Design Name: |
// Module Name: regfile |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module regfile( |
input [7:0] datain, |
input clk, we, |
input [2:0] wa, |
input [2:0] raa, |
input [2:0] rab, |
output [7:0] porta, |
output [7:0] portb |
); |
|
|
reg [7:0] mem [7:0]; |
|
always@(posedge clk) |
begin |
mem[0]<=0; |
if(we) |
mem[wa]<=datain; |
end |
|
assign porta=mem[raa]; |
assign portb=mem[rab]; |
|
|
endmodule |
|
/natalius_8bit_risc/trunk/processor_core/natalius_processor.v
0,0 → 1,56
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Universidad Pontificia Bolivariana |
// Engineer: Fabio Andres Guzman Figueroa |
// |
// Create Date: 20:52:12 05/14/2012 |
// Design Name: |
// Module Name: natalius_processor |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module natalius_processor( |
input clk, |
input rst, |
output [7:0] port_addr, |
output read_e, |
output write_e, |
input [7:0] data_in, |
output [7:0] data_out |
); |
|
wire z,c; |
wire insel; |
wire we; |
wire [2:0] raa; |
wire [2:0] rab; |
wire [2:0] wa; |
wire [2:0] opalu; |
wire [2:0] sh; |
wire selpc; |
wire ldpc; |
wire ldflag; |
wire [10:0] ninst_addr; |
wire selk; |
wire [7:0] KTE; |
wire [10:0] stack_addr; |
wire wr_en, rd_en; |
wire [7:0] imm; |
wire selimm; |
wire [15:0] instruction; |
wire [10:0] inst_addr; |
|
control_unit control_unit_i(clk,rst,instruction,z,c,port_addr,write_e,read_e,insel,we,raa,rab,wa,opalu,sh,selpc,ldpc,ldflag,ninst_addr,selk,KTE,stack_addr,wr_en,rd_en,imm,selimm); |
data_path data_path_i(clk,rst,data_in,insel,we,raa,rab,wa,opalu,sh,selpc,selk,ldpc,ldflag,wr_en,rd_en,ninst_addr,KTE,imm,selimm, data_out,inst_addr,stack_addr,z,c); |
instruction_memory inst_mem(clk,inst_addr,instruction); |
|
endmodule |
/natalius_8bit_risc/trunk/processor_core/control_unit.v
0,0 → 1,459
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Universidad Pontificia Bolivariana |
// Engineer: Fabio Andres Guzman Figueroa |
// |
// Create Date: 19:48:58 05/14/2012 |
// Design Name: |
// Module Name: control_unit |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module control_unit( |
input clk, |
input rst, |
input [15:0] instruction, |
input z, |
input c, |
output reg [7:0] port_addr, |
output reg write_e, |
output reg read_e, |
output reg insel, |
output reg we, |
output reg [2:0] raa, |
output reg [2:0] rab, |
output reg [2:0] wa, |
output reg [2:0] opalu, |
output reg [2:0] sh, |
output reg selpc, |
output reg ldpc, |
output reg ldflag, |
output reg [10:0] naddress, |
output reg selk, |
output reg [7:0] KTE, |
input [10:0] stack_addr, |
output reg wr_en, rd_en, |
output reg [7:0] imm, |
output reg selimm |
); |
|
|
parameter fetch= 5'd0; |
parameter decode= 5'd1; |
|
parameter ldi= 5'd2; |
parameter ldm= 5'd3; |
parameter stm= 5'd4; |
parameter cmp= 5'd5; |
parameter add= 5'd6; |
parameter sub= 5'd7; |
parameter andi= 5'd8; |
parameter oor= 5'd9; |
parameter xori= 5'd10; |
parameter jmp= 5'd11; |
parameter jpz= 5'd12; |
parameter jnz= 5'd13; |
parameter jpc= 5'd14; |
parameter jnc= 5'd15; |
parameter csr= 5'd16; |
parameter ret= 5'd17; |
|
parameter adi= 5'd18; |
parameter csz= 5'd19; |
parameter cnz= 5'd20; |
parameter csc= 5'd21; |
parameter cnc= 5'd22; |
parameter sl0= 5'd23; |
parameter sl1= 5'd24; |
parameter sr0= 5'd25; |
parameter sr1= 5'd26; |
parameter rrl= 5'd27; |
parameter rrr= 5'd28; |
parameter noti= 5'd29; |
|
parameter nop= 5'd30; |
|
wire [4:0] opcode; |
reg [4:0] state; |
|
assign opcode=instruction[15:11]; |
|
always@(posedge clk or posedge rst) |
if (rst) |
state<=decode; |
else |
case (state) |
fetch: state<=decode; |
|
decode: case (opcode) |
2: state<=ldi; |
3: state<=ldm; |
4: state<=stm; |
5: state<=cmp; |
6: state<=add; |
7: state<=sub; |
8: state<=andi; |
9: state<=oor; |
10: state<=xori; |
11: state<=jmp; |
12: state<=jpz; |
13: state<=jnz; |
14: state<=jpc; |
15: state<=jnc; |
16: state<=csr; |
17: state<=ret; |
18: state<=adi; |
19: state<=csz; |
20: state<=cnz; |
21: state<=csc; |
22: state<=cnc; |
23: state<=sl0; |
24: state<=sl1; |
25: state<=sr0; |
26: state<=sr1; |
27: state<=rrl; |
28: state<=rrr; |
29: state<=noti; |
default: state<=nop; |
endcase |
|
ldi: state<=fetch; |
|
ldm: state<=fetch; |
|
stm: state<=fetch; |
|
cmp: state<=fetch; |
|
add: state<=fetch; |
|
sub: state<=fetch; |
|
andi: state<=fetch; |
|
oor: state<=fetch; |
|
xori: state<=fetch; |
|
jmp: state<=fetch; |
|
jpz: state<=fetch; |
|
jnz: state<=fetch; |
|
jpc: state<=fetch; |
|
jnc: state<=fetch; |
|
csr: state<=fetch; |
|
ret: state<=fetch; |
|
adi: state<=fetch; |
|
csz: state<=fetch; |
|
cnz: state<=fetch; |
|
csc: state<=fetch; |
|
cnc: state<=fetch; |
|
sl0: state<=fetch; |
|
sl1: state<=fetch; |
|
sr0: state<=fetch; |
|
sr1: state<=fetch; |
|
rrl: state<=fetch; |
|
rrr: state<=fetch; |
|
noti: state<=fetch; |
|
nop: state<=fetch; |
endcase |
|
|
|
always@(*) |
begin |
port_addr<=0; |
write_e<=0; |
read_e<=0; |
insel<=0; |
we<=0; |
raa<=0; |
rab<=0; |
wa<=0; |
opalu<=4; |
sh<=4; |
selpc<=0; |
ldpc<=1; |
ldflag<=0; |
naddress<=0; |
selk<=0; |
KTE<=0; |
wr_en<=0; |
rd_en<=0; |
imm<=0; |
selimm<=0; |
|
case (state) |
fetch: ldpc<=0; |
|
decode: begin |
ldpc<=0; |
if (opcode==stm) |
begin |
raa<=instruction[10:8]; |
port_addr<=instruction[7:0]; |
end |
else if (opcode==ldm) |
begin |
wa<=instruction[10:8]; |
port_addr<=instruction[7:0]; |
end |
else if (opcode==ret) |
begin |
rd_en<=1; |
end |
end |
|
ldi: begin |
selk<=1; |
KTE<=instruction[7:0]; |
we<=1; |
wa<=instruction[10:8]; |
end |
|
ldm: begin |
wa<=instruction[10:8]; |
we<=1; |
read_e<=1; |
port_addr<=instruction[7:0]; |
end |
|
stm: begin |
raa<=instruction[10:8]; |
write_e<=1; |
port_addr<=instruction[7:0]; |
end |
|
cmp: begin |
ldflag<=1; |
raa<=instruction[10:8]; |
rab<=instruction[7:5]; |
opalu<=6; |
end |
|
add: begin |
raa<=instruction[10:8]; |
rab<=instruction[7:5]; |
wa<=instruction[10:8]; |
insel<=1; |
opalu<=5; |
we<=1; |
end |
|
sub: begin |
raa<=instruction[10:8]; |
rab<=instruction[7:5]; |
wa<=instruction[10:8]; |
insel<=1; |
opalu<=6; |
we<=1; |
end |
|
andi: begin |
raa<=instruction[10:8]; |
rab<=instruction[7:5]; |
wa<=instruction[10:8]; |
insel<=1; |
opalu<=1; |
we<=1; |
end |
|
oor: begin |
raa<=instruction[10:8]; |
rab<=instruction[7:5]; |
wa<=instruction[10:8]; |
insel<=1; |
opalu<=3; |
we<=1; |
end |
|
xori: begin |
raa<=instruction[10:8]; |
rab<=instruction[7:5]; |
wa<=instruction[10:8]; |
insel<=1; |
opalu<=2; |
we<=1; |
end |
|
jmp: begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
end |
|
jpz: if (z) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
end |
|
jnz: if (!z) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
end |
|
|
jpc: if (c) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
end |
|
|
jnc: if (!c) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
end |
|
csr: begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
wr_en<=1; |
end |
|
ret: begin |
naddress<=stack_addr; |
selpc<=1; |
ldpc<=1; |
end |
|
adi: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
imm<=instruction[7:0]; |
selimm<=1; |
insel<=1; |
opalu<=5; |
we<=1; |
end |
|
csz: if (z) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
wr_en<=1; |
end |
|
cnz: if (!z) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
wr_en<=1; |
end |
|
csc: if (c) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
wr_en<=1; |
end |
|
cnc: if (!c) |
begin |
naddress<=instruction[10:0]; |
selpc<=1; |
ldpc<=1; |
wr_en<=1; |
end |
|
sl0: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
sh<=0; |
we<=1; |
end |
|
sl1: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
sh<=5; |
we<=1; |
end |
|
sr0: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
sh<=2; |
we<=1; |
end |
|
sr1: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
sh<=6; |
we<=1; |
end |
|
rrl: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
sh<=1; |
we<=1; |
end |
|
rrr: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
sh<=3; |
we<=1; |
end |
|
noti: begin |
raa<=instruction[10:8]; |
wa<=instruction[10:8]; |
insel<=1; |
opalu<=0; |
we<=1; |
end |
|
nop: opalu<=4; |
|
endcase |
end |
|
|
endmodule |
/natalius_8bit_risc/trunk/processor_core/ALU.v
0,0 → 1,49
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:05:06 05/02/2012 |
// Design Name: |
// Module Name: ALU |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module ALU( |
input [7:0] a, |
input [7:0] b, |
output [7:0] result, |
input [2:0] opalu, |
output zero, carry |
); |
|
reg [7:0] resu; |
|
always@* |
case (opalu) |
0: resu <= ~a; |
1: resu <= a & b; |
2: resu <= a ^ b; |
3: resu <= a | b; |
4: resu <= a; |
5: resu <= a + b; |
6: resu <= a - b; |
default: resu <= a + 1; |
endcase |
|
assign zero=(resu==0); |
assign result=resu; |
assign carry=(a<b); |
|
|
endmodule |
|
/natalius_8bit_risc/trunk/processor_core/shiftbyte.v
0,0 → 1,39
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:22:46 05/02/2012 |
// Design Name: |
// Module Name: shifter |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module shiftbyte( |
input [7:0] din, |
output reg [7:0] dshift, |
input [2:0] sh |
); |
|
always@* |
case (sh) |
0: dshift <= {din[6:0], 0}; |
1: dshift <= {din[6:0], din[7]}; |
2: dshift <= {0, din[7:1]}; |
3: dshift <= {din[0], din[7:1]}; |
4: dshift <= din; |
5: dshift <= {din[6:0], 1}; |
6: dshift <= {1, din[7:1]}; |
default: dshift <= din; |
endcase |
|
endmodule |
/natalius_8bit_risc/trunk/processor_core/data_path.v
0,0 → 1,92
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Universidad Pontificia Bolivariana |
// Engineer: Fabio Andres Guzman Figueroa |
// |
// Create Date: 18:55:46 05/14/2012 |
// Design Name: |
// Module Name: data_path |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module data_path( |
input clk, |
input rst, |
input [7:0] data_in, |
input insel, |
input we, |
input [2:0] raa, |
input [2:0] rab, |
input [2:0] wa, |
input [2:0] opalu, |
input [2:0] sh, |
input selpc, |
input selk, |
input ldpc, |
input ldflag, |
input wr_en, rd_en, |
input [10:0] ninst_addr, |
input [7:0] kte, |
input [7:0] imm, |
input selimm, |
output [7:0] data_out, |
output [10:0] inst_addr, |
output [10:0] stack_addr, |
output reg z,c |
); |
|
wire [7:0] regmux, muxkte, muximm; |
wire [7:0] portA, portB; |
wire [7:0] aluresu; |
wire zero,carry; |
wire [7:0] shiftout; |
|
reg [10:0] PC; |
wire [10:0] fifo_out; |
|
regfile registros(regmux,clk,we,wa,raa,rab,portA,portB); |
ALU alui(portA,muximm,aluresu,opalu,zero,carry); |
shiftbyte shif_reg(aluresu,shiftout,sh); |
LIFO LIFOi(clk,rst,wr_en,rd_en,PC,fifo_out); |
|
assign stack_addr=fifo_out+1; |
assign regmux=insel? shiftout : muxkte; |
assign muxkte=selk? kte : data_in; |
assign muximm=selimm? imm : portB; |
|
always@(posedge clk or posedge rst) |
if (rst) |
begin |
z<=0; |
c<=0; |
end |
else |
if (ldflag) |
begin |
z<=zero; |
c<=carry; |
end |
|
always@(posedge clk or posedge rst) |
if (rst) |
PC<=0; |
else |
if (ldpc) |
if(selpc) |
PC<=ninst_addr; |
else |
PC<=PC+1; |
|
assign inst_addr=PC; |
assign data_out=shiftout; |
|
endmodule |
/natalius_8bit_risc/trunk/processor_core/LIFO.v
0,0 → 1,54
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 11:39:35 05/16/2012 |
// Design Name: |
// Module Name: LIFO |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module LIFO( |
input clk, |
input rst, |
input wr_en, |
input rd_en, |
input [10:0] din, |
output [10:0] dout |
); |
|
|
(* RAM_STYLE="DISTRIBUTED" *) |
reg [3:0] addr; |
reg [10:0] ram [15:0]; |
|
always@(posedge clk) |
if (rst) |
addr<=0; |
else |
begin |
if (wr_en==0 && rd_en==1) //leer |
if (addr>0) |
addr<=addr-1; |
if (wr_en==1 && rd_en==0) //guardar |
if (addr<15) |
addr<=addr+1; |
end |
|
always @(posedge clk) |
if (wr_en) |
ram[addr] <= din; |
|
assign dout = ram[addr]; |
|
endmodule |
/natalius_8bit_risc/trunk/processor_core/instruction_memory.v
0,0 → 1,46
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Universidad Pontificia Bolivariana |
// Engineer: Fabio Andres Guzman Figueroa |
// |
// Create Date: 21:03:05 05/14/2012 |
// Design Name: |
// Module Name: instruction_memory |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module instruction_memory( |
input clk, |
input [10:0] address, |
output reg [15:0] instruction |
); |
|
|
(* RAM_STYLE="BLOCK" *) |
|
reg [15:0] rom [2047:0]; |
wire we; |
initial |
$readmemh("instructions.mem", rom, 0, 2047); |
|
assign we=0; |
|
always @(posedge clk) |
if(we) |
rom[address]<=0; |
else |
instruction <= rom[address]; |
|
|
//assign instruction = rom[address]; |
|
endmodule |