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/pwm_with_dithering/trunk/Implementation_results.txt
0,0 → 1,214
Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
 
 
For minimal implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
Number of Slice Registers: 17 out of 126800 0%
Number of Slice LUTs: 36 out of 63400 0%
Number used as Logic: 36 out of 63400 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 36
Number with an unused Flip Flop: 19 out of 36 52%
Number with an unused LUT: 0 out of 36 0%
Number of fully used LUT-FF pairs: 17 out of 36 47%
Number of unique control sets: 1
 
IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 18 out of 210 8%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
 
Timing Summary: (after synthesis)
---------------
Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)
Minimum input arrival time before clock: 3.646ns
Maximum output required time after clock: 0.742ns
Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 3.387ns| N/A| 0
_BUFGP | HOLD | 0.287ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
For pipelined implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
Number of Slice Registers: 43 out of 126800 0%
Number of Slice LUTs: 49 out of 63400 0%
Number used as Logic: 49 out of 63400 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 50
Number with an unused Flip Flop: 7 out of 50 14%
Number with an unused LUT: 1 out of 50 2%
Number of fully used LUT-FF pairs: 42 out of 50 84%
Number of unique control sets: 2
 
IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 18 out of 210 8%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
 
Timing Summary: (after synthesis)
---------------
Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)
Minimum input arrival time before clock: 1.606ns
Maximum output required time after clock: 0.742ns
Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 2.027ns| N/A| 0
_BUFGP | HOLD | 0.209ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
For inequality based implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
Number of Slice Registers: 17 out of 126800 0%
Number of Slice LUTs: 43 out of 63400 0%
Number used as Logic: 43 out of 63400 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 44
Number with an unused Flip Flop: 27 out of 44 61%
Number with an unused LUT: 1 out of 44 2%
Number of fully used LUT-FF pairs: 16 out of 44 36%
Number of unique control sets: 2
 
IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 18 out of 210 8%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
 
Timing Summary: (after synthesis)
---------------
Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)
Minimum input arrival time before clock: 4.529ns
Maximum output required time after clock: 0.742ns
Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 4.390ns| N/A| 0
_BUFGP | HOLD | 0.287ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
For register based implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
Number of Slice Registers: 30 out of 126800 0%
Number of Slice LUTs: 35 out of 63400 0%
Number used as Logic: 35 out of 63400 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 36
Number with an unused Flip Flop: 6 out of 36 16%
Number with an unused LUT: 1 out of 36 2%
Number of fully used LUT-FF pairs: 29 out of 36 80%
Number of unique control sets: 2
 
IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 18 out of 210 8%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
 
Timing Summary: (after synthesis)
Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)
Minimum input arrival time before clock: 2.410ns
Maximum output required time after clock: 0.742ns
Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 2.436ns| N/A| 0
_BUFGP | HOLD | 0.212ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
For small pipelined implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
Number of Slice Registers: 31 out of 126800 0%
Number of Slice LUTs: 40 out of 63400 0%
Number used as Logic: 40 out of 63400 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 41
Number with an unused Flip Flop: 10 out of 41 24%
Number with an unused LUT: 1 out of 41 2%
Number of fully used LUT-FF pairs: 30 out of 41 73%
Number of unique control sets: 3
 
IO Utilization:
Number of IOs: 18
Number of bonded IOBs: 18 out of 210 8%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
 
Timing Summary: (after synthesis)
Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)
Minimum input arrival time before clock: 1.868ns
Maximum output required time after clock: 0.742ns
Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 2.083ns| N/A| 0
_BUFGP | HOLD | 0.201ns| | 0| 0
----------------------------------------------------------------------------------------------------------

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