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/quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/~$divide.docx
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quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/~$divide.docx
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Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx
===================================================================
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Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx (nonexistent)
quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx
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Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx
===================================================================
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Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx (nonexistent)
quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx
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Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/02_VerilogAlgorithmDesign/alu_8bit.v
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/02_VerilogAlgorithmDesign/alu_8bit.v (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/02_VerilogAlgorithmDesign/alu_8bit.v (nonexistent)
@@ -1,184 +0,0 @@
-`timescale 1ns / 1ps
-
-module ALU_8bit(
- clk,
- rst,
- en,
- ready,
- opcode,
- reg_in_1,
- reg_in_2,
- reg_out,
- reg_bank
- );
-
- input wire clk;
- input wire rst;
- input wire en;
- input wire [7:0] opcode;
- input wire [7:0] reg_in_1;
- input wire [7:0] reg_in_2;
-
- output reg ready;
- output reg [7:0] reg_out;
-
- /* ALU flags steps registers
- N
- Set when the result of the operation was Negative.
- Z
- Set when the result of the operation was Zero.
- C
- Set when the operation resulted in a Carry.
- V
- Set when the operation caused oVerflow.
-
- A carry occurs if the result of an add, subtract, or compare is greater than or equal to 232, or as the result of an inline barrel shifter operation in a move or logical instruction.
- Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than -231.
- */
- `define N 0:0
- `define Z 1:1
- `define C 2:2
- `define V 3:3
- output reg [3:0] reg_bank;
-
- reg [15:0] reg_out_temp;
-
- /* ROL and ROR steps and registers */
- `define R_FIRST_STEP 1'b0
- `define R_SECOND_STEP 1'b1
- reg rotation_step;
-
- /* math steps and registers */
- `define M_FIRST_STEP 2'b00
- `define M_SECOND_STEP 2'b01
- `define M_THIRD_STEP 2'b10
- reg [1:0] math_step;
- reg [7:0] dividend;
- reg [7:0] denom;
- reg [7:0] current;
- reg [7:0] temp_result;
-
- always@(posedge clk) begin
- if (rst == 1'b1) begin
- reg_out_temp <= 16'b0000;
- reg_out <= 8'h00;
- ready <= 1'b0;
- rotation_step <= `R_FIRST_STEP;
- reg_bank <= 4'b0000;
- math_step <= `M_FIRST_STEP;
- current <= 8'h01;
- temp_result <= 8'h00;
- dividend <= 8'h00;
- denom <= 8'h00;
- end else if (en == 1'b1) begin
- ready <= 1'b0;
-
- case(opcode)
- 8'h00:begin /* SUM(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 + reg_in_2]*/
- reg_out <= reg_in_1 + reg_in_2;
- ready <= 1'b1;
- end
-
- 8'h01:begin /* SUB(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 - reg_in_2]*/
- reg_out <= reg_in_1 - reg_in_2;
-
- if (reg_in_2 > reg_in_1) begin
- ready <= 1'b1;
- end
-
- if (reg_in_2 == reg_in_1) begin
- ready <= 1'b1;
- end
-
- ready <= 1'b1;
- end
-
- 8'h02:begin /* MUL(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 * reg_in_2]*/
-
- end
-
- 8'h03:begin /* DIV(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 / reg_in_2]*/
- case(math_step)
- `M_FIRST_STEP:begin
- dividend <= reg_in_1;
- denom <= reg_in_2;
- math_step <= `M_SECOND_STEP;
- end
-
- `M_SECOND_STEP:begin /* shift left to find first bit with value 1 */
- if (denom <= dividend) begin
- denom <= denom << 1;
- current <= current << 1;
- end else begin
- denom <= denom >> 1; /* shift right reg_in_2 to align it with reg_in_1 */
- current <= current >> 1;
- math_step <= `M_THIRD_STEP;
- end
- end
-
- `M_THIRD_STEP:begin
- if (current != 0) begin
- if (dividend >= denom) begin
- dividend <= dividend - denom;
- temp_result <= temp_result | current;
- end
-
- denom <= denom >> 1;
- current <= current >> 1;
- end else begin
- reg_out <= temp_result;
- current <= 8'h01;
- temp_result <= 8'h00;
- math_step <= `M_FIRST_STEP;
- ready <= 1'b1;
- end
- end
- endcase
- end
-
- 8'h04:begin /* MOD(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 % reg_in_2]*/
-
- end
-
- 8'h05:begin /* AND(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 & reg_in_2]*/
- reg_out <= reg_in_1 & reg_in_2;
- ready <= 1'b1;
- end
-
- 8'h06:begin /* OR(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 | reg_in_2]*/
- reg_out <= reg_in_1 | reg_in_2;
- ready <= 1'b1;
- end
-
- 8'h07:begin /* NOT(reg_out) reg_in_1 [reg_out = ~reg_in_1]*/
- reg_out <= ~reg_in_1;
- ready <= 1'b1;
- end
-
- 8'h08:begin /* XOR(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 ^ reg_in_2]*/
- reg_out <= reg_in_1 ^ reg_in_2;
- ready <= 1'b1;
- end
-
- 8'h09:begin /* SHL(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 << reg_in_2]*/
- reg_out <= reg_in_1 << reg_in_2;
- ready <= 1'b1;
- end
-
- 8'h0A:begin /* SHR(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 >> reg_in_2]*/
- reg_out <= reg_in_1 >> reg_in_2;
- ready <= 1'b1;ready <= 1'b1;
- end
-
- 8'h0B:begin /* ROL(reg_out) reg_in_1,reg_in_2 [reg_out = ??]*/
- reg_out <= (reg_in_1 << (reg_in_2 & 8´h07)) | (reg_in_1 >> (8´h08 - (reg_in_2 & 8´h07));
- ready <= 1'b1;
- end
-
- 8'h0C:begin /* ROR(reg_out) reg_in_1,reg_in_2 [reg_out = ??]*/
- reg_out <= (reg_in_1 >> (reg_in_2 & 8´h07)) | (reg_in_1 << (8´h08 - (reg_in_2 & 8´h07));
- end
- endcase
- end
- end
-endmodule
Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV_tb.m
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV_tb.m (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV_tb.m (nonexistent)
@@ -1,18 +0,0 @@
-function DIV_tb()
- div_alu = 0;
- div_real = 0;
-
- for y = 1:65535
- for x = 1:65535
- div_alu = DIV(x,y);
- div_real = fix(x/y);
-
- if (div_alu ~= div_real)
- disp(strcat('not ok! div_alu = ',num2str(div_alu),'; div_real = ',num2str(div_real)));
- return;
- else
- disp(strcat('opcode ok! div_alu = ',num2str(div_alu),'; div_real = ',num2str(div_real)));
- end
- end
- end
-end
\ No newline at end of file
Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MUL.m
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MUL.m (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MUL.m (nonexistent)
@@ -1,7 +0,0 @@
-function X = MUL(D1,D2)
- X = 0;
-
- for loop = 0:(D2 - 1)
- X = X + D1;
- end
-end
\ No newline at end of file
Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MOD.m
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MOD.m (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MOD.m (nonexistent)
@@ -1,17 +0,0 @@
-function [R,zero] = MOD(N,D)
- R = 0;
- X = 0;
- zero = 0;
-
- if (D == 0)
- zero = 1;
- return;
- end
-
- while N >= D
- N = N - D;
- X = X + 1;
- end
-
- R = N;
-end
\ No newline at end of file
Index: quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV.m
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV.m (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV.m (nonexistent)
@@ -1,37 +0,0 @@
-
-function [answer,zero] = DIV(dividend,divisor)
- denom = divisor;
- current = 1;
- answer = 0;
- zero = 0;
-
- if (divisor == 0)
- zero = 1;
- return;
- end
-
- % METHOD 1
- %while (dividend >= divisor)
- % dividend = dividend - divisor;
- % answer = answer + 1;
- %end
- %
-
- while (denom <= dividend)
- denom = fix(bitsll(denom, 1));
- current = fix(bitsll(current, 1));
- end
-
- denom = fix(bitsra(denom, 1));
- current = fix(bitsra(current, 1));
-
- while (current~=0)
- if (dividend >= denom)
- dividend = int16(dividend - denom);
- answer = bitor(answer, current);
- end
-
- current = fix(bitsra(current, 1));
- denom = fix(bitsra(denom, 1));
- end
-end
\ No newline at end of file
Index: quark/trunk/ENG04_RequirementsAnalysis/02_ExternalRequirements/wbspec_b4.pdf
===================================================================
--- quark/trunk/ENG04_RequirementsAnalysis/02_ExternalRequirements/wbspec_b4.pdf (revision 4)
+++ quark/trunk/ENG04_RequirementsAnalysis/02_ExternalRequirements/wbspec_b4.pdf (nonexistent)
@@ -1,14797 +0,0 @@
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