URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

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/single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5 and ECP5-5G sysCONFIG Usage Guide.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5 and ECP5-5G sysCONFIG Usage Guide.pdf

single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5 and ECP5-5G sysCONFIG Usage Guide.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5-5G Versa Development Board User Guide.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5-5G Versa Development Board User Guide.pdf =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5-5G Versa Development Board User Guide.pdf (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5-5G Versa Development Board User Guide.pdf (revision 5)

single-14-segment-display-driver-w-decoder/trunk/Documentation/Lattice_Versa_Board/ECP5-5G Versa Development Board User Guide.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_0.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['_5fmath_5freal',['_MATH_REAL',['../class___m_a_t_h___r_e_a_l.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_1.js (revision 5) @@ -0,0 +1,7 @@ +var searchData= +[ + ['arch',['arch',['../class_a_s_c_i_i_decoder_1_1arch.html',1,'arch'],['../class_display_driverw_decoder___top_1_1arch.html',1,'arch']]], + ['ascii_5fin',['ascii_in',['../class_display_driverw_decoder___top.html#a11737d50bbf001c0d64a327a2afca193',1,'DisplayDriverwDecoder_Top']]], + ['asciidecoder',['ASCIIDecoder',['../class_a_s_c_i_i_decoder.html',1,'']]], + ['asciidecoder_2evhd',['ASCIIDecoder.vhd',['../_a_s_c_i_i_decoder_8vhd.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_2.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['button',['button',['../class_display_driver_wrapper.html#a5b0cc1fc904e8a360edefca8a94aad6b',1,'DisplayDriverWrapper']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_3.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['clk',['clk',['../class_display_driverw_decoder___top.html#a4a4609c199d30b3adebbeb3a01276ec5',1,'DisplayDriverwDecoder_Top.clk()'],['../class_display_driver_wrapper.html#a4a4609c199d30b3adebbeb3a01276ec5',1,'DisplayDriverWrapper.clk()']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_4.js (revision 5) @@ -0,0 +1,9 @@ +var searchData= +[ + ['disp_5fdata',['disp_data',['../class_display_driverw_decoder___top.html#afe85e1682ca9b85576a5169bef98848c',1,'DisplayDriverwDecoder_Top.disp_data()'],['../class_display_driver_wrapper.html#afe85e1682ca9b85576a5169bef98848c',1,'DisplayDriverWrapper.disp_data()']]], + ['disp_5fsel',['disp_sel',['../class_display_driverw_decoder___top.html#ac39d5faa22b7c7b88914e8915f901d69',1,'DisplayDriverwDecoder_Top.disp_sel()'],['../class_display_driver_wrapper.html#ac39d5faa22b7c7b88914e8915f901d69',1,'DisplayDriverWrapper.disp_sel()']]], + ['displaydriverwdecoder_5ftop',['DisplayDriverwDecoder_Top',['../class_display_driverw_decoder___top.html',1,'']]], + ['displaydriverwdecoder_5ftop_2evhd',['DisplayDriverwDecoder_Top.vhd',['../_display_driverw_decoder___top_8vhd.html',1,'']]], + ['displaydriverwrapper',['DisplayDriverWrapper',['../class_display_driver_wrapper.html',1,'']]], + ['displaydriverwrapper_2evhd',['DisplayDriverWrapper.vhd',['../_display_driver_wrapper_8vhd.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_5.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['my_20personal_20index_20page',['My Personal Index Page',['../index.html',1,'']]], + ['math_5freal',['MATH_REAL',['../class_m_a_t_h___r_e_a_l.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_6.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['reset',['reset',['../class_display_driverw_decoder___top.html#aad8dc6359d9e23dabcbf342fadf2fa06',1,'DisplayDriverwDecoder_Top']]], + ['rst',['rst',['../class_display_driver_wrapper.html#ae0366c76519a377d49a533f4eff582ad',1,'DisplayDriverWrapper']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/all_7.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['wr_5fen',['wr_en',['../class_display_driverw_decoder___top.html#a8f9235710fc037196ed1f7fa93aa0ef3',1,'DisplayDriverwDecoder_Top']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_0.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['_5fmath_5freal',['_MATH_REAL',['../class___m_a_t_h___r_e_a_l.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_1.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['arch',['arch',['../class_a_s_c_i_i_decoder_1_1arch.html',1,'arch'],['../class_display_driverw_decoder___top_1_1arch.html',1,'arch']]], + ['asciidecoder',['ASCIIDecoder',['../class_a_s_c_i_i_decoder.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_2.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['displaydriverwdecoder_5ftop',['DisplayDriverwDecoder_Top',['../class_display_driverw_decoder___top.html',1,'']]], + ['displaydriverwrapper',['DisplayDriverWrapper',['../class_display_driver_wrapper.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/classes_3.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['math_5freal',['MATH_REAL',['../class_m_a_t_h___r_e_a_l.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/close.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/close.png =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/close.png (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/close.png (revision 5)

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/close.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_0.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['asciidecoder_2evhd',['ASCIIDecoder.vhd',['../_a_s_c_i_i_decoder_8vhd.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

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+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/files_1.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['displaydriverwdecoder_5ftop_2evhd',['DisplayDriverwDecoder_Top.vhd',['../_display_driverw_decoder___top_8vhd.html',1,'']]], + ['displaydriverwrapper_2evhd',['DisplayDriverWrapper.vhd',['../_display_driver_wrapper_8vhd.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/mag_sel.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/mag_sel.png =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/mag_sel.png (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/mag_sel.png (revision 5)

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/mag_sel.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/nomatches.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/nomatches.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/nomatches.html (revision 5) @@ -0,0 +1,12 @@ + + + + + + + +

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/nomatches.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/pages_0.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['my_20personal_20index_20page',['My Personal Index Page',['../index.html',1,'']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search.css =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search.css (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search.css (revision 5) @@ -0,0 +1,271 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#MSearchBox { + white-space : nowrap; + float: none; + margin-top: 8px; + right: 0px; + width: 170px; + height: 24px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:115px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; + -webkit-border-radius: 0px; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:8px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 10001; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; + z-index:10000; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +span.SRScope { + padding-left: 4px; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} + +/*---------------- External search page results */ + +.searchresult { + background-color: #F0F3F8; +} + +.pages b { + color: white; + padding: 5px 5px 3px 5px; + background-image: url("../tab_a.png"); + background-repeat: repeat-x; + text-shadow: 0 1px 1px #000000; +} + +.pages { + line-height: 17px; + margin-left: 4px; + text-decoration: none; +} + +.hl { + font-weight: bold; +} + +#searchresults { + margin-bottom: 20px; +} + +.searchpages { + margin-top: 10px; +} + Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search.js (revision 5) @@ -0,0 +1,791 @@ +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_l.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_m.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_m.png =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_m.png (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_m.png (revision 5)

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_m.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_r.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_r.png =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_r.png (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_r.png (revision 5)

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/search_r.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/searchdata.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/searchdata.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/searchdata.js (revision 5) @@ -0,0 +1,27 @@ +var indexSectionsWithContent = +{ + 0: "_abcdmrw", + 1: "_adm", + 2: "ad", + 3: "abcdrw", + 4: "m" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "variables", + 4: "pages" +}; + +var indexSectionLabels = +{ + 0: "All", + 1: "Classes", + 2: "Files", + 3: "Variables", + 4: "Pages" +}; + Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_0.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['ascii_5fin',['ascii_in',['../class_display_driverw_decoder___top.html#a11737d50bbf001c0d64a327a2afca193',1,'DisplayDriverwDecoder_Top']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_1.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['button',['button',['../class_display_driver_wrapper.html#a5b0cc1fc904e8a360edefca8a94aad6b',1,'DisplayDriverWrapper']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_2.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['clk',['clk',['../class_display_driverw_decoder___top.html#a4a4609c199d30b3adebbeb3a01276ec5',1,'DisplayDriverwDecoder_Top.clk()'],['../class_display_driver_wrapper.html#a4a4609c199d30b3adebbeb3a01276ec5',1,'DisplayDriverWrapper.clk()']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_3.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['disp_5fdata',['disp_data',['../class_display_driverw_decoder___top.html#afe85e1682ca9b85576a5169bef98848c',1,'DisplayDriverwDecoder_Top.disp_data()'],['../class_display_driver_wrapper.html#afe85e1682ca9b85576a5169bef98848c',1,'DisplayDriverWrapper.disp_data()']]], + ['disp_5fsel',['disp_sel',['../class_display_driverw_decoder___top.html#ac39d5faa22b7c7b88914e8915f901d69',1,'DisplayDriverwDecoder_Top.disp_sel()'],['../class_display_driver_wrapper.html#ac39d5faa22b7c7b88914e8915f901d69',1,'DisplayDriverWrapper.disp_sel()']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_4.js (revision 5) @@ -0,0 +1,5 @@ +var searchData= +[ + ['reset',['reset',['../class_display_driverw_decoder___top.html#aad8dc6359d9e23dabcbf342fadf2fa06',1,'DisplayDriverwDecoder_Top']]], + ['rst',['rst',['../class_display_driver_wrapper.html#ae0366c76519a377d49a533f4eff582ad',1,'DisplayDriverWrapper']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.html (revision 5) @@ -0,0 +1,26 @@ + + + + + + + + + +

+ +

Searching...

No Matches

+ +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.js =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.js (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/search/variables_5.js (revision 5) @@ -0,0 +1,4 @@ +var searchData= +[ + ['wr_5fen',['wr_en',['../class_display_driverw_decoder___top.html#a8f9235710fc037196ed1f7fa93aa0ef3',1,'DisplayDriverwDecoder_Top']]] +]; Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_a_s_c_i_i_decoder_8vhd.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_a_s_c_i_i_decoder_8vhd.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_a_s_c_i_i_decoder_8vhd.html (revision 5) @@ -0,0 +1,89 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd File Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

ASCII decoding table with I/O control logic. +More...

+ + + + + + +

+Entities
ASCIIDecoder	entity

arch	architecture

Detailed Description

ASCII decoding table with I/O control logic.

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_a_s_c_i_i_decoder_8vhd.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_display_driver_wrapper_8vhd.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_display_driver_wrapper_8vhd.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/_display_driver_wrapper_8vhd.html (revision 5) @@ -73,8 +73,6 @@ Entities DisplayDriverWrapper entity -arch architecture -

Detailed Description

Top wrapper for design FPGA prove.

Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/annotated.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/annotated.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/annotated.html (revision 5) @@ -65,10 +65,11 @@

Here is a list of all design unit members with links to the Entities they belong to:

[detail level 12]

- - - - + + + + +

▼CDisplayDriverwDecoder_Top	Top entity of the display driver
CDisplayDriverwDecoder_Top.arch	Architecture definition of the DisplayDriverwDecoder_Top
▼CDisplayDriverWrapper
CDisplayDriverWrapper.arch
▼CASCIIDecoder
CASCIIDecoder.arch
▼CDisplayDriverwDecoder_Top	Top entity of the display driver
CDisplayDriverwDecoder_Top.arch	Architecture definition of the DisplayDriverwDecoder_Top
CDisplayDriverWrapper

Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l-members.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l-members.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l-members.html (revision 5) @@ -0,0 +1,128 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: Member List + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

This is the complete list of members for MATH_REAL, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

""**X,Y, (defined in MATH_REAL)	MATH_REAL	Function
""**X,Y, (defined in MATH_REAL)	MATH_REAL	Function
"MOD"X,Y,X,Y, (defined in MATH_REAL)	MATH_REAL	Function
ARCCOSX, (defined in MATH_REAL)	MATH_REAL	Function
ARCCOSHX, (defined in MATH_REAL)	MATH_REAL	Function
ARCSINX, (defined in MATH_REAL)	MATH_REAL	Function
ARCSINHX, (defined in MATH_REAL)	MATH_REAL	Function
ARCTANY, (defined in MATH_REAL)	MATH_REAL	Function
ARCTANY,X, (defined in MATH_REAL)	MATH_REAL	Function
ARCTANHX, (defined in MATH_REAL)	MATH_REAL	Function
BASE_EPS (defined in MATH_REAL)	MATH_REAL	Constant
CBRTX, (defined in MATH_REAL)	MATH_REAL	Function
CEILX, (defined in MATH_REAL)	MATH_REAL	Function
CORDICX0,Y0,Z0,N,CORDIC_MODE, (defined in MATH_REAL)	MATH_REAL	Function
CORDIC_MODE_TYPE (defined in MATH_REAL)	MATH_REAL	Type
COSX, (defined in MATH_REAL)	MATH_REAL	Function
COSHX, (defined in MATH_REAL)	MATH_REAL	Function
EPSILON (defined in MATH_REAL)	MATH_REAL	Constant
EXPX, (defined in MATH_REAL)	MATH_REAL	Function
FLOORX, (defined in MATH_REAL)	MATH_REAL	Function
ILOGBX, (defined in MATH_REAL)	MATH_REAL	Function
KC (defined in MATH_REAL)	MATH_REAL	Constant
LDEXPX,N, (defined in MATH_REAL)	MATH_REAL	Function
LOGX, (defined in MATH_REAL)	MATH_REAL	Function
LOGX,BASE, (defined in MATH_REAL)	MATH_REAL	Function
LOG10X, (defined in MATH_REAL)	MATH_REAL	Function
LOG2X, (defined in MATH_REAL)	MATH_REAL	Function
MATH_E_P10 (defined in MATH_REAL)	MATH_REAL	Constant
MATH_E_P2 (defined in MATH_REAL)	MATH_REAL	Constant
MATH_EIGHT_PI (defined in MATH_REAL)	MATH_REAL	Constant
MAX_COUNT (defined in MATH_REAL)	MATH_REAL	Constant
MAX_ITER (defined in MATH_REAL)	MATH_REAL	Constant
NATURAL_VECTOR (defined in MATH_REAL)	MATH_REAL	Type
POWER_OF_2_SERIESD,INITIAL_VALUE,NUMBER_OF_VALUES, (defined in MATH_REAL)	MATH_REAL	Function
QUADRANT (defined in MATH_REAL)	MATH_REAL	Subtype
REAL_ARR_2 (defined in MATH_REAL)	MATH_REAL	Subtype
REAL_ARR_3 (defined in MATH_REAL)	MATH_REAL	Subtype
REAL_VECTOR (defined in MATH_REAL)	MATH_REAL	Type
REAL_VECTOR_N (defined in MATH_REAL)	MATH_REAL	Subtype
REALMAXX,Y,X,Y, (defined in MATH_REAL)	MATH_REAL	Function
REALMINX,Y,X,Y, (defined in MATH_REAL)	MATH_REAL	Function
ROUNDX, (defined in MATH_REAL)	MATH_REAL	Function
SIGNX, (defined in MATH_REAL)	MATH_REAL	Function
SINX, (defined in MATH_REAL)	MATH_REAL	Function
SINHX, (defined in MATH_REAL)	MATH_REAL	Function
SQRTX, (defined in MATH_REAL)	MATH_REAL	Function
TANX, (defined in MATH_REAL)	MATH_REAL	Function
TANHX, (defined in MATH_REAL)	MATH_REAL	Function
TRUNCX, (defined in MATH_REAL)	MATH_REAL	Function
TWO_AT_MINUS (defined in MATH_REAL)	MATH_REAL	Constant
UNIFORMSEED1,SEED2,SEED1,SEED2,X, (defined in MATH_REAL)	MATH_REAL	Procedure

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l-members.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l.html (revision 5) @@ -0,0 +1,216 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: MATH_REAL Package Body Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

+Package >> MATH_REAL
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions
+REAL_VECTOR	POWER_OF_2_SERIES ( +D: in in NATURAL_VECTOR +INITIAL_VALUE: in in REAL +NUMBER_OF_VALUES: in in NATURAL + )
+REAL_ARR_3	CORDIC ( +X0: in in REAL +Y0: in in REAL +Z0: in in REAL +N: in in NATURAL +CORDIC_MODE: in in CORDIC_MODE_TYPE + )
+REAL	SIGN ( X: in in REAL )
+REAL	CEIL ( X: in in REAL )
+REAL	FLOOR ( X: in in REAL )
+REAL	ROUND ( X: in in REAL )
+REAL	TRUNC ( X: in in REAL )
+REAL	"MOD" ( X: in in REAL , Y: in in REAL )
+REAL	REALMAX ( X: in in REAL , Y: in in REAL )
+REAL	REALMIN ( X: in in REAL , Y: in in REAL )
+REAL	SQRT ( X: in in REAL )
+REAL	CBRT ( X: in in REAL )
+REAL	"" ( X: in in INTEGER , Y: in in REAL** )
+REAL	"" ( X: in in REAL , Y: in in REAL** )
+REAL	EXP ( X: in in REAL )
+INTEGER	ILOGB ( X: in in REAL )
+REAL	LDEXP ( X: in in REAL , N: in in INTEGER )
+REAL	LOG ( X: in in REAL )
+REAL	LOG2 ( X: in in REAL )
+REAL	LOG10 ( X: in in REAL )
+REAL	LOG ( X: in in REAL , BASE: in in REAL )
+REAL	SIN ( X: in in REAL )
+REAL	COS ( X: in in REAL )
+REAL	TAN ( X: in in REAL )
+REAL	ARCSIN ( X: in in REAL )
+REAL	ARCCOS ( X: in in REAL )
+REAL	ARCTAN ( Y: in in REAL )
+REAL	ARCTAN ( Y: in in REAL , X: in in REAL )
+REAL	SINH ( X: in in REAL )
+REAL	COSH ( X: in in REAL )
+REAL	TANH ( X: in in REAL )
+REAL	ARCSINH ( X: in in REAL )
+REAL	ARCCOSH ( X: in in REAL )
+REAL	ARCTANH ( X: in in REAL )

+ + +

+Procedures
+	UNIFORM( +variable SEED1: inout POSITIVE + variable SEED2: inout POSITIVE + variable X: out REAL + )

+ + + + + + + + + + +

+Constants
+MATH_E_P2	REAL := 7 . 38905_60989_30650
+MATH_E_P10	REAL := 22026 . 46579_48067_17
+MATH_EIGHT_PI	REAL := 25 . 13274_12287_18345_90770_115
+MAX_ITER	INTEGER := 27
+MAX_COUNT	INTEGER := 150
+BASE_EPS	REAL := 0 . 00001
+KC	REAL := 6 . 0725293500888142e - 01
+TWO_AT_MINUS	REAL_VECTOR := POWER_OF_2_SERIES ( NATURAL_VECTOR ' ( 100 , 90 ) , 1 . 0 , MAX_ITER )
+EPSILON	REAL_VECTOR_N := ( 7 . 8539816339744827e - 01 , 4 . 6364760900080606e - 01 , 2 . 4497866312686413e - 01 , 1 . 2435499454676144e - 01 , 6 . 2418809995957351e - 02 , 3 . 1239833430268277e - 02 , 1 . 5623728620476830e - 02 , 7 . 8123410601011116e - 03 , 3 . 9062301319669717e - 03 , 1 . 9531225164788189e - 03 , 9 . 7656218955931937e - 04 , 4 . 8828121119489829e - 04 , 2 . 4414062014936175e - 04 , 1 . 2207031189367021e - 04 , 6 . 1035156174208768e - 05 , 3 . 0517578115526093e - 05 , 1 . 5258789061315760e - 05 , 7 . 6293945311019699e - 06 , 3 . 8146972656064960e - 06 , 1 . 9073486328101870e - 06 , 9 . 5367431640596080e - 07 , 4 . 7683715820308876e - 07 , 2 . 3841857910155801e - 07 , 1 . 1920928955078067e - 07 , 5 . 9604644775390553e - 08 , 2 . 9802322387695303e - 08 , 1 . 4901161193847654e - 08 , 7 . 4505805969238281e - 09 )

+ + + + +

+Types
+REAL_VECTOR	array ( NATURAL range <> ) of REAL
+NATURAL_VECTOR	array ( NATURAL range <> ) of NATURAL
+CORDIC_MODE_TYPE	( ROTATION , VECTORING )

+ + + + + +

+Subtypes
+REAL_VECTOR_N	REAL_VECTOR ( 0 to MAX_ITER )
+REAL_ARR_2	REAL_VECTOR ( 0 to 1 )
+REAL_ARR_3	REAL_VECTOR ( 0 to 2 )
+QUADRANT	INTEGER range 0 to 3

The documentation for this class was generated from the following file:

C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/._Real_._Math_.vhd

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class___m_a_t_h___r_e_a_l.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder-members.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder-members.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder-members.html (revision 5) @@ -0,0 +1,84 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: Member List + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

This is the complete list of members for ASCIIDecoder, including all inherited members.

+ + + + + + + + +

ascii_in (defined in ASCIIDecoder)	ASCIIDecoder	Port
clk (defined in ASCIIDecoder)	ASCIIDecoder	Port
disp_data (defined in ASCIIDecoder)	ASCIIDecoder	Port
ieee (defined in ASCIIDecoder)	ASCIIDecoder	Library
numeric_std (defined in ASCIIDecoder)	ASCIIDecoder	use clause
reset (defined in ASCIIDecoder)	ASCIIDecoder	Port
std_logic_1164 (defined in ASCIIDecoder)	ASCIIDecoder	use clause

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder-members.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder.html (revision 5) @@ -0,0 +1,110 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: ASCIIDecoder Entity Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

+ + + + +

+Entities
arch	architecture

+ + +

+Libraries
+ieee

+ + + +

+Use Clauses
+std_logic_1164
+numeric_std

+ + + + + +

+Ports
+clk	in std_logic
+reset	in std_logic
+ascii_in	in std_logic_vector ( 7 downto 0 )
+disp_data	out std_logic_vector ( 13 downto 0 )

The documentation for this class was generated from the following file:

C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder_1_1arch.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder_1_1arch.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder_1_1arch.html (revision 5) @@ -0,0 +1,81 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: arch Architecture Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

ASCIIDecoder
arch

+ +

The documentation for this class was generated from the following file:

C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_a_s_c_i_i_decoder_1_1arch.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driver_wrapper-members.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driver_wrapper-members.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driver_wrapper-members.html (revision 5) @@ -66,16 +66,15 @@

This is the complete list of members for DisplayDriverWrapper, including all inherited members.

- - - - - - - - + + + + + + +

ascii_in	DisplayDriverwDecoder_Top	Port
button	DisplayDriverWrapper	Port
clk	DisplayDriverWrapper	Port
disp_data	DisplayDriverWrapper	Port
disp_sel	DisplayDriverWrapper	Port
ieee (defined in DisplayDriverWrapper)	DisplayDriverWrapper	Library
numeric_std (defined in DisplayDriverwDecoder_Top)	DisplayDriverwDecoder_Top	use clause
reset	DisplayDriverWrapper	Port
button	DisplayDriverWrapper	Port
clk	DisplayDriverWrapper	Port
disp_data	DisplayDriverWrapper	Port
disp_sel	DisplayDriverWrapper	Port
ieee (defined in DisplayDriverWrapper)	DisplayDriverWrapper	Library
rst	DisplayDriverWrapper	Port
std_logic_1164 (defined in DisplayDriverWrapper)	DisplayDriverWrapper	use clause
std_logic_unsigned (defined in DisplayDriverWrapper)	DisplayDriverWrapper	use clause
syn_force_pad (defined in DisplayDriverWrapper)	DisplayDriverWrapper	Attribute

/single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driver_wrapper.html

61,6 → 61,7

67,28 → 68,7

106,18 → 86,23

126,7 → 111,7

/single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top-members.html

68,12 → 68,13

/single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top.html

70,14 → 70,6

106,7 → 98,10

135,8 → 130,8

145,7 → 140,7

154,7 → 149,16

/single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top_1_1arch-members.html

0,0 → 1,85

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top_1_1arch-members.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top_1_1arch.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top_1_1arch.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_display_driverw_decoder___top_1_1arch.html (revision 5) @@ -63,6 +63,10 @@

@@ -70,6 +74,24 @@

Architecture definition of the DisplayDriverwDecoder_Top. More...

+ + + +

+Processes
+ascii_in_reg	( clk )

+ + +

+Signals
+ascii_reg	std_logic_vector ( 7 downto 0 )

+ + + +

+Attributes
+syn_noprune	boolean
+syn_noprune	ascii_reg : signal is true

Detailed Description

Architecture definition of the DisplayDriverwDecoder_Top.

Detailed description of the DisplayDriverwDecoder_Top architecture.

/single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_m_a_t_h___r_e_a_l-members.html

0,0 → 1,127

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_m_a_t_h___r_e_a_l-members.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_m_a_t_h___r_e_a_l.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_m_a_t_h___r_e_a_l.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_m_a_t_h___r_e_a_l.html (revision 5) @@ -0,0 +1,196 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: MATH_REAL Package Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

+Package Body >> MATH_REAL
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions
+REAL	SIGN ( X: in in REAL )
+REAL	CEIL ( X: in in REAL )
+REAL	FLOOR ( X: in in REAL )
+REAL	ROUND ( X: in in REAL )
+REAL	TRUNC ( X: in in REAL )
+REAL	"MOD" ( X: in in REAL , Y: in in REAL )
+REAL	REALMAX ( X: in in REAL , Y: in in REAL )
+REAL	REALMIN ( X: in in REAL , Y: in in REAL )
+REAL	SQRT ( X: in in REAL )
+REAL	CBRT ( X: in in REAL )
+REAL	"" ( X: in in INTEGER , Y: in in REAL** )
+REAL	"" ( X: in in REAL , Y: in in REAL** )
+REAL	EXP ( X: in in REAL )
+REAL	LOG ( X: in in REAL )
+REAL	LOG2 ( X: in in REAL )
+REAL	LOG10 ( X: in in REAL )
+REAL	LOG ( X: in in REAL , BASE: in in REAL )
+REAL	SIN ( X: in in REAL )
+REAL	COS ( X: in in REAL )
+REAL	TAN ( X: in in REAL )
+REAL	ARCSIN ( X: in in REAL )
+REAL	ARCCOS ( X: in in REAL )
+REAL	ARCTAN ( Y: in in REAL )
+REAL	ARCTAN ( Y: in in REAL , X: in in REAL )
+REAL	SINH ( X: in in REAL )
+REAL	COSH ( X: in in REAL )
+REAL	TANH ( X: in in REAL )
+REAL	ARCSINH ( X: in in REAL )
+REAL	ARCCOSH ( X: in in REAL )
+REAL	ARCTANH ( X: in in REAL )

+ + +

+Procedures
+	UNIFORM( +variable SEED1: inout POSITIVE + variable SEED2: inout POSITIVE + variable X: out REAL + )

+ + + + + + + + + + + + + + + + + + + + +

+Constants
+CopyRightNotice	STRING := " Copyright 1996 IEEE. All rights reserved. "
+MATH_E	REAL := 2 . 71828_18284_59045_23536
+MATH_1_OVER_E	REAL := 0 . 36787_94411_71442_32160
+MATH_PI	REAL := 3 . 14159_26535_89793_23846
+MATH_2_PI	REAL := 6 . 28318_53071_79586_47693
+MATH_1_OVER_PI	REAL := 0 . 31830_98861_83790_67154
+MATH_PI_OVER_2	REAL := 1 . 57079_63267_94896_61923
+MATH_PI_OVER_3	REAL := 1 . 04719_75511_96597_74615
+MATH_PI_OVER_4	REAL := 0 . 78539_81633_97448_30962
+MATH_3_PI_OVER_2	REAL := 4 . 71238_89803_84689_85769
+MATH_LOG_OF_2	REAL := 0 . 69314_71805_59945_30942
+MATH_LOG_OF_10	REAL := 2 . 30258_50929_94045_68402
+MATH_LOG2_OF_E	REAL := 1 . 44269_50408_88963_4074
+MATH_LOG10_OF_E	REAL := 0 . 43429_44819_03251_82765
+MATH_SQRT_2	REAL := 1 . 41421_35623_73095_04880
+MATH_1_OVER_SQRT_2	REAL := 0 . 70710_67811_86547_52440
+MATH_SQRT_PI	REAL := 1 . 77245_38509_05516_02730
+MATH_DEG_TO_RAD	REAL := 0 . 01745_32925_19943_29577
+MATH_RAD_TO_DEG	REAL := 57 . 29577_95130_82320_87680

The documentation for this class was generated from the following file:

C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/._Real_._Math_.vhd

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/class_m_a_t_h___r_e_a_l.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/classes.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/classes.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/classes.html (revision 5) @@ -63,15 +63,16 @@

Design Units

a | d

- - - + +

DisplayDriverWrapper

DisplayDriverwDecoder_Top

ASCIIDecoder

DisplayDriverwDecoder_Top

a | d

Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_67acf7b6fc85adc0d2a4833e552045c6.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_67acf7b6fc85adc0d2a4833e552045c6.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_67acf7b6fc85adc0d2a4833e552045c6.html (revision 5) @@ -0,0 +1,82 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1 Directory Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

+ + +

+Directories

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_67acf7b6fc85adc0d2a4833e552045c6.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_7478c16ef27c7b3161fbacf7f6543ec1.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_7478c16ef27c7b3161fbacf7f6543ec1.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_7478c16ef27c7b3161fbacf7f6543ec1.html (revision 5) @@ -0,0 +1,82 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build Directory Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

Lattice_FPGA_Build

+ +

+ + +

+Directories

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_7478c16ef27c7b3161fbacf7f6543ec1.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_cf15ebe01e8daa991a4e7b750bde6f3e.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_cf15ebe01e8daa991a4e7b750bde6f3e.html (nonexistent) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_cf15ebe01e8daa991a4e7b750bde6f3e.html (revision 5) @@ -0,0 +1,78 @@ + + + + + + + +Single 14 Segment Display Driver with Limited ASCII Decoder: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/syntmp Directory Reference + + + + + + + + + +

+ + + + + + +

Single 14 Segment Display Driver with Limited ASCII Decoder + 0.1 +

+ + + + + + +

+ +

+ + +

+ +

+ + + +

single-14-segment-display-driver-w-decoder/trunk/Documentation/html/dir_cf15ebe01e8daa991a4e7b750bde6f3e.html Property changes : Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/files.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/files.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/files.html (revision 5) @@ -65,8 +65,9 @@

Here is a list of all documented files with brief descriptions:

- - + + +

DisplayDriverwDecoder_Top.vhd	Display Driver With Decoder Top Level Module
DisplayDriverWrapper.vhd	Top wrapper for design FPGA prove
ASCIIDecoder.vhd	ASCII decoding table with I/O control logic
DisplayDriverwDecoder_Top.vhd	Display Driver With Decoder Top Level Module
DisplayDriverWrapper.vhd	Top wrapper for design FPGA prove

Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/functions.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/functions.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/functions.html (revision 5) @@ -71,8 +71,8 @@ , DisplayDriverWrapper

disp_data -: DisplayDriverwDecoder_Top -, DisplayDriverWrapper +: DisplayDriverwDecoder_Top +, DisplayDriverWrapper

disp_sel : DisplayDriverwDecoder_Top @@ -80,8 +80,13 @@

reset : DisplayDriverwDecoder_Top -, DisplayDriverWrapper

rst +: DisplayDriverWrapper +

wr_en +: DisplayDriverwDecoder_Top +

Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/functions_vars.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/functions_vars.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/functions_vars.html (revision 5) @@ -71,8 +71,8 @@ , DisplayDriverWrapper

disp_data -: DisplayDriverwDecoder_Top -, DisplayDriverWrapper +: DisplayDriverwDecoder_Top +, DisplayDriverWrapper

disp_sel : DisplayDriverwDecoder_Top @@ -80,8 +80,13 @@

reset : DisplayDriverwDecoder_Top -, DisplayDriverWrapper

rst +: DisplayDriverWrapper +

wr_en +: DisplayDriverwDecoder_Top +

Index: single-14-segment-display-driver-w-decoder/trunk/Documentation/html/hierarchy.html =================================================================== --- single-14-segment-display-driver-w-decoder/trunk/Documentation/html/hierarchy.html (revision 4) +++ single-14-segment-display-driver-w-decoder/trunk/Documentation/html/hierarchy.html (revision 5) @@ -67,8 +67,9 @@

Go to the graphical class hierarchy

This inheritance list is sorted roughly, but not completely, alphabetically:

[detail level 12]

- - + + +

▼CDisplayDriverWrapper
CDisplayDriverwDecoder_Top	Top entity of the display driver
CASCIIDecoder
▼CDisplayDriverWrapper
CDisplayDriverwDecoder_Top	Top entity of the display driver

The module contains: + -# Input data register to hold the ASCII symbol codes + -# Decoder to translate the code to 14-segment display word + -# here is also the driver +

+ +#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016 +#install: C:\lscc\diamond\3.8_x64\synpbase +#OS: Windows 8 6.2 +#Hostname: DESKTOP-1AUKF7V + +# Fri Jan 13 00:54:37 2017 + +#Implementation: impl1 + +Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +@N:CD720 : std.vhd(123) | Setting time resolution to ns +@N: : DisplayDriverWrapper.vhd(15) | Top entity is set to DisplayDriverWrapper. +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling +VHDL syntax check successful! +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling +@N:CD630 : DisplayDriverWrapper.vhd(15) | Synthesizing work.displaydriverwrapper.arch. +@W:CD638 : DisplayDriverWrapper.vhd(38) | Signal empty is undriven. Either assign the signal a value or remove the signal declaration. +@N:CD630 : DisplayDriverwDecoder_Top.vhd(16) | Synthesizing work.displaydriverwdecoder_top.arch. +Post processing for work.displaydriverwdecoder_top.arch +Post processing for work.displaydriverwrapper.arch +@N:CL159 : DisplayDriverWrapper.vhd(20) | Input button is unused. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:37 2017 + +###########################################################] +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:37 2017 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:37 2017 + +###########################################################] +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:39 2017 + +###########################################################] +Pre-mapping Report + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version L-2016.03L-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@A:MF827 : | No constraint file specified. +Linked File: DisplayDriverwDecoder_impl1_scck.rpt +Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file +@N:MF248 : | Running in 64-bit mode. +@N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + + +Clock Summary +***************** + +Start Requested Requested Clock Clock Clock +Clock Frequency Period Type Group Load +----------------------------------------------------------------------------------------------------- +DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8 +===================================================================================================== + +@W:MT529 : displaydriverwdecoder_top.vhd(76) | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri Jan 13 00:54:39 2017 + +###########################################################] +Map & Optimize Report + +Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version L-2016.03L-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@N:MF248 : | Running in 64-bit mode. +@N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Available hyper_sources - for debug and ip models + None Found + +@N:MT206 : | Auto Constrain mode is enabled + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +@N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================== Non-Gated/Non-Generated Clocks =============================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------------- +ClockId0001 clk port 8 DDwD_Top.ascii_reg[6] +============================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB) + +Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) + +Writing EDIF Netlist and constraint files +@N:FX1056 : | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi +L-2016.03L-1 +@N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + +@W:MT420 : | Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri Jan 13 00:54:42 2017 +# + + +Top view: DisplayDriverWrapper +Requested Frequency: 1220.4 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): +@N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: -0.145 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------ +DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0 +==================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------- +DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths - +=========================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: DisplayDriverWrapper|clk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145 +DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145 +DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145 +DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145 +DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145 +DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145 +DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145 +DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145 +DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145 +DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145 +DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145 +DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145 +DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145 +DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145 +DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145 +=============================================================================================================== + + + +Worst Path Information +View Worst Path in Analyst +*********************** + + +Path information for path number 1: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[0] / Q + Ending point: DDwD_Top.ascii_reg[0] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 - +ascii_reg[0] Net - - - - 1 +DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 2: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[1] / Q + Ending point: DDwD_Top.ascii_reg[1] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 - +ascii_reg[1] Net - - - - 1 +DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 3: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[2] / Q + Ending point: DDwD_Top.ascii_reg[2] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 - +ascii_reg[2] Net - - - - 1 +DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 4: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[3] / Q + Ending point: DDwD_Top.ascii_reg[3] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 - +ascii_reg[3] Net - - - - 1 +DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 5: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[4] / Q + Ending point: DDwD_Top.ascii_reg[4] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 - +ascii_reg[4] Net - - - - 1 +DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 - +======================================================================================= + + + +##### END OF TIMING REPORT #####] + +Constraints that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um5g_45f-8 + +Register bits: 8 of 43848 (0%) +PIC Latch: 0 +I/O cells: 18 + + +Details: +FD1S3IX: 5 +FD1S3JX: 3 +GSR: 1 +IB: 2 +OB: 16 +PUR: 1 +VHI: 2 +VLO: 1 +false: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB) + +Process took 0h:00m:02s realtime, 0h:00m:01s cputime +# Fri Jan 13 00:54:42 2017 + +###########################################################] + +

+ +#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016 +#install: C:\lscc\diamond\3.8_x64\synpbase +#OS: Windows 8 6.2 +#Hostname: DESKTOP-1AUKF7V + +# Sun Jan 08 00:49:32 2017 + +#Implementation: impl1 + +Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +@N:CD720 : std.vhd(123) | Setting time resolution to ns +@N: : DisplayDriverWrapper.vhd(15) | Top entity is set to DisplayDriverWrapper. +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling +VHDL syntax check successful! +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling +@N:CD630 : DisplayDriverWrapper.vhd(15) | Synthesizing work.displaydriverwrapper.arch. +@W:CD638 : DisplayDriverWrapper.vhd(38) | Signal empty is undriven. Either assign the signal a value or remove the signal declaration. +@N:CD630 : DisplayDriverwDecoder_Top.vhd(16) | Synthesizing work.displaydriverwdecoder_top.arch. +Post processing for work.displaydriverwdecoder_top.arch +@W:CL240 : DisplayDriverwDecoder_Top.vhd(38) | disp_data is not assigned a value (floating) -- simulation mismatch possible. +Post processing for work.displaydriverwrapper.arch +@N:CL159 : DisplayDriverWrapper.vhd(20) | Input button is unused. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jan 08 00:49:32 2017 + +###########################################################] +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jan 08 00:49:32 2017 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jan 08 00:49:32 2017 + +###########################################################] +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N: : | Running in 64-bit mode +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level +@N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jan 08 00:49:34 2017 + +###########################################################] +Pre-mapping Report + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version L-2016.03L-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@A:MF827 : | No constraint file specified. +Linked File: impl1_scck.rpt +Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file +@N:MF248 : | Running in 64-bit mode. +@N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + + +Clock Summary +***************** + +Start Requested Requested Clock Clock Clock +Clock Frequency Period Type Group Load +----------------------------------------------------------------------------------------------------- +DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8 +===================================================================================================== + +@W:MT529 : displaydriverwdecoder_top.vhd(75) | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Jan 08 00:49:34 2017 + +###########################################################] +Map & Optimize Report + +Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version L-2016.03L-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@N:MF248 : | Running in 64-bit mode. +@N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Available hyper_sources - for debug and ip models + None Found + +@N:MT206 : | Auto Constrain mode is enabled + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +@N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================== Non-Gated/Non-Generated Clocks =============================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------------- +ClockId0001 clk port 8 DDwD_Top.ascii_reg[6] +============================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB) + +Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) + +Writing EDIF Netlist and constraint files +@N:FX1056 : | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi +L-2016.03L-1 +@N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + +@W:MT420 : | Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Sun Jan 08 00:49:36 2017 +# + + +Top view: DisplayDriverWrapper +Requested Frequency: 1297.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): +@N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: -0.136 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------ +DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0 +==================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------- +DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.771 -0.136 | No paths - | No paths - | No paths - +=========================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: DisplayDriverWrapper|clk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.853 -0.136 +DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.853 -0.136 +DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.853 -0.136 +DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.853 -0.136 +DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.853 -0.136 +DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.853 -0.136 +DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.853 -0.136 +DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.853 -0.136 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.717 -0.136 +DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.717 -0.136 +DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.717 -0.136 +DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.717 -0.136 +DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.717 -0.136 +DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.717 -0.136 +DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.717 -0.136 +DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.717 -0.136 +=============================================================================================================== + + + +Worst Path Information +View Worst Path in Analyst +*********************** + + +Path information for path number 1: + Requested Period: 0.771 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.717 + + - Propagation time: 0.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.136 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[0] / Q + Ending point: DDwD_Top.ascii_reg[0] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.853 0.853 - +ascii_reg[0] Net - - - - 1 +DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.853 - +======================================================================================= + + +Path information for path number 2: + Requested Period: 0.771 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.717 + + - Propagation time: 0.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.136 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[1] / Q + Ending point: DDwD_Top.ascii_reg[1] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.853 0.853 - +ascii_reg[1] Net - - - - 1 +DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.853 - +======================================================================================= + + +Path information for path number 3: + Requested Period: 0.771 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.717 + + - Propagation time: 0.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.136 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[2] / Q + Ending point: DDwD_Top.ascii_reg[2] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.853 0.853 - +ascii_reg[2] Net - - - - 1 +DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.853 - +======================================================================================= + + +Path information for path number 4: + Requested Period: 0.771 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.717 + + - Propagation time: 0.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.136 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[3] / Q + Ending point: DDwD_Top.ascii_reg[3] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.853 0.853 - +ascii_reg[3] Net - - - - 1 +DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.853 - +======================================================================================= + + +Path information for path number 5: + Requested Period: 0.771 + - Setup time: 0.054 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.717 + + - Propagation time: 0.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.136 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[4] / Q + Ending point: DDwD_Top.ascii_reg[4] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.853 0.853 - +ascii_reg[4] Net - - - - 1 +DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.853 - +======================================================================================= + + + +##### END OF TIMING REPORT #####] + +Constraints that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5u_45f-6 + +Register bits: 8 of 43848 (0%) +PIC Latch: 0 +I/O cells: 17 + + +Details: +FD1S3IX: 5 +FD1S3JX: 3 +GSR: 1 +IB: 2 +OB: 15 +PUR: 1 +VHI: 2 +VLO: 1 +false: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Jan 08 00:49:36 2017 + +###########################################################] + +

Project Settings

Project Name

proj_1

Implementation Name

impl1

Top Module

DisplayDriverWrapper

Pipelining

Retiming

Resource Sharing

Fanout Guide

1000

Disable I/O Insertion

Disable Sequential Optimizations

Clock Conversion

Run Status

Job Name

Status

CPU Time

Real Time

Memory

Date/Time

(compiler)

Complete

0m:00s

13-Jan-17
00:54:37

(premap)

Complete

0m:00s

141MB

13-Jan-17
00:54:39

(fpga_mapper)

Complete

0m:01s

0m:02s

144MB

13-Jan-17
00:54:42

Multi-srs Generator

Complete

0m:01s

13-Jan-17
00:54:39

Area Summary

I/O cells

Block RAMs +(v_ram)

DSPs +(dsp_used)

ORCA LUTs +(total_luts)

Timing Summary

Clock Name

Req Freq

Est Freq

Slack

DisplayDriverWrapper|clk

1220.4 MHz

1037.3 MHz

-0.145

Optimizations Summary

Combined Clock Conversion

1 / 0

Lattice Synthesis Timing Report +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Sun Jan 08 00:20:00 2017 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: DisplayDriverWrapper +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +-------------------------------------------------------------------------------- + + +All constraints were met. + + + +Timing summary: +--------------- + +Timing errors: 0 Score: 0 + +Constraints cover 0 paths, 0 nets, and 0 connections (0.0% coverage) + + +Peak memory: 104431616 bytes, TRCE: 49152 bytes, DLYMAN: 0 bytes +CPU_TIME_REPORT: 0 secs + + + +
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BITGEN: Bitstream Generator Diamond (64-bit) 3.8.0.115.3 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + +Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.sec -k C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.bek -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1.ncd DisplayDriverwDecoder_impl1.prf + +Loading design for application Bitgen from file DisplayDriverwDecoder_impl1.ncd. +Design name: DisplayDriverWrapper +NCD version: 3.3 +Vendor: LATTICE +Device: LFE5UM5G-45F +Package: CABGA381 +Performance: 8 +Loading device for application Bitgen from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga. +Package Status: Final Version 1.36. +Performance Hardware Data Status: Final Version 50.1. + +Running DRC. +WARNING - netcheck: Design is completely unrouted. 0 warnings not reported below. +DRC detected 0 errors and 1 warnings. +Reading Preference File from DisplayDriverwDecoder_impl1.prf. + + +Preference Summary: + ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| CfgMode | Disable** | ++---------------------------------+---------------------------------+ +| DONE_EX | OFF** | ++---------------------------------+---------------------------------+ +| DONE_OD | ON** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.4** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| CONFIG_MODE | JTAG** | ++---------------------------------+---------------------------------+ +| WAKE_UP | 21** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | OFF** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ +| DisableUES | FALSE** | ++---------------------------------+---------------------------------+ +| SLAVE_PARALLEL_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| DONE_PULL | ON** | ++---------------------------------+---------------------------------+ +| CONFIG_IOVOLTAGE | 2.5** | ++---------------------------------+---------------------------------+ +| TRANSFR | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 10.23. + +Saving bit stream in "DisplayDriverwDecoder_impl1.bit". + + + +
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+ Lattice Mapping Report File for Design Module 'DisplayDriverWrapper' + + + +Design Information + +Command line: map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial + DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr + DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C: + /Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B + uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single + -14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv + erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w- + decoder/Project/Lattice_FPGA_Build/promote.xml +Target Vendor: LATTICE +Target Device: LFE5UM5G-45FCABGA381 +Target Performance: 8 +Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3 +Mapped on: 01/13/17 00:54:48 + + +Design Summary + Number of registers: 0 out of 44457 (0%) + PFU registers: 0 out of 43848 (0%) + PIO registers: 0 out of 609 (0%) + Number of SLICEs: 0 out of 21924 (0%) + SLICEs as Logic/ROM: 0 out of 21924 (0%) + SLICEs as RAM: 0 out of 16443 (0%) + SLICEs as Carry: 0 out of 21924 (0%) + Number of LUT4s: 0 out of 43848 (0%) + Number used as logic LUTs: 0 + Number used as distributed RAM: 0 + Number used as ripple logic: 0 + Number used as shift registers: 0 + Number of PIO sites used: 16 out of 203 (8%) + Number of block RAMs: 0 out of 108 (0%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + DTR used : No + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%) + Number of DCC: 0 out of 60 (0%) + Number of DCS: 0 out of 2 (0%) + Number of PLLs: 0 out of 4 (0%) + Number of DDRDLLs: 0 out of 4 (0%) + Number of CLKDIV: 0 out of 4 (0%) + Number of ECLKSYNC: 0 out of 10 (0%) + Number of ECLKBRIDGECS: 0 out of 2 (0%) + Number of DCUs: 0 out of 2 (0%) + Number of DCU Channels: 0 out of 4 (0%) + Number of EXTREFs: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + + + Number Of Mapped DSP Components: + -------------------------------- + MULT18X18D 0 + MULT9X9D 0 + ALU54B 0 + ALU24B 0 + PRADD18A 0 + PRADD9A 0 + -------------------------------- + Number of Used DSP MULT Sites: 0 out of 144 (0 %) + Number of Used DSP ALU Sites: 0 out of 72 (0 %) + Number of Used DSP PRADD Sites: 0 out of 144 (0 %) + Number of clocks: 0 + Number of Clock Enables: 0 + Number of LSRs: 0 + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + + + + + Number of warnings: 1 + Number of errors: 0 + + + + + +Design Errors/Warnings + +WARNING - map: IO buffer missing for top level port button...logic will be + discarded. + + + +IO (PIO) Attributes + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| disp_data[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_sel | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[14] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[13] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[12] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[11] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[10] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[9] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[8] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + +| disp_data[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| disp_data[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + + +Removed logic + +Block GSR_INST undriven or does not drive anything - clipped. +Block rst_pad undriven or does not drive anything - clipped. +Block DDwD_Top/VCC undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped. +Block DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped. +Block clk_pad undriven or does not drive anything - clipped. +Signal GND undriven or does not drive anything - clipped. +Signal VCC undriven or does not drive anything - clipped. +Signal rst undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped. +Signal rst_c undriven or does not drive anything - clipped. +Signal DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped. +Signal clk_c undriven or does not drive anything - clipped. +Signal clk undriven or does not drive anything - clipped. +Block GND was optimized away. +Block VCC was optimized away. + + + +Memory Usage + + + + + + + + + + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 60 MB + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights + reserved. + + + +
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PAD Specification File +*************************** + +PART TYPE: LFE5UM5G-45F +Performance Grade: 8 +PACKAGE: CABGA381 +Package Status: Final Version 1.36 + +Fri Jan 13 00:54:59 2017 + +Pinout by Port Name: ++---------------+----------+--------------+-------+-----------+-------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties | ++---------------+----------+--------------+-------+-----------+-------------------------------+ +| disp_data[0] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[10] | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[11] | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[12] | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[13] | R16/3 | LVCMOS25_OUT | PR44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[14] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[1] | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[2] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[3] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[4] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[5] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[6] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[7] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[8] | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_data[9] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | +| disp_sel | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | ++---------------+----------+--------------+-------+-----------+-------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 3 | 2.5V | +| 6 | 2.5V | +| 8 | 2.5V | ++------+-------+ + + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+--------------+--------------+--------------------------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | BC Enable | ++----------+-----------------------+------------+--------------+--------------+--------------------------+-----------+ +| A2/7 | unused, PULL:DOWN | | | PL23A | LDQ29 | | +| A3/7 | unused, PULL:DOWN | | | PL14C | LDQ17 | | +| A4/7 | unused, PULL:DOWN | | | PL11A | ULC_GPLL0T_IN/LDQ17 | | +| A5/7 | unused, PULL:DOWN | | | PL11B | ULC_GPLL0C_IN/LDQ17 | | +| A6/0 | unused, PULL:DOWN | | | PT4A | ULC_GPLL1T_IN | | +| A7/0 | unused, PULL:DOWN | | | PT18A | | | +| A8/0 | unused, PULL:DOWN | | | PT18B | | | +| A9/0 | unused, PULL:DOWN | | | PT33A | GR_PCLK0_1 | | +| A10/0 | unused, PULL:DOWN | | | PT36A | PCLKT0_1 | | +| A11/0 | unused, PULL:DOWN | | | PT36B | | | +| A12/1 | unused, PULL:DOWN | | | PT49A | | | +| A13/1 | unused, PULL:DOWN | | | PT49B | | | +| A14/1 | unused, PULL:DOWN | | | PT56A | | | +| A15/1 | unused, PULL:DOWN | | | PT67A | | | +| A16/1 | unused, PULL:DOWN | | | PT74A | | | +| A17/1 | unused, PULL:DOWN | | | PT80A | | | +| A18/1 | unused, PULL:DOWN | | | PT83A | | | +| A19/1 | unused, PULL:DOWN | | | PT85A | URC_GPLL1T_IN | | +| B1/7 | unused, PULL:DOWN | | | PL23B | LDQ29 | | +| B2/7 | unused, PULL:DOWN | | | PL23C | VREF1_7/LDQ29 | | +| B3/7 | unused, PULL:DOWN | | | PL14D | LDQ17 | | +| B4/7 | unused, PULL:DOWN | | | PL14B | LDQ17 | | +| B5/7 | unused, PULL:DOWN | | | PL11C | LDQ17 | | +| B6/0 | unused, PULL:DOWN | | | PT4B | ULC_GPLL1C_IN | | +| B8/0 | unused, PULL:DOWN | | | PT15B | | | +| B9/0 | unused, PULL:DOWN | | | PT31A | | | +| B10/0 | unused, PULL:DOWN | | | PT33B | GR_PCLK0_0 | | +| B11/0 | unused, PULL:DOWN | | | PT38A | PCLKT0_0 | | +| B12/1 | unused, PULL:DOWN | | | PT44A | PCLKT1_0 | | +| B13/1 | unused, PULL:DOWN | | | PT51A | | | +| B15/1 | unused, PULL:DOWN | | | PT69A | | | +| B16/1 | unused, PULL:DOWN | | | PT74B | | | +| B17/1 | unused, PULL:DOWN | | | PT78A | | | +| B18/1 | unused, PULL:DOWN | | | PT80B | | | +| B19/1 | unused, PULL:DOWN | | | PT83B | | | +| B20/1 | unused, PULL:DOWN | | | PT85B | URC_GPLL1C_IN | | +| C1/7 | unused, PULL:DOWN | | | PL26A | LDQ29 | | +| C2/7 | unused, PULL:DOWN | | | PL23D | LDQ29 | | +| C3/7 | unused, PULL:DOWN | | | PL17C | LDQ17 | | +| C4/7 | unused, PULL:DOWN | | | PL14A | LDQ17 | | +| C5/7 | unused, PULL:DOWN | | | PL11D | LDQ17 | | +| C6/0 | unused, PULL:DOWN | | | PT11A | | | +| C7/0 | unused, PULL:DOWN | | | PT11B | | | +| C8/0 | unused, PULL:DOWN | | | PT15A | | | +| C9/0 | unused, PULL:DOWN | | | PT27A | | | +| C10/0 | unused, PULL:DOWN | | | PT31B | | | +| C11/0 | unused, PULL:DOWN | | | PT38B | | | +| C12/1 | unused, PULL:DOWN | | | PT44B | | | +| C13/1 | unused, PULL:DOWN | | | PT51B | | | +| C14/1 | unused, PULL:DOWN | | | PT56B | | | +| C15/1 | unused, PULL:DOWN | | | PT69B | | | +| C16/1 | unused, PULL:DOWN | | | PT76A | | | +| C17/1 | unused, PULL:DOWN | | | PT78B | | | +| C18/2 | unused, PULL:DOWN | | | PR11A | URC_GPLL0T_IN/RDQ17 | | +| C20/2 | unused, PULL:DOWN | | | PR23A | RDQ29 | | +| CCLK/8 | | | | CCLK | MCLK/SCK | | +| D1/7 | unused, PULL:DOWN | | | PL26B | LDQ29 | | +| D2/7 | unused, PULL:DOWN | | | PL26C | LDQ29 | | +| D3/7 | unused, PULL:DOWN | | | PL17D | LDQ17 | | +| D5/7 | unused, PULL:DOWN | | | PL17B | LDQSN17 | | +| D6/0 | unused, PULL:DOWN | | | PT6B | | | +| D7/0 | unused, PULL:DOWN | | | PT9B | | | +| D8/0 | unused, PULL:DOWN | | | PT13B | | | +| D9/0 | unused, PULL:DOWN | | | PT20A | | | +| D10/0 | unused, PULL:DOWN | | | PT29A | | | +| D11/1 | unused, PULL:DOWN | | | PT42A | PCLKT1_1 | | +| D12/1 | unused, PULL:DOWN | | | PT47A | GR_PCLK1_0 | | +| D13/1 | unused, PULL:DOWN | | | PT53A | | | +| D14/1 | unused, PULL:DOWN | | | PT58A | | | +| D15/1 | unused, PULL:DOWN | | | PT71A | | | +| D16/1 | unused, PULL:DOWN | | | PT76B | | | +| D17/2 | unused, PULL:DOWN | | | PR11B | URC_GPLL0C_IN/RDQ17 | | +| D18/2 | unused, PULL:DOWN | | | PR14A | RDQ17 | | +| D19/2 | unused, PULL:DOWN | | | PR23B | RDQ29 | | +| D20/2 | unused, PULL:DOWN | | | PR23C | VREF1_2/RDQ29 | | +| E1/7 | unused, PULL:DOWN | | | PL26D | LDQ29 | | +| E2/7 | unused, PULL:DOWN | | | PL32D | PCLKC7_0/LDQ29 | | +| E3/7 | unused, PULL:DOWN | | | PL20B | LDQ17 | | +| E4/7 | unused, PULL:DOWN | | | PL17A | LDQS17 | | +| E5/7 | unused, PULL:DOWN | | | PL20C | LDQ17 | | +| E6/0 | unused, PULL:DOWN | | | PT6A | | | +| E7/0 | unused, PULL:DOWN | | | PT9A | | | +| E8/0 | unused, PULL:DOWN | | | PT13A | | | +| E9/0 | unused, PULL:DOWN | | | PT20B | | | +| E10/0 | unused, PULL:DOWN | | | PT29B | | | +| E11/1 | unused, PULL:DOWN | | | PT42B | | | +| E12/1 | unused, PULL:DOWN | | | PT47B | GR_PCLK1_1 | | +| E13/1 | unused, PULL:DOWN | | | PT53B | | | +| E14/1 | unused, PULL:DOWN | | | PT58B | | | +| E15/1 | unused, PULL:DOWN | | | PT71B | | | +| E16/2 | unused, PULL:DOWN | | | PR11C | RDQ17 | | +| E17/2 | unused, PULL:DOWN | | | PR14B | RDQ17 | | +| E18/2 | unused, PULL:DOWN | | | PR14C | RDQ17 | | +| E19/2 | unused, PULL:DOWN | | | PR23D | RDQ29 | | +| E20/2 | unused, PULL:DOWN | | | PR26A | RDQ29 | | +| F1/6 | unused, PULL:DOWN | | | PL35B | PCLKC6_1/LDQ41 | | +| F2/7 | unused, PULL:DOWN | | | PL32C | PCLKT7_0/LDQ29 | | +| F3/7 | unused, PULL:DOWN | | | PL32B | PCLKC7_1/LDQ29 | | +| F4/7 | unused, PULL:DOWN | | | PL20A | LDQ17 | | +| F5/7 | unused, PULL:DOWN | | | PL20D | LDQ17 | | +| F16/2 | unused, PULL:DOWN | | | PR11D | RDQ17 | | +| F17/2 | unused, PULL:DOWN | | | PR17A | RDQS17 | | +| F18/2 | unused, PULL:DOWN | | | PR14D | RDQ17 | | +| F19/2 | unused, PULL:DOWN | | | PR26B | RDQ29 | | +| F20/2 | unused, PULL:DOWN | | | PR26C | RDQ29 | | +| G1/6 | unused, PULL:DOWN | | | PL35D | PCLKC6_0/LDQ41 | | +| G2/6 | unused, PULL:DOWN | | | PL35A | PCLKT6_1/LDQ41 | | +| G3/7 | unused, PULL:DOWN | | | PL32A | PCLKT7_1/LDQ29 | | +| G5/7 | unused, PULL:DOWN | | | PL29B | LDQSN29 | | +| G16/2 | unused, PULL:DOWN | | | PR17C | RDQ17 | | +| G18/2 | unused, PULL:DOWN | | | PR17B | RDQSN17 | | +| G19/2 | unused, PULL:DOWN | | | PR29A | GR_PCLK2_1/RDQS29 | | +| G20/2 | unused, PULL:DOWN | | | PR26D | RDQ29 | | +| H1/6 | unused, PULL:DOWN | | | PL41C | LDQ41 | | +| H2/6 | unused, PULL:DOWN | | | PL35C | PCLKT6_0/LDQ41 | | +| H3/7 | unused, PULL:DOWN | | | PL29D | LDQ29 | | +| H4/7 | unused, PULL:DOWN | | | PL29A | GR_PCLK7_1/LDQS29 | | +| H5/7 | unused, PULL:DOWN | | | PL29C | GR_PCLK7_0/LDQ29 | | +| H16/2 | unused, PULL:DOWN | | | PR17D | RDQ17 | | +| H17/2 | unused, PULL:DOWN | | | PR20B | RDQ17 | | +| H18/2 | unused, PULL:DOWN | | | PR20A | RDQ17 | | +| H20/2 | unused, PULL:DOWN | | | PR29B | RDQSN29 | | +| J1/6 | disp_sel | LOCATED | LVCMOS25_OUT | PL41B | LDQSN41 | | +| J3/6 | unused, PULL:DOWN | | | PL38C | GR_PCLK6_1/LDQ41 | | +| J4/6 | unused, PULL:DOWN | | | PL38A | GR_PCLK6_0/LDQ41 | | +| J5/6 | unused, PULL:DOWN | | | PL38B | LDQ41 | | +| J16/2 | unused, PULL:DOWN | | | PR20D | RDQ17 | | +| J17/2 | unused, PULL:DOWN | | | PR20C | RDQ17 | | +| J18/2 | unused, PULL:DOWN | | | PR29C | GR_PCLK2_0/RDQ29 | | +| J19/2 | unused, PULL:DOWN | | | PR32A | PCLKT2_1/RDQ29 | | +| J20/2 | unused, PULL:DOWN | | | PR32C | PCLKT2_0/RDQ29 | | +| K1/6 | unused, PULL:DOWN | | | PL41D | LDQ41 | | +| K2/6 | unused, PULL:DOWN | | | PL41A | LDQS41 | | +| K3/6 | unused, PULL:DOWN | | | PL38D | LDQ41 | | +| K4/6 | unused, PULL:DOWN | | | PL44A | LDQ41 | | +| K5/6 | unused, PULL:DOWN | | | PL44B | VREF1_6/LDQ41 | | +| K18/2 | unused, PULL:DOWN | | | PR29D | RDQ29 | | +| K19/2 | unused, PULL:DOWN | | | PR32B | PCLKC2_1/RDQ29 | | +| K20/2 | unused, PULL:DOWN | | | PR32D | PCLKC2_0/RDQ29 | | +| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | | +| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | | +| L3/6 | unused, PULL:DOWN | | | PL62C | LDQ65 | | +| L4/6 | unused, PULL:DOWN | | | PL44C | LDQ41 | | +| L5/6 | unused, PULL:DOWN | | | PL44D | LDQ41 | | +| L16/3 | disp_data[3] | LOCATED | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | | +| L17/3 | disp_data[4] | LOCATED | LVCMOS25_OUT | PR38B | RDQ41 | | +| L18/3 | disp_data[1] | LOCATED | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | | +| L19/3 | unused, PULL:DOWN | | | PR35C | PCLKT3_0/RDQ41 | | +| L20/3 | unused, PULL:DOWN | | | PR35A | PCLKT3_1/RDQ41 | | +| M1/6 | unused, PULL:DOWN | | | PL65B | LDQSN65 | | +| M3/6 | unused, PULL:DOWN | | | PL62B | LDQ65 | | +| M4/6 | unused, PULL:DOWN | | | PL59A | LDQ65 | | +| M5/6 | unused, PULL:DOWN | | | PL53A | LDQS53 | | +| M17/3 | disp_data[9] | LOCATED | LVCMOS25_OUT | PR41B | RDQSN41 | | +| M18/3 | disp_data[5] | LOCATED | LVCMOS25_OUT | PR38D | RDQ41 | | +| M19/3 | disp_data[2] | LOCATED | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | | +| M20/3 | disp_data[0] | LOCATED | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | | +| N1/6 | unused, PULL:DOWN | | | PL65D | LDQ65 | | +| N2/6 | unused, PULL:DOWN | | | PL65A | LDQS65 | | +| N3/6 | unused, PULL:DOWN | | | PL62A | LDQ65 | | +| N4/6 | unused, PULL:DOWN | | | PL59C | LDQ65 | | +| N5/6 | unused, PULL:DOWN | | | PL59B | LDQ65 | | +| N16/3 | disp_data[8] | LOCATED | LVCMOS25_OUT | PR41A | RDQS41 | | +| N17/3 | disp_data[11] | LOCATED | LVCMOS25_OUT | PR44A | RDQ41 | | +| N18/3 | disp_data[10] | LOCATED | LVCMOS25_OUT | PR41C | RDQ41 | | +| N19/3 | unused, PULL:DOWN | | | PR59A | RDQ65 | | +| N20/3 | unused, PULL:DOWN | | | PR59B | RDQ65 | | +| P1/6 | unused, PULL:DOWN | | | PL68A | LDQ65 | | +| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | | +| P3/6 | unused, PULL:DOWN | | | PL68C | LLC_GPLL0T_IN/LDQ65 | | +| P4/6 | unused, PULL:DOWN | | | PL68D | LLC_GPLL0C_IN/LDQ65 | | +| P5/6 | unused, PULL:DOWN | | | PL59D | LDQ65 | | +| P16/3 | disp_data[12] | LOCATED | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | | +| P17/3 | disp_data[7] | LOCATED | LVCMOS25_OUT | PR41D | RDQ41 | | +| P18/3 | unused, PULL:DOWN | | | PR59D | RDQ65 | | +| P19/3 | unused, PULL:DOWN | | | PR59C | RDQ65 | | +| P20/3 | unused, PULL:DOWN | | | PR62A | RDQ65 | | +| PL47A/6 | unused, PULL:DOWN | | | PL47A | LDQ53 | | +| PL47B/6 | unused, PULL:DOWN | | | PL47B | LDQ53 | | +| PL47C/6 | unused, PULL:DOWN | | | PL47C | LDQ53 | | +| PL47D/6 | unused, PULL:DOWN | | | PL47D | LDQ53 | | +| PL50A/6 | unused, PULL:DOWN | | | PL50A | LDQ53 | | +| PL50B/6 | unused, PULL:DOWN | | | PL50B | LDQ53 | | +| PL50C/6 | unused, PULL:DOWN | | | PL50C | LDQ53 | | +| PL50D/6 | unused, PULL:DOWN | | | PL50D | LDQ53 | | +| PL53B/6 | unused, PULL:DOWN | | | PL53B | LDQSN53 | | +| PL53C/6 | unused, PULL:DOWN | | | PL53C | LDQ53 | | +| PL53D/6 | unused, PULL:DOWN | | | PL53D | LDQ53 | | +| PL56A/6 | unused, PULL:DOWN | | | PL56A | LDQ53 | | +| PL56B/6 | unused, PULL:DOWN | | | PL56B | LDQ53 | | +| PL56C/6 | unused, PULL:DOWN | | | PL56C | LDQ53 | | +| PL56D/6 | unused, PULL:DOWN | | | PL56D | LDQ53 | | +| PR47A/3 | unused, PULL:DOWN | | | PR47A | RDQ53 | | +| PR47B/3 | unused, PULL:DOWN | | | PR47B | RDQ53 | | +| PR47C/3 | unused, PULL:DOWN | | | PR47C | RDQ53 | | +| PR47D/3 | unused, PULL:DOWN | | | PR47D | RDQ53 | | +| PR50A/3 | unused, PULL:DOWN | | | PR50A | RDQ53 | | +| PR50B/3 | unused, PULL:DOWN | | | PR50B | RDQ53 | | +| PR50C/3 | unused, PULL:DOWN | | | PR50C | RDQ53 | | +| PR50D/3 | unused, PULL:DOWN | | | PR50D | RDQ53 | | +| PR53B/3 | unused, PULL:DOWN | | | PR53B | RDQSN53 | | +| PR53C/3 | unused, PULL:DOWN | | | PR53C | RDQ53 | | +| PR53D/3 | unused, PULL:DOWN | | | PR53D | RDQ53 | | +| PR56A/3 | unused, PULL:DOWN | | | PR56A | RDQ53 | | +| PR56B/3 | unused, PULL:DOWN | | | PR56B | RDQ53 | | +| PR56C/3 | unused, PULL:DOWN | | | PR56C | RDQ53 | | +| PR56D/3 | unused, PULL:DOWN | | | PR56D | RDQ53 | | +| PT22A/0 | unused, PULL:DOWN | | | PT22A | | | +| PT22B/0 | unused, PULL:DOWN | | | PT22B | | | +| PT24A/0 | unused, PULL:DOWN | | | PT24A | | | +| PT24B/0 | unused, PULL:DOWN | | | PT24B | | | +| PT27B/0 | unused, PULL:DOWN | | | PT27B | | | +| PT60A/1 | unused, PULL:DOWN | | | PT60A | | | +| PT60B/1 | unused, PULL:DOWN | | | PT60B | | | +| PT62A/1 | unused, PULL:DOWN | | | PT62A | | | +| PT62B/1 | unused, PULL:DOWN | | | PT62B | | | +| PT65A/1 | unused, PULL:DOWN | | | PT65A | | | +| PT65B/1 | unused, PULL:DOWN | | | PT65B | | | +| PT67B/1 | unused, PULL:DOWN | | | PT67B | | | +| R1/8 | unused, PULL:DOWN | | | PB4A | D7/IO7 | | +| R2/8 | unused, PULL:DOWN | | | PB15A | HOLDN/DI/BUSY/CSSPIN/CEN | | +| R3/8 | unused, PULL:DOWN | | | PB15B | DOUT/CSON | | +| R16/3 | disp_data[13] | LOCATED | LVCMOS25_OUT | PR44C | RDQ41 | | +| R17/3 | disp_data[6] | LOCATED | LVCMOS25_OUT | PR44D | RDQ41 | | +| R18/3 | unused, PULL:DOWN | | | PR65B | RDQSN65 | | +| R20/3 | unused, PULL:DOWN | | | PR62B | RDQ65 | | +| T1/8 | unused, PULL:DOWN | | | PB4B | D6/IO6 | | +| T2/8 | unused, PULL:DOWN | | | PB13A | SN/CSN | | +| T3/8 | unused, PULL:DOWN | | | PB18A | WRITEN | | +| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | | +| T17/3 | unused, PULL:DOWN | | | PR68D | LRC_GPLL0C_IN/RDQ65 | | +| T18/3 | unused, PULL:DOWN | | | PR65D | RDQ65 | | +| T19/3 | unused, PULL:DOWN | | | PR65A | RDQS65 | | +| T20/3 | unused, PULL:DOWN | | | PR62C | RDQ65 | | +| TCK/40 | | | | TCK | | | +| TDI/40 | | | | TDI | | | +| TDO/40 | | | | TDO | | | +| TMS/40 | | | | TMS | | | +| U1/8 | disp_data[14] | LOCATED | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | | +| U2/8 | unused, PULL:DOWN | | | PB13B | CS1N | | +| U16/3 | unused, PULL:DOWN | | | PR68C | LRC_GPLL0T_IN/RDQ65 | | +| U17/3 | unused, PULL:DOWN | | | PR68B | RDQ65 | | +| U18/3 | unused, PULL:DOWN | | | PR68A | RDQ65 | | +| U19/3 | unused, PULL:DOWN | | | PR65C | RDQ65 | | +| U20/3 | unused, PULL:DOWN | | | PR62D | RDQ65 | | +| V1/8 | unused, PULL:DOWN | | | PB6B | D4/MOSI2/IO4 | | +| V2/8 | unused, PULL:DOWN | | | PB11A | D1/MISO/IO1 | | +| W1/8 | unused, PULL:DOWN | | | PB9A | D3/IO3 | | +| W2/8 | unused, PULL:DOWN | | | PB11B | D0/MOSI/IO0 | | +| W4/50 | | | | HDTXP0_D0CH0 | | | +| W5/50 | | | | HDTXN0_D0CH0 | | | +| W8/50 | | | | HDTXP0_D0CH1 | | | +| W9/50 | | | | HDTXN0_D0CH1 | | | +| W13/51 | | | | HDTXP0_D1CH0 | | | +| W14/51 | | | | HDTXN0_D1CH0 | | | +| W17/51 | | | | HDTXP0_D1CH1 | | | +| W18/51 | | | | HDTXN0_D1CH1 | | | +| W20/51 | | | | REFCLKN_D1 | | | +| Y2/8 | unused, PULL:DOWN | | | PB9B | D2/IO2 | | +| Y5/50 | | | | HDRXP0_D0CH0 | | | +| Y6/50 | | | | HDRXN0_D0CH0 | | | +| Y7/50 | | | | HDRXP0_D0CH1 | | | +| Y8/50 | | | | HDRXN0_D0CH1 | | | +| Y11/50 | | | | REFCLKP_D0 | | | +| Y12/50 | | | | REFCLKN_D0 | | | +| Y14/51 | | | | HDRXP0_D1CH0 | | | +| Y15/51 | | | | HDRXN0_D1CH0 | | | +| Y16/51 | | | | HDRXP0_D1CH1 | | | +| Y17/51 | | | | HDRXN0_D1CH1 | | | +| Y19/51 | | | | REFCLKP_D1 | | | ++----------+-----------------------+------------+--------------+--------------+--------------------------+-----------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "disp_data[0]" SITE "M20"; +LOCATE COMP "disp_data[10]" SITE "N18"; +LOCATE COMP "disp_data[11]" SITE "N17"; +LOCATE COMP "disp_data[12]" SITE "P16"; +LOCATE COMP "disp_data[13]" SITE "R16"; +LOCATE COMP "disp_data[14]" SITE "U1"; +LOCATE COMP "disp_data[1]" SITE "L18"; +LOCATE COMP "disp_data[2]" SITE "M19"; +LOCATE COMP "disp_data[3]" SITE "L16"; +LOCATE COMP "disp_data[4]" SITE "L17"; +LOCATE COMP "disp_data[5]" SITE "M18"; +LOCATE COMP "disp_data[6]" SITE "R17"; +LOCATE COMP "disp_data[7]" SITE "P17"; +LOCATE COMP "disp_data[8]" SITE "N16"; +LOCATE COMP "disp_data[9]" SITE "M17"; +LOCATE COMP "disp_sel" SITE "J1"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.8.0.115.3. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. +Fri Jan 13 00:54:59 2017 + + + + +
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PAR: Place And Route Diamond (64-bit) 3.8.0.115.3. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. +Fri Jan 13 00:54:53 2017 + +C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t +DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir +DisplayDriverwDecoder_impl1.prf -gui -msgset +C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml + + +Preference file: DisplayDriverwDecoder_impl1.prf. + +Cost Table Summary +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 - - - - 06 Complete + + +* : Design saved. + +Total (real) run time for 1-seed: 6 secs + +par done! + +Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd" +Fri Jan 13 00:54:53 2017 + + +Best Par Run +PAR: Place And Route Diamond (64-bit) 3.8.0.115.3. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf +Preference file: DisplayDriverwDecoder_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd. +Design name: DisplayDriverWrapper +NCD version: 3.3 +Vendor: LATTICE +Device: LFE5UM5G-45F +Package: CABGA381 +Performance: 8 +Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga. +Package Status: Final Version 1.36. +Performance Hardware Data Status: Final Version 50.1. +License checked out. + + +Ignore Preference Error(s): True + +Device utilization summary: + + PIO (prelim) 16/245 6% used + 16/203 7% bonded + + SLICE 0/21924 0% used + + + +Number of Signals: 0 +Number of Connections: 0 + +Pin Constraint Summary: + 16 out of 16 pins locked (100% locked). + + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. + +Finished Placer Phase 0. REAL time: 5 secs + +Starting Placer Phase 1. + +Placer score = 0. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 0 +Finished Placer Phase 2. REAL time: 5 secs + + + +Clock Report + +Global Clock Resources: + CLK_PIN : 0 out of 12 (0%) + GR_PCLK : 0 out of 12 (0%) + PLL : 0 out of 4 (0%) + DCS : 0 out of 2 (0%) + DCC : 0 out of 60 (0%) + CLKDIV : 0 out of 4 (0%) + +Quadrant TL Clocks: + + PRIMARY : 0 out of 16 (0%) + +Quadrant TR Clocks: + + PRIMARY : 0 out of 16 (0%) + +Quadrant BL Clocks: + + PRIMARY : 0 out of 16 (0%) + +Quadrant BR Clocks: + + PRIMARY : 0 out of 16 (0%) + +Edge Clocks: + + No edge clock selected. + + + + + ++ +I/O Usage Summary (final): + 16 out of 245 (6.5%) PIO sites used. + 16 out of 203 (7.9%) bonded PIO sites used. + Number of PIO comps: 16; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 0 / 27 ( 0%) | - | - | - | +| 1 | 0 / 33 ( 0%) | - | - | - | +| 2 | 0 / 32 ( 0%) | - | - | - | +| 3 | 14 / 33 ( 42%) | 2.5V | - | - | +| 6 | 1 / 33 ( 3%) | 2.5V | - | - | +| 7 | 0 / 32 ( 0%) | - | - | - | +| 8 | 1 / 13 ( 7%) | 2.5V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd. + +INFO - par: The routing stage will be skipped since the design contains no signals and/or connections. +Timing score: 0 + +Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> +PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> +PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> +PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 6 secs + +par done! + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + + + +
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DisplayDriverwDecoder project summary
Module Name:	DisplayDriverwDecoder	Synthesis:	SynplifyPro
Implementation Name:	impl1	Strategy Name:	Strategy1
Last Process:	Bitstream File	State:	Passed
Target Device:	LFE5UM5G-45F-8BG381C	Device Family:	ECP5UM5G
Device Type:	LFE5UM5G-45F	Package Type:	CABGA381
Performance grade:	8	Operating conditions:	COM
Logic preference file:	DisplayDriverwDecoder.lpf
Physical Preference file:	impl1/DisplayDriverwDecoder_impl1.prf
Product Version:	3.8.0.115.3	Patch Version:
Updated:	2017/01/13 00:56:27
Implementation Location:	C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1
Project File:	C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf

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Synthesis Report +#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016 +#install: C:\lscc\diamond\3.8_x64\synpbase +#OS: Windows 8 6.2 +#Hostname: DESKTOP-1AUKF7V + +# Fri Jan 13 00:54:37 2017 + +#Implementation: impl1 + +Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N|Running in 64-bit mode +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N|Running in 64-bit mode +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. + +@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper. +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling +VHDL syntax check successful! +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling +@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch. +@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration. +@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch. +Post processing for work.displaydriverwdecoder_top.arch +Post processing for work.displaydriverwrapper.arch +@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused. + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:37 2017 + +###########################################################] +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N|Running in 64-bit mode +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:37 2017 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:37 2017 + +###########################################################] +Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 +@N|Running in 64-bit mode +File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Fri Jan 13 00:54:39 2017 + +###########################################################] +Pre-mapping Report + +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version L-2016.03L-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@A: MF827 |No constraint file specified. +@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt +Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + + +Clock Summary +***************** + +Start Requested Requested Clock Clock Clock +Clock Frequency Period Type Group Load +----------------------------------------------------------------------------------------------------- +DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8 +===================================================================================================== + +@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri Jan 13 00:54:39 2017 + +###########################################################] +Map & Optimize Report + +Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 +Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. +Product Version L-2016.03L-1 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Available hyper_sources - for debug and ip models + None Found + +@N: MT206 |Auto Constrain mode is enabled + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + + + +@S |Clock Optimization Summary + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +============================== Non-Gated/Non-Generated Clocks =============================== +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------------- +@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6] +============================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB) + +Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi +L-2016.03L-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + +@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk" + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Fri Jan 13 00:54:42 2017 +# + + +Top view: DisplayDriverWrapper +Requested Frequency: 1220.4 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: -0.145 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------------------------ +DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0 +==================================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------------- +DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths - +=========================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: DisplayDriverWrapper|clk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145 +DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145 +DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145 +DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145 +DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145 +DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145 +DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145 +DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145 +============================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145 +DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145 +DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145 +DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145 +DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145 +DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145 +DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145 +DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145 +=============================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[0] / Q + Ending point: DDwD_Top.ascii_reg[0] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 - +ascii_reg[0] Net - - - - 1 +DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 2: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[1] / Q + Ending point: DDwD_Top.ascii_reg[1] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 - +ascii_reg[1] Net - - - - 1 +DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 3: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[2] / Q + Ending point: DDwD_Top.ascii_reg[2] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 - +ascii_reg[2] Net - - - - 1 +DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 4: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[3] / Q + Ending point: DDwD_Top.ascii_reg[3] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 - +ascii_reg[3] Net - - - - 1 +DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 - +======================================================================================= + + +Path information for path number 5: + Requested Period: 0.819 + - Setup time: 0.211 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.608 + + - Propagation time: 0.753 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -0.145 + + Number of logic level(s): 0 + Starting point: DDwD_Top.ascii_reg[4] / Q + Ending point: DDwD_Top.ascii_reg[4] / D + The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 - +ascii_reg[4] Net - - - - 1 +DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 - +======================================================================================= + + + +##### END OF TIMING REPORT #####] + +Constraints that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um5g_45f-8 + +Register bits: 8 of 43848 (0%) +PIC Latch: 0 +I/O cells: 18 + + +Details: +FD1S3IX: 5 +FD1S3JX: 3 +GSR: 1 +IB: 2 +OB: 16 +PUR: 1 +VHI: 2 +VLO: 1 +false: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB) + +Process took 0h:00m:02s realtime, 0h:00m:01s cputime +# Fri Jan 13 00:54:42 2017 + +###########################################################] + + + +
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Map TRACE Report + +Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd. +Design name: DisplayDriverWrapper +NCD version: 3.3 +Vendor: LATTICE +Device: LFE5UM5G-45F +Package: CABGA381 +Performance: 8 +Loading device for application trce from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga. +Package Status: Final Version 1.36. +Performance Hardware Data Status: Final Version 50.1. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3 +Fri Jan 13 00:54:52 2017 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf +Design file: displaydriverwdecoder_impl1_map.ncd +Preference file: displaydriverwdecoder_impl1.prf +Device,speed: LFE5UM5G-45F,8 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Preference Summary + +

Default path enumeration(0 errors)

0 items scored, 0 timing errors detected. + +

Default net enumeration(0 errors)

0 items scored, 0 timing errors detected. + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: Default path enumeration + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: Default net enumeration + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +Default path enumeration | -| -| 0 + | | | +Default net enumeration | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 0 clocks: + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 0 paths, 0 nets, and 0 connections (100.00% coverage) + +-------------------------------------------------------------------------------- + + + + +
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Setting log file to 'C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/hdla_gen_hierarchy.html'. +Starting: parse design source files +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/standard.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package standard +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/std_1164.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164 +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164 +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/mgc_qsim.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/numeric_bit.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/numeric_std.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/textio.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/std_logic_textio.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_attr.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_misc.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc +INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real +INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_arit.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_sign.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_unsi.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/synattr.vhd +INFO - C:/lscc/diamond/3.8_x64/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes +(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.v +(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5um.vhd +(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd +INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(16,8-16,33) (VHDL-1012) analyzing entity displaydriverwdecoder_top +INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(50,14-50,18) (VHDL-1010) analyzing architecture arch +(VHDL-1481) Analyzing VHDL file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd +INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(15,8-15,28) (VHDL-1012) analyzing entity displaydriverwrapper +INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(37,14-37,18) (VHDL-1010) analyzing architecture arch +INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd(15,8-15,28) (VHDL-1067) elaborating DisplayDriverWrapper(arch) +INFO - C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd(16,8-16,33) (VHDL-1067) elaborating DisplayDriverwDecoder_Top_uniq_0(arch) +Done: design load finished with (0) errors, and (0) warnings + +

Synthesis and Ngdbuild Report +synthesis: version Diamond (64-bit) 3.8.0.115.3 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. +Sun Jan 08 00:19:59 2017 + + +Command Line: synthesis -f DisplayDriverwDecoder_impl1_lattice.synproj -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml + +Synthesis options: +The -a option is ECP5U. +The -s option is 6. +The -t option is CABGA381. +The -d option is LFE5U-45F. +Using package CABGA381. +Using performance grade 6. + + +########################################################## + +### Lattice Family : ECP5U + +### Device : LFE5U-45F + +### Package : CABGA381 + +### Speed : 6 + +########################################################## + + + +Optimization goal = Timing +Top-level module name = DisplayDriverWrapper. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data (searchpath added) +-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1 (searchpath added) +-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build (searchpath added) +VHDL library = work +VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd +VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd +NGD file = DisplayDriverwDecoder_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 +Compile design. +Compile Design Begin +INFO - synthesis: The default VHDL library search path is now "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1". VHDL-1504 +Analyzing VHDL file c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd. VHDL-1481 +INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16): analyzing entity displaydriverwdecoder_top. VHDL-1012 +INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50): analyzing architecture arch. VHDL-1010 +unit DisplayDriverWrapper is not yet analyzed. VHDL-1485 +Analyzing VHDL file c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd. VHDL-1481 +INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): analyzing entity displaydriverwrapper. VHDL-1012 +INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(35): analyzing architecture arch. VHDL-1010 +unit DisplayDriverWrapper is not yet analyzed. VHDL-1485 +unit DisplayDriverWrapper is not yet analyzed. VHDL-1485 +c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): executing DisplayDriverWrapper(arch) + +WARNING - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31): replacing existing netlist DisplayDriverWrapper(arch). VHDL-1205 +Top module name (VHDL): DisplayDriverWrapper +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data/sa5plib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'sa5p45.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga. +Package Status: Final Version 1.38. +Top-level module name = DisplayDriverWrapper. +######## Missing driver on net disp_data[13]. Patching with GND. +######## Missing driver on net disp_data[12]. Patching with GND. +######## Missing driver on net disp_data[11]. Patching with GND. +######## Missing driver on net disp_data[10]. Patching with GND. +######## Missing driver on net disp_data[9]. Patching with GND. +######## Missing driver on net disp_data[8]. Patching with GND. +######## Missing driver on net disp_data[7]. Patching with GND. +######## Missing driver on net disp_data[6]. Patching with GND. +######## Missing driver on net disp_data[5]. Patching with GND. +######## Missing driver on net disp_data[4]. Patching with GND. +######## Missing driver on net disp_data[3]. Patching with GND. +######## Missing driver on net disp_data[2]. Patching with GND. +######## Missing driver on net disp_data[1]. Patching with GND. +######## Missing driver on net disp_data[0]. Patching with GND. + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +Applying 1.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in DisplayDriverWrapper_drc.log. +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data/sa5plib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'... +WARNING - synthesis: logical net 'clk' has no load. +WARNING - synthesis: input pad net 'clk' has no legal load. +WARNING - synthesis: logical net 'reset' has no load. +WARNING - synthesis: input pad net 'reset' has no legal load. +WARNING - synthesis: logical net 'button' has no load. +WARNING - synthesis: input pad net 'button' has no legal load. +WARNING - synthesis: DRC complete with 6 warnings. +All blocks are expanded and NGD expansion is successful. +Writing NGD file DisplayDriverwDecoder_impl1.ngd. + +################### Begin Area Report (DisplayDriverWrapper)###################### +Number of register bits => 0 of 44457 (0 % ) +GSR => 1 +OB => 15 +################### End Area Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 0 +Clock Enable Nets +Number of Clock Enables: 0 +Top 0 highest fanout Clock Enables: +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : disp_data[0], loads : 0 + Net : disp_data[1], loads : 0 + Net : disp_data[2], loads : 0 + Net : disp_data[3], loads : 0 + Net : disp_data[4], loads : 0 + Net : disp_data[5], loads : 0 + Net : disp_data[6], loads : 0 + Net : disp_data[7], loads : 0 + Net : disp_data[8], loads : 0 + Net : disp_data[9], loads : 0 +################### End Clock Report ################## + +Peak Memory Usage: 99.668 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 1.156 secs +-------------------------------------------------------------- + + + +
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pn170106141512 +#Start recording tcl command: 1/6/2017 14:08:36 +#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder +prj_project new -name "DisplayDriverwDecoder" -impl "impl1" -dev LFE5U-45F-6BG381C -synthesis "lse" +prj_src add "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd" +prj_project save +prj_project save +prj_run Synthesis -impl impl1 +prj_run Synthesis -impl impl1 +#Stop recording: 1/6/2017 14:15:12 + + + +pn170108153204 +#Start recording tcl command: 1/8/2017 15:04:35 +#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder +prj_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf" +#Stop recording: 1/8/2017 15:32:04 + + + +pn170112233227 +#Start recording tcl command: 1/12/2017 23:29:59 +#Project Location: C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build; Project name: DisplayDriverwDecoder +prj_project open "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.ldf" +#Stop recording: 1/12/2017 23:32:27 + + + +
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Subversion Repositories single-14-segment-display-driver-w-decoder

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