URL
https://opencores.org/ocsvn/soc_maker/soc_maker/trunk
Subversion Repositories soc_maker
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/soc_maker/trunk/doc/class_arch.uml
52,7 → 52,7
UML 1.4 |
</plugin> |
</profile> |
<XMI xmi.version = '1.2' xmlns:UML = 'org.omg.xmi.namespace.UML' timestamp = 'Tue May 20 21:09:11 CEST 2014'> |
<XMI xmi.version = '1.2' xmlns:UML = 'org.omg.xmi.namespace.UML' timestamp = 'Fri Jun 13 19:26:19 CEST 2014'> |
<XMI.header> <XMI.documentation> |
<XMI.exporter>ArgoUML (using Netbeans XMI Writer version 1.0)</XMI.exporter> |
<XMI.exporterVersion>0.34(6) revised on $Date: 2010-01-11 22:20:14 +0100 (Mon, 11 Jan 2010) $ </XMI.exporterVersion> |
1394,6 → 1394,83
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name = 'ConInst' visibility = 'public' isSpecification = 'false' isRoot = 'false' |
isLeaf = 'false' isAbstract = 'false' isActive = 'false'/> |
<UML:Class xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5B' |
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isRoot = 'false' isLeaf = 'false' isAbstract = 'false' isActive = 'false'> |
<UML:GeneralizableElement.generalization> |
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</UML:GeneralizableElement.generalization> |
</UML:Class> |
<UML:Generalization xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5C' |
isSpecification = 'false'> |
<UML:Generalization.child> |
<UML:Class xmi.idref = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5B'/> |
</UML:Generalization.child> |
<UML:Generalization.parent> |
<UML:Class xmi.idref = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B52'/> |
</UML:Generalization.parent> |
</UML:Generalization> |
<UML:Association xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5D' |
name = '' isSpecification = 'false' isRoot = 'false' isLeaf = 'false' isAbstract = 'false'> |
<UML:Association.connection> |
<UML:AssociationEnd xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5E' |
name = '1' visibility = 'public' isSpecification = 'false' isNavigable = 'true' |
ordering = 'unordered' aggregation = 'composite' targetScope = 'instance' |
changeability = 'changeable'> |
<UML:AssociationEnd.participant> |
<UML:Class xmi.idref = '127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000867'/> |
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</UML:AssociationEnd> |
<UML:AssociationEnd xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5F' |
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<UML:AssociationEnd.participant> |
<UML:Class xmi.idref = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B52'/> |
</UML:AssociationEnd.participant> |
</UML:AssociationEnd> |
</UML:Association.connection> |
</UML:Association> |
<UML:Association xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B60' |
name = '' isSpecification = 'false' isRoot = 'false' isLeaf = 'false' isAbstract = 'false'> |
<UML:Association.connection> |
<UML:AssociationEnd xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B61' |
visibility = 'public' isSpecification = 'false' isNavigable = 'true' ordering = 'unordered' |
aggregation = 'composite' targetScope = 'instance' changeability = 'changeable'> |
<UML:AssociationEnd.participant> |
<UML:Class xmi.idref = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B52'/> |
</UML:AssociationEnd.participant> |
</UML:AssociationEnd> |
<UML:AssociationEnd xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B62' |
visibility = 'public' isSpecification = 'false' isNavigable = 'true' ordering = 'unordered' |
aggregation = 'none' targetScope = 'instance' changeability = 'changeable'> |
<UML:AssociationEnd.participant> |
<UML:Class xmi.idref = '127-0-0-1-7fb16bdf:1461af0060b:-8000:000000000000093C'/> |
</UML:AssociationEnd.participant> |
</UML:AssociationEnd> |
</UML:Association.connection> |
</UML:Association> |
<UML:Association xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B63' |
name = '' isSpecification = 'false' isRoot = 'false' isLeaf = 'false' isAbstract = 'false'> |
<UML:Association.connection> |
<UML:AssociationEnd xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B64' |
visibility = 'public' isSpecification = 'false' isNavigable = 'true' ordering = 'unordered' |
aggregation = 'aggregate' targetScope = 'instance' changeability = 'changeable'> |
<UML:AssociationEnd.participant> |
<UML:Class xmi.idref = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B52'/> |
</UML:AssociationEnd.participant> |
</UML:AssociationEnd> |
<UML:AssociationEnd xmi.id = '127-0-0-1--639abe74:1462d254995:-8000:0000000000000B65' |
visibility = 'public' isSpecification = 'false' isNavigable = 'true' ordering = 'unordered' |
aggregation = 'none' targetScope = 'instance' changeability = 'changeable'> |
<UML:AssociationEnd.participant> |
<UML:Class xmi.idref = '127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008B4'/> |
</UML:AssociationEnd.participant> |
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1439,7 → 1516,7
justification="Center" |
>Component</text> |
<group name="Fig0.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[689, 225, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[593, 241, 478, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000866" |
fill="0" |
fillcolor="white" |
1451,9 → 1528,9
</private> |
|
<rectangle name="Fig0.2.0" |
x="689" |
y="225" |
width="64" |
x="593" |
y="241" |
width="478" |
height="0" |
fill="0" |
fillcolor="white" |
1836,7 → 1913,7
justification="Center" |
>SOCDef</text> |
<group name="Fig1.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[593, 673, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[593, 673, 150, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000867" |
fill="0" |
fillcolor="white" |
1850,7 → 1927,7
<rectangle name="Fig1.2.0" |
x="593" |
y="673" |
width="64" |
width="150" |
height="0" |
fill="0" |
fillcolor="white" |
2025,7 → 2102,7
justification="Center" |
>CoreDefinition</text> |
<group name="Fig2.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1001, 673, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1001, 673, 126, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000868" |
fill="0" |
fillcolor="white" |
2039,7 → 2116,7
<rectangle name="Fig2.2.0" |
x="1001" |
y="673" |
width="64" |
width="126" |
height="0" |
fill="0" |
fillcolor="white" |
2163,7 → 2240,7
offset="-10" /> |
</private> |
<path name="Fig3.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
2194,7 → 2271,7
offset="21" /> |
</private> |
<path name="Fig4.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
2244,7 → 2321,7
justification="Center" |
>HDLFile</text> |
<group name="Fig5.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1217, 673, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1217, 673, 128, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008AD" |
fill="0" |
fillcolor="white" |
2258,7 → 2335,7
<rectangle name="Fig5.2.0" |
x="1217" |
y="673" |
width="64" |
width="128" |
height="0" |
fill="0" |
fillcolor="white" |
2348,7 → 2425,7
<text name="Fig5.4.4" |
x="1217" |
y="744" |
width="129" |
width="128" |
height="16" |
fill="0" |
fillcolor="white" |
2449,7 → 2526,7
justification="Center" |
>CoreInst</text> |
<group name="Fig6.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[801, 673, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[801, 673, 134, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008B4" |
fill="0" |
fillcolor="white" |
2463,7 → 2540,7
<rectangle name="Fig6.2.0" |
x="801" |
y="673" |
width="64" |
width="134" |
height="0" |
fill="0" |
fillcolor="white" |
2629,7 → 2706,7
offset="25" /> |
</private> |
<path name="Fig7.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
2679,7 → 2756,7
justification="Center" |
>SParameter</text> |
<group name="Fig8.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1129, 441, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1129, 441, 123, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008BC" |
fill="0" |
fillcolor="white" |
2693,7 → 2770,7
<rectangle name="Fig8.2.0" |
x="1129" |
y="441" |
width="64" |
width="123" |
height="0" |
fill="0" |
fillcolor="white" |
2839,7 → 2916,7
x="1313" |
y="457" |
width="114" |
height="21" |
height="22" |
fill="0" |
fillcolor="white" |
stroke="0" |
2852,7 → 2929,7
justification="Center" |
>SParameterEntry</text> |
<group name="Fig9.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1313, 457, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1313, 457, 114, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008C3" |
fill="0" |
fillcolor="white" |
2866,7 → 2943,7
<rectangle name="Fig9.2.0" |
x="1313" |
y="457" |
width="64" |
width="114" |
height="0" |
fill="0" |
fillcolor="white" |
2876,7 → 2953,7
</group> |
<rectangle name="Fig9.3" |
x="1312" |
y="478" |
y="479" |
width="116" |
height="1" |
fill="1" |
2885,7 → 2962,7
strokecolor="black" |
/> |
<group name="Fig9.4" |
description="org.argouml.uml.diagram.ui.FigAttributesCompartment[1313, 479, 114, 39]" |
description="org.argouml.uml.diagram.ui.FigAttributesCompartment[1313, 480, 114, 39]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008C3" |
fill="0" |
fillcolor="white" |
2897,7 → 2974,7
|
<rectangle name="Fig9.4.0" |
x="1313" |
y="479" |
y="480" |
width="114" |
height="39" |
fill="0" |
2907,7 → 2984,7
/> |
<text name="Fig9.4.1" |
x="1313" |
y="479" |
y="480" |
width="114" |
height="22" |
fill="0" |
2924,7 → 3001,7
</group> |
<rectangle name="Fig9.5" |
x="1312" |
y="518" |
y="519" |
width="116" |
height="1" |
fill="1" |
2933,7 → 3010,7
strokecolor="black" |
/> |
<group name="Fig9.6" |
description="org.argouml.uml.diagram.ui.FigOperationsCompartment[1313, 519, 114, 40]" |
description="org.argouml.uml.diagram.ui.FigOperationsCompartment[1313, 520, 114, 39]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008C3" |
fill="0" |
fillcolor="white" |
2945,9 → 3022,9
|
<rectangle name="Fig9.6.0" |
x="1313" |
y="519" |
y="520" |
width="114" |
height="40" |
height="39" |
fill="0" |
fillcolor="white" |
stroke="0" |
2955,7 → 3032,7
/> |
<text name="Fig9.6.1" |
x="1313" |
y="519" |
y="520" |
width="114" |
height="22" |
fill="0" |
3014,15 → 3091,9
ownerhref="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008C6" |
angle="95.0" |
offset="22" /> |
<argouml:pathitem figname="Fig10.6" |
classname="org.argouml.uml.diagram.ui.PathItemPlacement" |
figclassname="org.argouml.uml.diagram.ui.FigEdgePort" |
ownerhref="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008C4" |
angle="270.0" |
offset="0" /> |
</private> |
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description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3072,7 → 3143,7
justification="Center" |
>Parameter</text> |
<group name="Fig11.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1265, 217, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[1265, 217, 190, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:00000000000008CB" |
fill="0" |
fillcolor="white" |
3086,7 → 3157,7
<rectangle name="Fig11.2.0" |
x="1265" |
y="217" |
width="64" |
width="190" |
height="0" |
fill="0" |
fillcolor="white" |
3290,7 → 3361,7
offset="-10" /> |
</private> |
<path name="Fig12.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3347,7 → 3418,7
offset="5" /> |
</private> |
<path name="Fig13.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3404,7 → 3475,7
offset="21" /> |
</private> |
<path name="Fig14.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3461,7 → 3532,7
offset="17" /> |
</private> |
<path name="Fig15.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3518,7 → 3589,7
offset="25" /> |
</private> |
<path name="Fig16.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3568,7 → 3639,7
justification="Center" |
>IfcSpc</text> |
<group name="Fig17.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[353, 249, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[353, 249, 174, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:000000000000093B" |
fill="0" |
fillcolor="white" |
3582,7 → 3653,7
<rectangle name="Fig17.2.0" |
x="353" |
y="249" |
width="64" |
width="174" |
height="0" |
fill="0" |
fillcolor="white" |
3741,7 → 3812,7
justification="Center" |
>IfcDef</text> |
<group name="Fig18.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[361, 457, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[361, 457, 150, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:000000000000093C" |
fill="0" |
fillcolor="white" |
3755,7 → 3826,7
<rectangle name="Fig18.2.0" |
x="361" |
y="457" |
width="64" |
width="150" |
height="0" |
fill="0" |
fillcolor="white" |
3937,7 → 4008,7
offset="29" /> |
</private> |
<path name="Fig19.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
3994,7 → 4065,7
offset="5" /> |
</private> |
<path name="Fig20.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
4044,7 → 4115,7
justification="Center" |
>IFCPort</text> |
<group name="Fig21.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[153, 513, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[153, 513, 110, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000958" |
fill="0" |
fillcolor="white" |
4058,7 → 4129,7
<rectangle name="Fig21.2.0" |
x="153" |
y="513" |
width="64" |
width="110" |
height="0" |
fill="0" |
fillcolor="white" |
4208,7 → 4279,7
offset="24" /> |
</private> |
<path name="Fig22.0" |
description="org.tigris.gef.presentation.FigPoly" |
description="org.argouml.gefext.ArgoFigPoly" |
fill="0" |
fillcolor="white" |
stroke="1" |
4221,7 → 4292,7
</path> |
</group> |
<group name="Fig23" |
description="org.argouml.uml.diagram.static_structure.ui.FigClass[184, 856, 128, 95]pathVisible=false;stereotypeView=0;operationsVisible=true;attributesVisible=true;" |
description="org.argouml.uml.diagram.static_structure.ui.FigClass[312, 720, 128, 95]pathVisible=false;stereotypeView=0;operationsVisible=true;attributesVisible=true;" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000966" |
fill="1" |
fillcolor="white" |
4232,8 → 4303,8
</private> |
|
<rectangle name="Fig23.0" |
x="184" |
y="856" |
x="312" |
y="720" |
width="128" |
height="95" |
fill="1" |
4242,8 → 4313,8
strokecolor="black" |
/> |
<text name="Fig23.1" |
x="185" |
y="857" |
x="313" |
y="721" |
width="126" |
height="22" |
fill="0" |
4258,7 → 4329,7
justification="Center" |
>HDLCoder</text> |
<group name="Fig23.2" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[185, 856, 64, 0]" |
description="org.argouml.uml.diagram.ui.FigStereotypesGroup[313, 721, 126, 0]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000966" |
fill="0" |
fillcolor="white" |
4270,9 → 4341,9
</private> |
|
<rectangle name="Fig23.2.0" |
x="185" |
y="856" |
width="64" |
x="313" |
y="721" |
width="126" |
height="0" |
fill="0" |
fillcolor="white" |
4281,8 → 4352,8
/> |
</group> |
<rectangle name="Fig23.3" |
x="184" |
y="879" |
x="312" |
y="743" |
width="128" |
height="1" |
fill="1" |
4291,7 → 4362,7
strokecolor="black" |
/> |
<group name="Fig23.4" |
description="org.argouml.uml.diagram.ui.FigAttributesCompartment[185, 880, 126, 34]" |
description="org.argouml.uml.diagram.ui.FigAttributesCompartment[313, 744, 126, 34]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000966" |
fill="0" |
fillcolor="white" |
4302,8 → 4373,8
</private> |
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<rectangle name="Fig23.4.0" |
x="185" |
y="880" |
x="313" |
y="744" |
width="126" |
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fill="0" |
4313,8 → 4384,8
/> |
</group> |
<rectangle name="Fig23.5" |
x="184" |
y="914" |
x="312" |
y="778" |
width="128" |
height="1" |
fill="1" |
4323,7 → 4394,7
strokecolor="black" |
/> |
<group name="Fig23.6" |
description="org.argouml.uml.diagram.ui.FigOperationsCompartment[185, 915, 126, 34]" |
description="org.argouml.uml.diagram.ui.FigOperationsCompartment[313, 779, 126, 34]" |
href="127-0-0-1-7fb16bdf:1461af0060b:-8000:0000000000000966" |
fill="0" |
fillcolor="white" |
4334,8 → 4405,8
</private> |
|
<rectangle name="Fig23.6.0" |
x="185" |
y="915" |
x="313" |
y="779" |
width="126" |
height="34" |
fill="0" |
4346,7 → 4417,7
</group> |
</group> |
<group name="Fig24" |
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fill="1" |
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4357,8 → 4428,8
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|
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x="248" |
y="896" |
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height="88" |
fill="1" |
4367,8 → 4438,8
strokecolor="black" |
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<text name="Fig24.1" |
x="113" |
y="1001" |
x="249" |
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4383,7 → 4454,7
justification="Center" |
>VHDLCoder</text> |
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fill="0" |
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4395,9 → 4466,9
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|
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4406,8 → 4477,8
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</group> |
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x="248" |
y="919" |
width="120" |
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fill="1" |
4416,7 → 4487,7
strokecolor="black" |
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<group name="Fig24.4" |
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fill="0" |
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4427,8 → 4498,8
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4438,8 → 4509,8
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</group> |
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height="1" |
fill="1" |
4448,7 → 4519,7
strokecolor="black" |
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fill="0" |
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4459,8 → 4530,8
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fill="0" |
4471,7 → 4542,7
</group> |
</group> |
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4482,8 → 4553,8
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|
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4492,8 → 4563,8
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4508,7 → 4579,7
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4520,9 → 4591,9
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4531,8 → 4602,8
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4541,7 → 4612,7
strokecolor="black" |
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4552,8 → 4623,8
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4573,7 → 4644,7
strokecolor="black" |
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fill="0" |
fillcolor="white" |
4584,8 → 4655,8
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|
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4594,8 → 4665,8
strokecolor="black" |
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<text name="Fig25.6.1" |
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width="110" |
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4630,16 → 4701,16
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<moveto x="344" |
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<lineto x="344" |
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<group name="Fig27" |
4661,16 → 4732,16
offset="-10" /> |
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<moveto x="432" |
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<lineto x="432" |
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4718,18 → 4789,476
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<lineto x="439" |
y="768" /> |
</path> |
</group> |
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<private> |
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|
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<text name="Fig29.1" |
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font="Dialog" |
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>ConInst</text> |
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<private> |
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<private> |
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fillcolor="white" |
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<private> |
</private> |
|
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fill="0" |
fillcolor="white" |
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strokecolor="black" |
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</group> |
</group> |
<group name="Fig30" |
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href="127-0-0-1--639abe74:1462d254995:-8000:0000000000000B5B" |
fill="1" |
fillcolor="white" |
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<private> |
</private> |
|
<rectangle name="Fig30.0" |
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fill="1" |
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<text name="Fig30.1" |
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>ConInstExclusive</text> |
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<private> |
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|
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</group> |
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<group name="Fig30.4" |
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<private> |
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|
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<group name="Fig30.6" |
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<private> |
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|
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</group> |
</group> |
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<private> |
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</group> |
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<private> |
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</private> |
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<private> |
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<private> |
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/soc_maker/trunk/lib/soc_maker/.conf.rb.swo
File deleted
\ No newline at end of file
/soc_maker/trunk/lib/soc_maker/.core_inst.rb.swp
File deleted
\ No newline at end of file
/soc_maker/trunk/lib/soc_maker/.hdl_file.rb.swp
File deleted
\ No newline at end of file
/soc_maker/trunk/lib/soc_maker/.component.rb.swp
File deleted
\ No newline at end of file
/soc_maker/trunk/lib/soc_maker/.ypp.rb.swp
File deleted
\ No newline at end of file
/soc_maker/trunk/lib/soc_maker/ifc_def.rb
103,7 → 103,7
|
# ports |
serr_if( coder[ 'ports' ] == nil, |
"No ports are given for interface defiinition", |
"No ports are given for interface definition", |
field: 'ports' ) |
@ports = coder[ 'ports' ] |
serr_if( !@ports.is_a?( Hash ) || |
/soc_maker/trunk/lib/soc_maker/hdl_coder.rb
87,7 → 87,7
# In addition, we add some VHDL comments (author, mail, license) |
# |
def add_core_declaration( core_name, core_spec ) |
|
|
@decl_part << "--\n" |
@decl_part << "-- core author: #{core_spec.author} - #{core_spec.authormail}\n" |
@decl_part << "-- license: #{core_spec.license}\n" |
189,6 → 189,9
|
|
|
|
|
|
|
def ifc_declaration( ifc_spec, ifc_name, length ) |
|
221,32 → 224,42
dst_ifc_sel = src_ifc |
end |
|
port_tmp_name = "#{ifc_name}_#{port_name.to_s}" |
|
# length == 0 means, that no |
# signal is assigned to this connection |
if length[ port_name ] > 0 |
|
# combine all sources |
tmp = "#{port_tmp_name} <= " |
# loop over instances |
src_inst_sel.each_with_index do |(inst_name, inst), i| |
( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name ) |
tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ] |
tmp << "#{inst_name}_#{tmp_name}" |
tmp << " and \n" unless i == src_inst_sel.size-1 |
end |
tmp << ";\n" |
@asgn_part << tmp |
port_tmp_name = "#{ifc_name}_#{port_name.to_s}" |
|
# assign to destination |
tmp = "" |
dst_inst_sel.each_with_index do |(inst_name, inst), i| |
( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name ) |
tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}" |
tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1 |
|
# combine all sources |
tmp = "#{port_tmp_name} <= " |
# loop over instances |
src_inst_sel.each_with_index do |(inst_name, inst), i| |
( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name ) |
if port != nil |
tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ] |
tmp << "#{inst_name}_#{tmp_name}" |
tmp << " and \n" unless i == src_inst_sel.size-1 |
end |
|
end |
tmp << ";\n" |
@asgn_part << tmp |
|
# assign to destination |
tmp = "" |
dst_inst_sel.each_with_index do |(inst_name, inst), i| |
( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name ) |
if port != nil |
tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}" |
tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1 |
tmp << ";\n" |
end |
end |
@asgn_part << tmp |
end |
@asgn_part << tmp |
|
|
end |
|
|
257,7 → 270,8
|
# TODO: add sig list as argument (or interface list) for entity description |
def get_entity( soc, entity_name ) |
entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n") |
add_toplevel_sig( soc, entity_name ) |
entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n") + "\n" |
entity_str << "-- Auto-Generated by #{SOCMaker::conf[ :app_name ]} \n" |
entity_str << "-- Date: #{Time.now}\n" |
entity_str << SOCMaker::conf[ :vhdl_include ] + "\n" |
285,10 → 299,21
return entity_str |
end |
|
def add_toplevel_sig( soc, entity_name ) |
soc.ports do |port_name, length, dir, is_last| |
@asgn_part << "#{port_name} <= #{entity_name}_#{port_name}" |
@asgn_part << "," unless is_last |
@asgn_part << "\n" |
if length > 1 |
@decl_part << "signal #{entity_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n" |
else |
@decl_part << "signal #{entity_name}_#{port_name} : std_logic;\n" |
end |
end |
end |
|
|
|
|
def asgn_str( ifc_spec, con, ifc_name, core1, core1_name, core2, core2_name ) |
port_string = "" |
|
/soc_maker/trunk/lib/soc_maker/core_inst.rb
78,11 → 78,6
|
end |
|
# |
# TODO: extract the HDL ports |
# |
# HDLParam = Struct.new( :value, :type ) |
# HDLPort = Struct.new( :len, :dir ) |
def ports |
@ports.each_with_index do |(name, port_def), i| |
yield( name.to_s, port_def[ :len ], port_def[ :dir ], i==@ports.size-1 ) |
102,14 → 97,20
|
def get_len( ifc_name, port_spec_name ) |
|
# get the port name, which we are using |
|
# get the port name, which we are using |
tmp = @defn.interfaces[ ifc_name.to_sym ]. |
ports.select{ |key,hash| hash.defn == port_spec_name.to_s }. |
keys.first.to_s |
return @ports[ tmp.to_sym ][ :len ] |
|
return tmp.size == 0 ? 0 : @ports[ tmp.to_sym ][ :len ] |
end |
|
|
def implements_port?( ifc_name, port_spec_name ) |
@defn.implements_port?( ifc_name, port_spec_name ) |
end |
|
def get_port( ifc_name, port_spec_name ) |
tmp = @defn.interfaces[ ifc_name.to_sym ]. |
ports.select{ |key,hash| hash.defn == port_spec_name.to_s }. |
190,8 → 191,11
end |
|
|
def to_s |
"type: #{type}\n" + |
"params: #{params}\n" |
end |
|
|
def ==(o) |
o.class == self.class && |
o.type == self.type && |
/soc_maker/trunk/lib/soc_maker/soc_def.rb
82,15 → 82,6
end |
|
|
def get_and_ensure_dst_dir!( core_name ) |
dst_dir = File.expand_path( |
File.join( |
SOCMaker::conf[ :build_dir ], |
SOCMaker::conf[ :hdl_dir ], |
core_name ) ) |
FileUtils.mkdir_p dst_dir |
return dst_dir |
end |
|
|
|
140,6 → 131,20
end |
|
|
|
def get_core_def( inst ) |
if @cores[ inst.to_sym ] != nil |
return @cores[ inst.to_sym ].defn |
elsif inst == @name |
return self |
else |
perr_if( true, |
"Instance '#{inst}' does not exist in SOC '#{self.name}'" ) |
end |
end |
|
|
|
def add_connection( inst1, ifc1_name, inst2, ifc2_name, con_name ) |
|
return nil if inst_in_use?( con_name ) |
151,15 → 156,11
"Interface #{sub_arr[ 1 ]} of instance '#{sub_arr[ 0 ]}' is already in use " ) |
end |
|
[ inst1, inst2 ].each do |inst| |
perr_if( @cores[ inst.to_sym ] == nil, |
"Instance '#{inst}' does not exist in SOC '#{self.name}'" ) |
end |
|
# get the core-specs |
core_spec_1 = SOCMaker::lib.get_core( @cores[ inst1.to_sym ].type ) |
core_spec_2 = SOCMaker::lib.get_core( @cores[ inst2.to_sym ].type ) |
core_spec_1 = get_core_def( inst1 ) |
core_spec_2 = get_core_def( inst2 ) |
|
|
[ [ core_spec_1, ifc1_name ], |
[ core_spec_2, ifc2_name ] ].each do |sub_arr| |
perr_if( sub_arr[ 0 ].interfaces[ sub_arr[ 1 ].to_sym ] == nil, |
182,7 → 183,7
:rule => "or", |
:mapping => [ { inst1.to_sym => ifc1_name.to_sym }, |
{ inst2.to_sym => ifc2_name.to_sym } ] } |
|
return false |
end |
|
def set_param( instance, param, value ) |
251,7 → 252,7
|
def gen_toplevel( coder = VHDLCoder.new() ) |
|
file_name = @name |
file_name = @name.dup |
|
if coder.is_a?( VHDLCoder ) |
file_name << ".vhd" |
328,28 → 329,30
|
# fetch somehow the spec |
ifc_spec = SOCMaker::lib.get_ifc( |
@cores[ src.keys.first ].defn.interfaces[ src.values.first ].name, |
@cores[ src.keys.first ].defn.interfaces[ src.values.first ].version ) |
get_core_def( src.keys.first.to_s ).interfaces[ src.values.first ].name, |
get_core_def( src.keys.first.to_s ).interfaces[ src.values.first ].version ) |
|
length_tmp = {}; |
|
port_used_tmp = {}; |
ifc_spec.ports.keys.each do |_name| |
# TODO: bis dahin konnte angenommen werden, dass self auch eine Art instanz ist, |
# aber hier geht das nicht mehr, weil get_len nur für CoreInst definiert ist. |
# |
|
|
# create a length table |
length_tmp[ _name ] = [] |
port_used_tmp[ _name ] = false |
dst.each do |inst_name, ifc_name| |
length_tmp[ _name ] << @cores[ inst_name ].get_len( ifc_name, _name ) |
port_used_tmp[ _name ] ||= get_core_def( inst_name ).implements_port?( ifc_name, _name ) |
end |
src.each do |inst_name, ifc_name| |
length_tmp[ _name ] << @cores[ inst_name ].get_len( ifc_name, _name ) |
port_used_tmp[ _name ] ||= get_core_def( inst_name ).implements_port?( ifc_name, _name ) |
end |
|
end |
|
# getting the maximum length for each signal |
max_length = Hash[ length_tmp.map{ |key, arr| [ key, arr.max ] } ] |
# max_length = Hash[ length_tmp.map{ |key, arr| [ key, arr.max ] } ] |
|
coder.ifc_declaration( ifc_spec, name, max_length ) |
# coder.ifc_declaration( ifc_spec, name, max_length ) |
|
|
|
362,7 → 365,7
|
|
|
coder.ifc_assignment( ifc_spec, name, max_length, src_inst, dst_inst, src, dst ) |
# coder.ifc_assignment( ifc_spec, name, max_length, src_inst, dst_inst, src, dst ) |
|
end |
|
384,8 → 387,9
# copy each file into destination dir |
core_def.hdlfiles.each do |file, val| |
file_path = File.join( core_def.dir, val.path ) |
dst_path = File.join( dst_dir, file.to_s ) |
dst_path = File.join( dst_dir, val.path ) |
SOCMaker::logger.proc( "copy #{file_path} to #{ dst_path} " ) |
FileUtils.mkdir_p(File.dirname(dst_path)) |
FileUtils.cp( file_path, dst_path ) |
end |
|
450,6 → 454,25
end |
|
|
def to_s |
|
tmp = "_________ SOC #{@name}: _______\n" + |
super + |
"\n__connections__\n" |
|
@cons.each do |_con_name, con_def| |
tmp += "#{_con_name}: #{con_def}\n" |
end |
|
tmp += "\n__cores__\n" |
@cores.each do |inst_name, inst| |
tmp += "#{inst_name}:\n#{inst}\n" |
end |
tmp += "'''''''''''''''''''''''''''''''''''\n" |
return tmp |
end |
|
|
end # class SOCSpec |
end # module SOCMaker |
|
/soc_maker/trunk/lib/soc_maker/component.rb
222,8 → 222,11
|
|
def get_files |
unless self.vccmd.nil? or self.vccmd == 0 |
system( self.vccmd ) |
puts "PATH: " |
p File.join( @dir ) |
unless self.vccmd.nil? or @vccmd.size == 0 |
puts"cd #{@dir} && #{@vccmd}" |
system( "cd #{@dir} && #{vccmd} " ) |
end |
end |
|
236,6 → 239,15
end |
end |
|
def get_and_ensure_dst_dir!( core_name ) |
dst_dir = File.expand_path( |
File.join( |
SOCMaker::conf[ :build_dir ], |
SOCMaker::conf[ :hdl_dir ], |
core_name ) ) |
FileUtils.mkdir_p dst_dir |
return dst_dir |
end |
|
# |
# Iterates over interface list. |
311,9 → 323,17
|
end |
|
def implements_port?( ifc_name, port_spec_name ) |
tmp = @interfaces[ ifc_name.to_sym ]. |
ports.select{ |key,hash| hash.defn == port_spec_name.to_s }.keys |
|
perr_if( tmp.size > 1, |
"The port #{port_spec_name} of interface #{ifc_name} is implemented |
multiple times" ) |
|
return tmp.size == 1 |
end |
|
|
def param_ok?( param_name, param_value ) |
param = inst_parameters[ param_name.to_sym ] |
param = static_parameters[ param_name.to_sym ] if param == nil |
355,6 → 375,23
return true |
end |
|
def to_s |
"version: #{@version}\n" + |
"toplevel: #{@toplevel}\n" + |
"description: #{@description}\n" + |
"date: #{@date}\n" + |
"license: #{@license}\n" + |
"licensefile: #{@licensefile}\n" + |
"author: #{@author}\n" + |
"authormail: #{@authormail}\n" + |
"vccmd: #{@vccmd}\n" + |
"interfaces: #{@interfaces}\n" + |
"functions: #{@functions}\n" + |
"inst_parameters: #{@inst_parameters}\n" + |
"static_parameters: #{@static_parameters}\n" |
end |
|
|
end # class CoreDef |
end # module SOCMaker |
|
/soc_maker/trunk/lib/soc_maker/core_def.rb
101,11 → 101,11
end |
|
|
def get_files |
unless self.vccmd.nil? or self.vccmd == 0 |
system( self.vccmd ) |
end |
end |
# def get_files |
# unless self.vccmd.nil? or self.vccmd.size == 0 |
# system( self.vccmd ) |
# end |
# end |
|
|
|
/soc_maker/trunk/lib/soc_maker/lib.rb
247,6 → 247,15
return ifc_list |
end |
|
|
# |
# TODO add test code |
# |
def cores |
@cores_lib.each do |nameversion,core| |
yield( nameversion.to_s, core ) |
end |
end |
|
|
end #class Lib |
/soc_maker/trunk/lib/soc_maker/cli.rb
285,6 → 285,20
end |
|
|
|
PRINT_USAGE = |
" > print # prints SOC information |
|
" |
def do_print( args ) |
if args.size != 0 |
puts "no arguments are required:\nusage:\n#{PRINT_USAGE}" |
else |
puts @soc |
end |
end |
|
|
# |
# Quit |
# |
322,6 → 336,23
@commands.each { |c| eval "puts #{c.upcase}_USAGE" } |
end |
|
|
SET_USAGE = |
" > set # not implemented yet |
|
" |
def do_set( args ) |
puts "NOT IMPLEMENTED, YET" |
end |
|
GET_USAGE = |
" > get # not implemented yet |
|
" |
def do_get( args ) |
puts "NOT IMPLEMENTED, YET" |
end |
|
# end command implementations |
# |
################################# |
331,12 → 362,6
@soc = nil |
|
def initialize |
## |
# Setup readline |
# |
@cmd_list = %w[ list generate open exit |
help quit add parameter save |
connect sparameter delete ].sort |
|
# appreviation map |
@appr_map = { 'n' => "new", |
350,6 → 375,7
'p' => "parameter", |
'd' => "delete", |
'c' => "connect", |
'i' => "print", |
'x' => "exit" |
} |
|
356,9 → 382,9
# all available commands |
@commands = %w[ new open list add parameter sparameter |
delete connect save help quit exit |
generate ] |
generate print set get ] |
|
comp = proc { |s| (@cmd_list + Dir.entries( Dir.pwd )).grep( /^#{Regexp.escape(s)}/ ) } |
comp = proc { |s| (@commands + Dir.entries( Dir.pwd )).grep( /^#{Regexp.escape(s)}/ ) } |
Readline.completion_append_character = " " |
Readline.completion_proc = comp |
|
/soc_maker/trunk/bin/soc_maker_cli
22,7 → 22,8
exit |
end |
|
opts.on("-l", "--library <p1,p2,p3...>", Array, "Sets library include paths (overrides config value)" ) do |path| |
opts.on("-l", "--library <p1,p2,p3...>", Array, |
"Sets library include paths (overrides config value)" ) do |path| |
cmd_options.lib_inc << path |
end |
|
/soc_maker/trunk/spec/test_soc.yaml
8,7 → 8,22
author: 'feddischson' |
authormail: 'feddischson [ at ] opencores.org' |
vccmd: '' |
interfaces: {} |
interfaces: |
:top_ifc: SOCM_IFC |
name: core_AB_ifc |
dir: 0 |
version: "1" |
ports: |
:sig_con1a: SOCM_PORT |
defn: sig_a |
len: 8 |
:sig_con1b: SOCM_PORT |
defn: sig_b |
len: 8 |
:sig_con1c: SOCM_PORT |
defn: sig_c |
len: 1 |
|
functions: {} |
inst_parameters: {} |
static_parameters: {} |
38,5 → 53,10
:mapping: |
- :inst_a: :ifc01 |
- :inst_c: :myifc |
# :top_con: |
# :rule: or |
# :mapping: |
# - :test_soc: :top_ifc |
# - :inst_d: :myifc |
hdlfiles: {} |
toplevel: test_soc_top |
/soc_maker/trunk/spec/core_inst_spec.rb
80,6 → 80,24
|
end |
|
describe SOCMaker::CoreDef, "HDL interaction" do |
|
it 'should return true and false for implements_port?, when a port is implemented and |
not implemented' do |
file = { "file.vhd".to_sym => SOCMaker::HDLFile.new( "./file.vhd" ) } |
core = SOCMaker::CoreDef.new( "mycore", "rel1", file, "top" ) |
ifc_spc = SOCMaker::IfcSpc.new( "a_ifc", "v1", "ports" => { p1: 1, p2: 0 } ) |
ifc = SOCMaker::IfcDef.new( "a_ifc", "v1", 1, { p1: SOCMaker::IfcPort.new( "p1", 1 ) } ) |
core.interfaces[ :i1 ] = ifc |
SOCMaker::lib.add_core( core ) |
SOCMaker::lib.add_ifc( ifc_spc ) |
|
o1 = SOCMaker::CoreInst.new( "mycorerel1", {} ) |
o1.implements_port?( 'i1', 'p1' ).should be == true |
o1.implements_port?( 'i1', 'p2' ).should be == false |
end |
end |
|
describe SOCMaker::CoreDef, "object handling, en-decoding:" do |
|
it "should be possible to encode and decode a core instance" do |
/soc_maker/trunk/spec/soc_def_spec.rb
285,6 → 285,32
@soc.cons[ :a_new_con ].should be == { rule:'or', mapping: [ {inst_a: :ifc_a},{inst_b: :ifc_b} ] } |
end |
|
|
|
|
it "should add a connection entry, which connects the toplevel's port" do |
|
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: 1, port_b: 0 } ) |
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ) } ) |
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { b: SOCMaker::IfcPort.new( "port_b", 1 ) } ) |
file = { "file.vhd".to_sym => SOCMaker::HDLFile.new( "./file.vhd" ) } |
core_a = SOCMaker::CoreDef.new( "core_a", "v1", file, "top" ) |
core_a.interfaces[ :ifc_a ] = ifc_def_0 |
core_a.interfaces[ :ifc_b ] = ifc_def_1 |
|
SOCMaker::lib.add_ifc( ifc_spc ) |
SOCMaker::lib.add_core( core_a ) |
|
|
SOCMaker::lib.add_core( @soc ) |
@soc.interfaces[ :t1 ] = ifc_def_1 |
@soc.cores[ :inst_a ] = SOCMaker::CoreInst.new( "core_av1" ) |
@soc.add_connection( "inst_a", "ifc_a", @soc.name, "t1", "a_new_con" ) |
@soc.cons[ :a_new_con ].should be == { rule:'or', mapping: [ {inst_a: :ifc_a},{ @soc.name.to_sym => :t1} ] } |
end |
|
|
|
it "should raise an error, if a parameter of unkonwn core is set" do |
expect{ @soc.set_param( "a_unknown_core", "p1", 1234 ) }. |
to raise_error( SOCMaker::ERR::ProcessingError ) |
/soc_maker/trunk/spec/component_spec.rb
174,7 → 174,9
a_is_last.should be == [ false, false, false, true ] |
end |
|
|
|
|
it 'should iterate over all ports' do |
|
SOCMaker::lib.clear |
/soc_maker/trunk/examples/or1200_test.rb
0,0 → 1,30
require_relative '../lib/soc_maker' |
|
options = {} |
options[ :libpath ] = "./core_lib/" |
## |
# initialize SOCMaker core |
# this sets up logging and parses all yaml files |
# found in the configure path (see also soc_maker_conf.rb) |
SOCMaker::load( options ) |
|
|
puts "Library Content:" |
|
|
puts SOCMaker::lib |
|
|
SOCMaker::lib.cores do |name_version, core| |
core.get_files |
end |
|
soc = SOCMaker::SOCDef.new( 'or1200_test', 'v1', 'or1200_test' ) |
|
soc.add_core( 'or1200', 'rel2', 'cpu' ) |
soc.add_core( 'wb_connect', '1', 'wb_bus' ) |
|
soc.add_connection( 'cpu', 'wb_instruction', 'wb_bus', 'i0', 'con_instruction' ) |
soc.gen_toplevel |
soc.copy_files |
|
/soc_maker/trunk/core_lib/interfaces/clk_rst/single.yaml
0,0 → 1,6
SOCM_IFC_SPC |
name: single |
version: "1" |
ports: |
:single: 0 |
|
/soc_maker/trunk/core_lib/interfaces/clk_rst/rst.yaml
0,0 → 1,5
SOCM_IFC_SPC |
name: rst |
version: "1" |
ports: |
:rst: 0 |
/soc_maker/trunk/core_lib/interfaces/clk_rst/clk.yaml
0,0 → 1,5
SOCM_IFC_SPC |
name: clk |
version: "1" |
ports: |
:clk: 0 |
/soc_maker/trunk/core_lib/interfaces/debug/debug.yaml
0,0 → 1,16
SOCM_IFC_SPC |
name: debug |
version: "1" |
ports: |
:dbg_stall: 0 |
:dbg_ewt: 0 |
:dbg_lss: 1 |
:dbg_iso: 1 |
:dbg_wpo: 1 |
:dbg_bpo: 1 |
:dbg_stb: 0 |
:dbg_we: 0 |
:dbg_adr: 0 |
:dbg_dat: 0 |
:dbg_dat: 1 |
:dbg_ack: 1 |
/soc_maker/trunk/core_lib/interfaces/power/or_power.yaml
0,0 → 1,15
SOCM_IFC_SPC |
name: or_power_management |
version: "1" |
ports: |
:pm_cpustall: 0 |
:pm_clksd: 1 |
:pm_dc_gate: 1 |
:pm_ic_gate: 1 |
:pm_dmmu_gate: 1 |
:pm_immu_gate: 1 |
:pm_tt_gate: 1 |
:pm_cpu_gate: 1 |
:pm_wakeup: 1 |
:pm_lvolt: 1 |
|
/soc_maker/trunk/core_lib/interfaces/wishbone/wishbone_ma_b3.yaml
0,0 → 1,19
SOCM_IFC_SPC |
name: wishbone_ma |
version: "b3" |
ports: |
:dat_i: 0 |
:dat_o: 1 |
:tgd_i: 1 |
:tgd_o: 0 |
:adr: 1 |
:cyc: 1 |
:err: 0 |
:lock: 1 |
:rty: 0 |
:sel: 1 |
:stb: 1 |
:tga: 1 |
:tgc: 1 |
:we: 1 |
:ack: 0 |
/soc_maker/trunk/core_lib/interfaces/wishbone/wishbone_sl_b3.yaml
0,0 → 1,20
SOCM_IFC_SPC |
name: wishbone_sl |
version: "b3" |
ports: |
:dat_i: 0 |
:dat_o: 1 |
:tgd_i: 1 |
:tgd_o: 0 |
:ack: 1 |
:adr: 0 |
:cyc: 0 |
:err: 1 |
:lock: 0 |
:rty: 1 |
:sel: 0 |
:stb: 0 |
:tga: 0 |
:tgc: 0 |
:we: 0 |
|
/soc_maker/trunk/core_lib/inc.yaml
0,0 → 1,8
SOCM_INCLUDE |
dirs: |
- cores/or1200_rel2 |
- cores/wb_connect |
- interfaces/clk_rst |
- interfaces/debug |
- interfaces/power |
- interfaces/wishbone |
/soc_maker/trunk/core_lib/cores/wb_connect/wb_connect.yaml
0,0 → 1,564
SOCM_CORE |
name: wb_connect |
description: A block to connect RISC and peripheral controllers together |
version: "1" |
license: LGPL |
licensefile: |
author: Damjan Lampret |
authormail: lampret@opencores.org |
toplevel: minsoc_tc_top |
interfaces: |
:i0: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i0_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i0_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i0_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i0_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i0_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i0_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i0_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i0_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i0_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i1: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i1_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i1_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i1_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i1_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i1_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i1_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i1_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i1_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i1_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i2: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i2_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i2_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i2_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i2_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i2_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i2_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i2_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i2_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i2_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i3: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i3_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i3_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i3_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i3_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i3_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i3_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i3_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i3_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i3_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i4: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i4_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i4_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i4_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i4_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i4_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i4_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i4_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i4_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i4_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i5: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i5_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i5_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i5_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i5_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i5_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i5_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i5_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i5_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i5_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i6: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i6_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i6_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i6_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i6_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i6_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i6_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i6_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i6_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i6_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:i7: SOCM_IFC |
name: wishbone_ma |
dir: 1 |
version: "b3" |
ports: |
:i7_wb_cyc_i: SOCM_PORT |
defn: cyc |
len: 1 |
:i7_wb_stb_i: SOCM_PORT |
defn: stb |
len: 1 |
:i7_wb_adr_i: SOCM_PORT |
defn: adr |
len: 32 |
:i7_wb_sel_i: SOCM_PORT |
defn: sel |
len: 1 |
:i7_wb_we_i: SOCM_PORT |
defn: we |
len: 1 |
:i7_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:i7_wb_dat_o: SOCM_PORT |
defn: dat_o |
len: 32 |
:i7_wb_ack_o: SOCM_PORT |
defn: ack |
len: 1 |
:i7_wb_err_o: SOCM_PORT |
defn: err |
len: 1 |
:t0: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t0_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t0_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t0_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t0_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t0_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t0_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t0_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t0_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t0_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t1: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t1_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t1_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t1_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t1_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t1_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t1_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t1_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t1_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t1_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t2: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t2_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t2_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t2_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t2_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t2_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t2_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t2_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t2_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t2_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t3: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t3_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t3_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t3_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t3_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t3_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t3_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t3_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t3_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t3_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t4: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t4_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t4_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t4_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t4_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t4_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t4_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t4_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t4_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t4_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t5: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t5_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t5_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t5_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t5_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t5_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t5_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t5_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t5_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t5_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t6: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t6_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t6_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t6_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t6_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t6_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t6_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t6_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t6_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t6_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t7: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t7_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t7_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t7_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t7_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t7_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t7_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t7_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t7_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t7_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
:t8: SOCM_IFC |
name: wishbone_sl |
dir: 1 |
version: "b3" |
ports: |
:t8_wb_cyc_o: SOCM_PORT |
defn: cyc |
len: 1 |
:t8_wb_stb_o: SOCM_PORT |
defn: stb |
len: 1 |
:t8_wb_adr_o: SOCM_PORT |
defn: adr |
len: 32 |
:t8_wb_sel_o: SOCM_PORT |
defn: sel |
len: 1 |
:t8_wb_we_o: SOCM_PORT |
defn: we |
len: 1 |
:t8_wb_dat_o: SOCM_PORT |
defn: dat_i |
len: 32 |
:t8_wb_dat_i: SOCM_PORT |
defn: dat_i |
len: 32 |
:t8_wb_ack_i: SOCM_PORT |
defn: ack |
len: 1 |
:t8_wb_err_i: SOCM_PORT |
defn: err |
len: 1 |
|
|
|
|
hdlfiles: |
:minsoc_tc_top: SOCM_HDL_FILE |
use_syn: true |
use_sim: true |
type: verilog |
path: minsoc_tc_top.v |
/soc_maker/trunk/core_lib/cores/wb_connect/minsoc_tc_top.v
0,0 → 1,1684
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Xess Traffic Cop //// |
//// //// |
//// This file is part of the OR1K test application //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// //// |
//// Description //// |
//// This block connectes the RISC and peripheral controller //// |
//// cores together. //// |
//// //// |
//// To Do: //// |
//// - nothing really //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002 OpenCores //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: tc_top.v,v $ |
// Revision 1.4 2004/04/05 08:44:34 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.2 2002/03/29 20:57:30 lampret |
// Removed unused ports wb_clki and wb_rst_i |
// |
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret |
// First import of the "new" XESS XSV environment. |
// |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
|
// |
// Width of address bus |
// |
`define TC_AW 32 |
|
// |
// Width of data bus |
// |
`define TC_DW 32 |
|
// |
// Width of byte select bus |
// |
`define TC_BSW 4 |
|
// |
// Width of WB target inputs (coming from WB slave) |
// |
// data bus width + ack + err |
// |
`define TC_TIN_W `TC_DW+1+1 |
|
// |
// Width of WB initiator inputs (coming from WB masters) |
// |
// cyc + stb + address bus width + |
// byte select bus width + we + data bus width |
// |
`define TC_IIN_W 1+1+`TC_AW+`TC_BSW+1+`TC_DW |
|
// |
// Traffic Cop Top |
// |
module minsoc_tc_top ( |
wb_clk_i, |
wb_rst_i, |
|
i0_wb_cyc_i, |
i0_wb_stb_i, |
i0_wb_adr_i, |
i0_wb_sel_i, |
i0_wb_we_i, |
i0_wb_dat_i, |
i0_wb_dat_o, |
i0_wb_ack_o, |
i0_wb_err_o, |
|
i1_wb_cyc_i, |
i1_wb_stb_i, |
i1_wb_adr_i, |
i1_wb_sel_i, |
i1_wb_we_i, |
i1_wb_dat_i, |
i1_wb_dat_o, |
i1_wb_ack_o, |
i1_wb_err_o, |
|
i2_wb_cyc_i, |
i2_wb_stb_i, |
i2_wb_adr_i, |
i2_wb_sel_i, |
i2_wb_we_i, |
i2_wb_dat_i, |
i2_wb_dat_o, |
i2_wb_ack_o, |
i2_wb_err_o, |
|
i3_wb_cyc_i, |
i3_wb_stb_i, |
i3_wb_adr_i, |
i3_wb_sel_i, |
i3_wb_we_i, |
i3_wb_dat_i, |
i3_wb_dat_o, |
i3_wb_ack_o, |
i3_wb_err_o, |
|
i4_wb_cyc_i, |
i4_wb_stb_i, |
i4_wb_adr_i, |
i4_wb_sel_i, |
i4_wb_we_i, |
i4_wb_dat_i, |
i4_wb_dat_o, |
i4_wb_ack_o, |
i4_wb_err_o, |
|
i5_wb_cyc_i, |
i5_wb_stb_i, |
i5_wb_adr_i, |
i5_wb_sel_i, |
i5_wb_we_i, |
i5_wb_dat_i, |
i5_wb_dat_o, |
i5_wb_ack_o, |
i5_wb_err_o, |
|
i6_wb_cyc_i, |
i6_wb_stb_i, |
i6_wb_adr_i, |
i6_wb_sel_i, |
i6_wb_we_i, |
i6_wb_dat_i, |
i6_wb_dat_o, |
i6_wb_ack_o, |
i6_wb_err_o, |
|
i7_wb_cyc_i, |
i7_wb_stb_i, |
i7_wb_adr_i, |
i7_wb_sel_i, |
i7_wb_we_i, |
i7_wb_dat_i, |
i7_wb_dat_o, |
i7_wb_ack_o, |
i7_wb_err_o, |
|
t0_wb_cyc_o, |
t0_wb_stb_o, |
t0_wb_adr_o, |
t0_wb_sel_o, |
t0_wb_we_o, |
t0_wb_dat_o, |
t0_wb_dat_i, |
t0_wb_ack_i, |
t0_wb_err_i, |
|
t1_wb_cyc_o, |
t1_wb_stb_o, |
t1_wb_adr_o, |
t1_wb_sel_o, |
t1_wb_we_o, |
t1_wb_dat_o, |
t1_wb_dat_i, |
t1_wb_ack_i, |
t1_wb_err_i, |
|
t2_wb_cyc_o, |
t2_wb_stb_o, |
t2_wb_adr_o, |
t2_wb_sel_o, |
t2_wb_we_o, |
t2_wb_dat_o, |
t2_wb_dat_i, |
t2_wb_ack_i, |
t2_wb_err_i, |
|
t3_wb_cyc_o, |
t3_wb_stb_o, |
t3_wb_adr_o, |
t3_wb_sel_o, |
t3_wb_we_o, |
t3_wb_dat_o, |
t3_wb_dat_i, |
t3_wb_ack_i, |
t3_wb_err_i, |
|
t4_wb_cyc_o, |
t4_wb_stb_o, |
t4_wb_adr_o, |
t4_wb_sel_o, |
t4_wb_we_o, |
t4_wb_dat_o, |
t4_wb_dat_i, |
t4_wb_ack_i, |
t4_wb_err_i, |
|
t5_wb_cyc_o, |
t5_wb_stb_o, |
t5_wb_adr_o, |
t5_wb_sel_o, |
t5_wb_we_o, |
t5_wb_dat_o, |
t5_wb_dat_i, |
t5_wb_ack_i, |
t5_wb_err_i, |
|
t6_wb_cyc_o, |
t6_wb_stb_o, |
t6_wb_adr_o, |
t6_wb_sel_o, |
t6_wb_we_o, |
t6_wb_dat_o, |
t6_wb_dat_i, |
t6_wb_ack_i, |
t6_wb_err_i, |
|
t7_wb_cyc_o, |
t7_wb_stb_o, |
t7_wb_adr_o, |
t7_wb_sel_o, |
t7_wb_we_o, |
t7_wb_dat_o, |
t7_wb_dat_i, |
t7_wb_ack_i, |
t7_wb_err_i, |
|
t8_wb_cyc_o, |
t8_wb_stb_o, |
t8_wb_adr_o, |
t8_wb_sel_o, |
t8_wb_we_o, |
t8_wb_dat_o, |
t8_wb_dat_i, |
t8_wb_ack_i, |
t8_wb_err_i |
|
); |
|
// |
// Parameters |
// |
parameter t0_addr_w = 4; |
parameter t0_addr = 4'd8; |
parameter t1_addr_w = 4; |
parameter t1_addr = 4'd0; |
parameter t28c_addr_w = 4; |
parameter t28_addr = 4'd0; |
parameter t28i_addr_w = 4; |
parameter t2_addr = 4'd1; |
parameter t3_addr = 4'd2; |
parameter t4_addr = 4'd3; |
parameter t5_addr = 4'd4; |
parameter t6_addr = 4'd5; |
parameter t7_addr = 4'd6; |
parameter t8_addr = 4'd7; |
|
// |
// I/O Ports |
// |
input wb_clk_i; |
input wb_rst_i; |
|
// |
// WB slave i/f connecting initiator 0 |
// |
input i0_wb_cyc_i; |
input i0_wb_stb_i; |
input [`TC_AW-1:0] i0_wb_adr_i; |
input [`TC_BSW-1:0] i0_wb_sel_i; |
input i0_wb_we_i; |
input [`TC_DW-1:0] i0_wb_dat_i; |
output [`TC_DW-1:0] i0_wb_dat_o; |
output i0_wb_ack_o; |
output i0_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 1 |
// |
input i1_wb_cyc_i; |
input i1_wb_stb_i; |
input [`TC_AW-1:0] i1_wb_adr_i; |
input [`TC_BSW-1:0] i1_wb_sel_i; |
input i1_wb_we_i; |
input [`TC_DW-1:0] i1_wb_dat_i; |
output [`TC_DW-1:0] i1_wb_dat_o; |
output i1_wb_ack_o; |
output i1_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 2 |
// |
input i2_wb_cyc_i; |
input i2_wb_stb_i; |
input [`TC_AW-1:0] i2_wb_adr_i; |
input [`TC_BSW-1:0] i2_wb_sel_i; |
input i2_wb_we_i; |
input [`TC_DW-1:0] i2_wb_dat_i; |
output [`TC_DW-1:0] i2_wb_dat_o; |
output i2_wb_ack_o; |
output i2_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 3 |
// |
input i3_wb_cyc_i; |
input i3_wb_stb_i; |
input [`TC_AW-1:0] i3_wb_adr_i; |
input [`TC_BSW-1:0] i3_wb_sel_i; |
input i3_wb_we_i; |
input [`TC_DW-1:0] i3_wb_dat_i; |
output [`TC_DW-1:0] i3_wb_dat_o; |
output i3_wb_ack_o; |
output i3_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 4 |
// |
input i4_wb_cyc_i; |
input i4_wb_stb_i; |
input [`TC_AW-1:0] i4_wb_adr_i; |
input [`TC_BSW-1:0] i4_wb_sel_i; |
input i4_wb_we_i; |
input [`TC_DW-1:0] i4_wb_dat_i; |
output [`TC_DW-1:0] i4_wb_dat_o; |
output i4_wb_ack_o; |
output i4_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 5 |
// |
input i5_wb_cyc_i; |
input i5_wb_stb_i; |
input [`TC_AW-1:0] i5_wb_adr_i; |
input [`TC_BSW-1:0] i5_wb_sel_i; |
input i5_wb_we_i; |
input [`TC_DW-1:0] i5_wb_dat_i; |
output [`TC_DW-1:0] i5_wb_dat_o; |
output i5_wb_ack_o; |
output i5_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 6 |
// |
input i6_wb_cyc_i; |
input i6_wb_stb_i; |
input [`TC_AW-1:0] i6_wb_adr_i; |
input [`TC_BSW-1:0] i6_wb_sel_i; |
input i6_wb_we_i; |
input [`TC_DW-1:0] i6_wb_dat_i; |
output [`TC_DW-1:0] i6_wb_dat_o; |
output i6_wb_ack_o; |
output i6_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 7 |
// |
input i7_wb_cyc_i; |
input i7_wb_stb_i; |
input [`TC_AW-1:0] i7_wb_adr_i; |
input [`TC_BSW-1:0] i7_wb_sel_i; |
input i7_wb_we_i; |
input [`TC_DW-1:0] i7_wb_dat_i; |
output [`TC_DW-1:0] i7_wb_dat_o; |
output i7_wb_ack_o; |
output i7_wb_err_o; |
|
// |
// WB master i/f connecting target 0 |
// |
output t0_wb_cyc_o; |
output t0_wb_stb_o; |
output [`TC_AW-1:0] t0_wb_adr_o; |
output [`TC_BSW-1:0] t0_wb_sel_o; |
output t0_wb_we_o; |
output [`TC_DW-1:0] t0_wb_dat_o; |
input [`TC_DW-1:0] t0_wb_dat_i; |
input t0_wb_ack_i; |
input t0_wb_err_i; |
|
// |
// WB master i/f connecting target 1 |
// |
output t1_wb_cyc_o; |
output t1_wb_stb_o; |
output [`TC_AW-1:0] t1_wb_adr_o; |
output [`TC_BSW-1:0] t1_wb_sel_o; |
output t1_wb_we_o; |
output [`TC_DW-1:0] t1_wb_dat_o; |
input [`TC_DW-1:0] t1_wb_dat_i; |
input t1_wb_ack_i; |
input t1_wb_err_i; |
|
// |
// WB master i/f connecting target 2 |
// |
output t2_wb_cyc_o; |
output t2_wb_stb_o; |
output [`TC_AW-1:0] t2_wb_adr_o; |
output [`TC_BSW-1:0] t2_wb_sel_o; |
output t2_wb_we_o; |
output [`TC_DW-1:0] t2_wb_dat_o; |
input [`TC_DW-1:0] t2_wb_dat_i; |
input t2_wb_ack_i; |
input t2_wb_err_i; |
|
// |
// WB master i/f connecting target 3 |
// |
output t3_wb_cyc_o; |
output t3_wb_stb_o; |
output [`TC_AW-1:0] t3_wb_adr_o; |
output [`TC_BSW-1:0] t3_wb_sel_o; |
output t3_wb_we_o; |
output [`TC_DW-1:0] t3_wb_dat_o; |
input [`TC_DW-1:0] t3_wb_dat_i; |
input t3_wb_ack_i; |
input t3_wb_err_i; |
|
// |
// WB master i/f connecting target 4 |
// |
output t4_wb_cyc_o; |
output t4_wb_stb_o; |
output [`TC_AW-1:0] t4_wb_adr_o; |
output [`TC_BSW-1:0] t4_wb_sel_o; |
output t4_wb_we_o; |
output [`TC_DW-1:0] t4_wb_dat_o; |
input [`TC_DW-1:0] t4_wb_dat_i; |
input t4_wb_ack_i; |
input t4_wb_err_i; |
|
// |
// WB master i/f connecting target 5 |
// |
output t5_wb_cyc_o; |
output t5_wb_stb_o; |
output [`TC_AW-1:0] t5_wb_adr_o; |
output [`TC_BSW-1:0] t5_wb_sel_o; |
output t5_wb_we_o; |
output [`TC_DW-1:0] t5_wb_dat_o; |
input [`TC_DW-1:0] t5_wb_dat_i; |
input t5_wb_ack_i; |
input t5_wb_err_i; |
|
// |
// WB master i/f connecting target 6 |
// |
output t6_wb_cyc_o; |
output t6_wb_stb_o; |
output [`TC_AW-1:0] t6_wb_adr_o; |
output [`TC_BSW-1:0] t6_wb_sel_o; |
output t6_wb_we_o; |
output [`TC_DW-1:0] t6_wb_dat_o; |
input [`TC_DW-1:0] t6_wb_dat_i; |
input t6_wb_ack_i; |
input t6_wb_err_i; |
|
// |
// WB master i/f connecting target 7 |
// |
output t7_wb_cyc_o; |
output t7_wb_stb_o; |
output [`TC_AW-1:0] t7_wb_adr_o; |
output [`TC_BSW-1:0] t7_wb_sel_o; |
output t7_wb_we_o; |
output [`TC_DW-1:0] t7_wb_dat_o; |
input [`TC_DW-1:0] t7_wb_dat_i; |
input t7_wb_ack_i; |
input t7_wb_err_i; |
|
// |
// WB master i/f connecting target 8 |
// |
output t8_wb_cyc_o; |
output t8_wb_stb_o; |
output [`TC_AW-1:0] t8_wb_adr_o; |
output [`TC_BSW-1:0] t8_wb_sel_o; |
output t8_wb_we_o; |
output [`TC_DW-1:0] t8_wb_dat_o; |
input [`TC_DW-1:0] t8_wb_dat_i; |
input t8_wb_ack_i; |
input t8_wb_err_i; |
|
// |
// Internal wires & registers |
// |
|
// |
// Outputs for initiators from both mi_to_st blocks |
// |
wire [`TC_DW-1:0] xi0_wb_dat_o; |
wire xi0_wb_ack_o; |
wire xi0_wb_err_o; |
wire [`TC_DW-1:0] xi1_wb_dat_o; |
wire xi1_wb_ack_o; |
wire xi1_wb_err_o; |
wire [`TC_DW-1:0] xi2_wb_dat_o; |
wire xi2_wb_ack_o; |
wire xi2_wb_err_o; |
wire [`TC_DW-1:0] xi3_wb_dat_o; |
wire xi3_wb_ack_o; |
wire xi3_wb_err_o; |
wire [`TC_DW-1:0] xi4_wb_dat_o; |
wire xi4_wb_ack_o; |
wire xi4_wb_err_o; |
wire [`TC_DW-1:0] xi5_wb_dat_o; |
wire xi5_wb_ack_o; |
wire xi5_wb_err_o; |
wire [`TC_DW-1:0] xi6_wb_dat_o; |
wire xi6_wb_ack_o; |
wire xi6_wb_err_o; |
wire [`TC_DW-1:0] xi7_wb_dat_o; |
wire xi7_wb_ack_o; |
wire xi7_wb_err_o; |
wire [`TC_DW-1:0] yi0_wb_dat_o; |
wire yi0_wb_ack_o; |
wire yi0_wb_err_o; |
wire [`TC_DW-1:0] yi1_wb_dat_o; |
wire yi1_wb_ack_o; |
wire yi1_wb_err_o; |
wire [`TC_DW-1:0] yi2_wb_dat_o; |
wire yi2_wb_ack_o; |
wire yi2_wb_err_o; |
wire [`TC_DW-1:0] yi3_wb_dat_o; |
wire yi3_wb_ack_o; |
wire yi3_wb_err_o; |
wire [`TC_DW-1:0] yi4_wb_dat_o; |
wire yi4_wb_ack_o; |
wire yi4_wb_err_o; |
wire [`TC_DW-1:0] yi5_wb_dat_o; |
wire yi5_wb_ack_o; |
wire yi5_wb_err_o; |
wire [`TC_DW-1:0] yi6_wb_dat_o; |
wire yi6_wb_ack_o; |
wire yi6_wb_err_o; |
wire [`TC_DW-1:0] yi7_wb_dat_o; |
wire yi7_wb_ack_o; |
wire yi7_wb_err_o; |
|
// |
// Intermediate signals connecting peripheral channel's |
// mi_to_st and si_to_mt blocks. |
// |
wire z_wb_cyc_i; |
wire z_wb_stb_i; |
wire [`TC_AW-1:0] z_wb_adr_i; |
wire [`TC_BSW-1:0] z_wb_sel_i; |
wire z_wb_we_i; |
wire [`TC_DW-1:0] z_wb_dat_i; |
wire [`TC_DW-1:0] z_wb_dat_t; |
wire z_wb_ack_t; |
wire z_wb_err_t; |
|
// |
// Outputs for initiators are ORed from both mi_to_st blocks |
// |
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; |
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; |
assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; |
assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; |
assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; |
assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; |
assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; |
assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; |
assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; |
assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; |
assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; |
assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; |
assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; |
assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; |
assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; |
assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; |
assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; |
assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; |
assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; |
assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; |
assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; |
assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; |
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; |
assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; |
|
// |
// From initiators to target 0 |
// |
tc_mi_to_st #(t0_addr_w, t0_addr, |
0, t0_addr_w, t0_addr) t0_ch( |
.wb_clk_i(wb_clk_i), |
.wb_rst_i(wb_rst_i), |
|
.i0_wb_cyc_i(i0_wb_cyc_i), |
.i0_wb_stb_i(i0_wb_stb_i), |
.i0_wb_adr_i(i0_wb_adr_i), |
.i0_wb_sel_i(i0_wb_sel_i), |
.i0_wb_we_i(i0_wb_we_i), |
.i0_wb_dat_i(i0_wb_dat_i), |
.i0_wb_dat_o(xi0_wb_dat_o), |
.i0_wb_ack_o(xi0_wb_ack_o), |
.i0_wb_err_o(xi0_wb_err_o), |
|
.i1_wb_cyc_i(i1_wb_cyc_i), |
.i1_wb_stb_i(i1_wb_stb_i), |
.i1_wb_adr_i(i1_wb_adr_i), |
.i1_wb_sel_i(i1_wb_sel_i), |
.i1_wb_we_i(i1_wb_we_i), |
.i1_wb_dat_i(i1_wb_dat_i), |
.i1_wb_dat_o(xi1_wb_dat_o), |
.i1_wb_ack_o(xi1_wb_ack_o), |
.i1_wb_err_o(xi1_wb_err_o), |
|
.i2_wb_cyc_i(i2_wb_cyc_i), |
.i2_wb_stb_i(i2_wb_stb_i), |
.i2_wb_adr_i(i2_wb_adr_i), |
.i2_wb_sel_i(i2_wb_sel_i), |
.i2_wb_we_i(i2_wb_we_i), |
.i2_wb_dat_i(i2_wb_dat_i), |
.i2_wb_dat_o(xi2_wb_dat_o), |
.i2_wb_ack_o(xi2_wb_ack_o), |
.i2_wb_err_o(xi2_wb_err_o), |
|
.i3_wb_cyc_i(i3_wb_cyc_i), |
.i3_wb_stb_i(i3_wb_stb_i), |
.i3_wb_adr_i(i3_wb_adr_i), |
.i3_wb_sel_i(i3_wb_sel_i), |
.i3_wb_we_i(i3_wb_we_i), |
.i3_wb_dat_i(i3_wb_dat_i), |
.i3_wb_dat_o(xi3_wb_dat_o), |
.i3_wb_ack_o(xi3_wb_ack_o), |
.i3_wb_err_o(xi3_wb_err_o), |
|
.i4_wb_cyc_i(i4_wb_cyc_i), |
.i4_wb_stb_i(i4_wb_stb_i), |
.i4_wb_adr_i(i4_wb_adr_i), |
.i4_wb_sel_i(i4_wb_sel_i), |
.i4_wb_we_i(i4_wb_we_i), |
.i4_wb_dat_i(i4_wb_dat_i), |
.i4_wb_dat_o(xi4_wb_dat_o), |
.i4_wb_ack_o(xi4_wb_ack_o), |
.i4_wb_err_o(xi4_wb_err_o), |
|
.i5_wb_cyc_i(i5_wb_cyc_i), |
.i5_wb_stb_i(i5_wb_stb_i), |
.i5_wb_adr_i(i5_wb_adr_i), |
.i5_wb_sel_i(i5_wb_sel_i), |
.i5_wb_we_i(i5_wb_we_i), |
.i5_wb_dat_i(i5_wb_dat_i), |
.i5_wb_dat_o(xi5_wb_dat_o), |
.i5_wb_ack_o(xi5_wb_ack_o), |
.i5_wb_err_o(xi5_wb_err_o), |
|
.i6_wb_cyc_i(i6_wb_cyc_i), |
.i6_wb_stb_i(i6_wb_stb_i), |
.i6_wb_adr_i(i6_wb_adr_i), |
.i6_wb_sel_i(i6_wb_sel_i), |
.i6_wb_we_i(i6_wb_we_i), |
.i6_wb_dat_i(i6_wb_dat_i), |
.i6_wb_dat_o(xi6_wb_dat_o), |
.i6_wb_ack_o(xi6_wb_ack_o), |
.i6_wb_err_o(xi6_wb_err_o), |
|
.i7_wb_cyc_i(i7_wb_cyc_i), |
.i7_wb_stb_i(i7_wb_stb_i), |
.i7_wb_adr_i(i7_wb_adr_i), |
.i7_wb_sel_i(i7_wb_sel_i), |
.i7_wb_we_i(i7_wb_we_i), |
.i7_wb_dat_i(i7_wb_dat_i), |
.i7_wb_dat_o(xi7_wb_dat_o), |
.i7_wb_ack_o(xi7_wb_ack_o), |
.i7_wb_err_o(xi7_wb_err_o), |
|
.t0_wb_cyc_o(t0_wb_cyc_o), |
.t0_wb_stb_o(t0_wb_stb_o), |
.t0_wb_adr_o(t0_wb_adr_o), |
.t0_wb_sel_o(t0_wb_sel_o), |
.t0_wb_we_o(t0_wb_we_o), |
.t0_wb_dat_o(t0_wb_dat_o), |
.t0_wb_dat_i(t0_wb_dat_i), |
.t0_wb_ack_i(t0_wb_ack_i), |
.t0_wb_err_i(t0_wb_err_i) |
|
); |
|
// |
// From initiators to targets 1-8 (upper part) |
// |
tc_mi_to_st #(t1_addr_w, t1_addr, |
1, t28c_addr_w, t28_addr) t18_ch_upper( |
.wb_clk_i(wb_clk_i), |
.wb_rst_i(wb_rst_i), |
|
.i0_wb_cyc_i(i0_wb_cyc_i), |
.i0_wb_stb_i(i0_wb_stb_i), |
.i0_wb_adr_i(i0_wb_adr_i), |
.i0_wb_sel_i(i0_wb_sel_i), |
.i0_wb_we_i(i0_wb_we_i), |
.i0_wb_dat_i(i0_wb_dat_i), |
.i0_wb_dat_o(yi0_wb_dat_o), |
.i0_wb_ack_o(yi0_wb_ack_o), |
.i0_wb_err_o(yi0_wb_err_o), |
|
.i1_wb_cyc_i(i1_wb_cyc_i), |
.i1_wb_stb_i(i1_wb_stb_i), |
.i1_wb_adr_i(i1_wb_adr_i), |
.i1_wb_sel_i(i1_wb_sel_i), |
.i1_wb_we_i(i1_wb_we_i), |
.i1_wb_dat_i(i1_wb_dat_i), |
.i1_wb_dat_o(yi1_wb_dat_o), |
.i1_wb_ack_o(yi1_wb_ack_o), |
.i1_wb_err_o(yi1_wb_err_o), |
|
.i2_wb_cyc_i(i2_wb_cyc_i), |
.i2_wb_stb_i(i2_wb_stb_i), |
.i2_wb_adr_i(i2_wb_adr_i), |
.i2_wb_sel_i(i2_wb_sel_i), |
.i2_wb_we_i(i2_wb_we_i), |
.i2_wb_dat_i(i2_wb_dat_i), |
.i2_wb_dat_o(yi2_wb_dat_o), |
.i2_wb_ack_o(yi2_wb_ack_o), |
.i2_wb_err_o(yi2_wb_err_o), |
|
.i3_wb_cyc_i(i3_wb_cyc_i), |
.i3_wb_stb_i(i3_wb_stb_i), |
.i3_wb_adr_i(i3_wb_adr_i), |
.i3_wb_sel_i(i3_wb_sel_i), |
.i3_wb_we_i(i3_wb_we_i), |
.i3_wb_dat_i(i3_wb_dat_i), |
.i3_wb_dat_o(yi3_wb_dat_o), |
.i3_wb_ack_o(yi3_wb_ack_o), |
.i3_wb_err_o(yi3_wb_err_o), |
|
.i4_wb_cyc_i(i4_wb_cyc_i), |
.i4_wb_stb_i(i4_wb_stb_i), |
.i4_wb_adr_i(i4_wb_adr_i), |
.i4_wb_sel_i(i4_wb_sel_i), |
.i4_wb_we_i(i4_wb_we_i), |
.i4_wb_dat_i(i4_wb_dat_i), |
.i4_wb_dat_o(yi4_wb_dat_o), |
.i4_wb_ack_o(yi4_wb_ack_o), |
.i4_wb_err_o(yi4_wb_err_o), |
|
.i5_wb_cyc_i(i5_wb_cyc_i), |
.i5_wb_stb_i(i5_wb_stb_i), |
.i5_wb_adr_i(i5_wb_adr_i), |
.i5_wb_sel_i(i5_wb_sel_i), |
.i5_wb_we_i(i5_wb_we_i), |
.i5_wb_dat_i(i5_wb_dat_i), |
.i5_wb_dat_o(yi5_wb_dat_o), |
.i5_wb_ack_o(yi5_wb_ack_o), |
.i5_wb_err_o(yi5_wb_err_o), |
|
.i6_wb_cyc_i(i6_wb_cyc_i), |
.i6_wb_stb_i(i6_wb_stb_i), |
.i6_wb_adr_i(i6_wb_adr_i), |
.i6_wb_sel_i(i6_wb_sel_i), |
.i6_wb_we_i(i6_wb_we_i), |
.i6_wb_dat_i(i6_wb_dat_i), |
.i6_wb_dat_o(yi6_wb_dat_o), |
.i6_wb_ack_o(yi6_wb_ack_o), |
.i6_wb_err_o(yi6_wb_err_o), |
|
.i7_wb_cyc_i(i7_wb_cyc_i), |
.i7_wb_stb_i(i7_wb_stb_i), |
.i7_wb_adr_i(i7_wb_adr_i), |
.i7_wb_sel_i(i7_wb_sel_i), |
.i7_wb_we_i(i7_wb_we_i), |
.i7_wb_dat_i(i7_wb_dat_i), |
.i7_wb_dat_o(yi7_wb_dat_o), |
.i7_wb_ack_o(yi7_wb_ack_o), |
.i7_wb_err_o(yi7_wb_err_o), |
|
.t0_wb_cyc_o(z_wb_cyc_i), |
.t0_wb_stb_o(z_wb_stb_i), |
.t0_wb_adr_o(z_wb_adr_i), |
.t0_wb_sel_o(z_wb_sel_i), |
.t0_wb_we_o(z_wb_we_i), |
.t0_wb_dat_o(z_wb_dat_i), |
.t0_wb_dat_i(z_wb_dat_t), |
.t0_wb_ack_i(z_wb_ack_t), |
.t0_wb_err_i(z_wb_err_t) |
|
); |
|
// |
// From initiators to targets 1-8 (lower part) |
// |
tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, |
t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( |
|
.i0_wb_cyc_i(z_wb_cyc_i), |
.i0_wb_stb_i(z_wb_stb_i), |
.i0_wb_adr_i(z_wb_adr_i), |
.i0_wb_sel_i(z_wb_sel_i), |
.i0_wb_we_i(z_wb_we_i), |
.i0_wb_dat_i(z_wb_dat_i), |
.i0_wb_dat_o(z_wb_dat_t), |
.i0_wb_ack_o(z_wb_ack_t), |
.i0_wb_err_o(z_wb_err_t), |
|
.t0_wb_cyc_o(t1_wb_cyc_o), |
.t0_wb_stb_o(t1_wb_stb_o), |
.t0_wb_adr_o(t1_wb_adr_o), |
.t0_wb_sel_o(t1_wb_sel_o), |
.t0_wb_we_o(t1_wb_we_o), |
.t0_wb_dat_o(t1_wb_dat_o), |
.t0_wb_dat_i(t1_wb_dat_i), |
.t0_wb_ack_i(t1_wb_ack_i), |
.t0_wb_err_i(t1_wb_err_i), |
|
.t1_wb_cyc_o(t2_wb_cyc_o), |
.t1_wb_stb_o(t2_wb_stb_o), |
.t1_wb_adr_o(t2_wb_adr_o), |
.t1_wb_sel_o(t2_wb_sel_o), |
.t1_wb_we_o(t2_wb_we_o), |
.t1_wb_dat_o(t2_wb_dat_o), |
.t1_wb_dat_i(t2_wb_dat_i), |
.t1_wb_ack_i(t2_wb_ack_i), |
.t1_wb_err_i(t2_wb_err_i), |
|
.t2_wb_cyc_o(t3_wb_cyc_o), |
.t2_wb_stb_o(t3_wb_stb_o), |
.t2_wb_adr_o(t3_wb_adr_o), |
.t2_wb_sel_o(t3_wb_sel_o), |
.t2_wb_we_o(t3_wb_we_o), |
.t2_wb_dat_o(t3_wb_dat_o), |
.t2_wb_dat_i(t3_wb_dat_i), |
.t2_wb_ack_i(t3_wb_ack_i), |
.t2_wb_err_i(t3_wb_err_i), |
|
.t3_wb_cyc_o(t4_wb_cyc_o), |
.t3_wb_stb_o(t4_wb_stb_o), |
.t3_wb_adr_o(t4_wb_adr_o), |
.t3_wb_sel_o(t4_wb_sel_o), |
.t3_wb_we_o(t4_wb_we_o), |
.t3_wb_dat_o(t4_wb_dat_o), |
.t3_wb_dat_i(t4_wb_dat_i), |
.t3_wb_ack_i(t4_wb_ack_i), |
.t3_wb_err_i(t4_wb_err_i), |
|
.t4_wb_cyc_o(t5_wb_cyc_o), |
.t4_wb_stb_o(t5_wb_stb_o), |
.t4_wb_adr_o(t5_wb_adr_o), |
.t4_wb_sel_o(t5_wb_sel_o), |
.t4_wb_we_o(t5_wb_we_o), |
.t4_wb_dat_o(t5_wb_dat_o), |
.t4_wb_dat_i(t5_wb_dat_i), |
.t4_wb_ack_i(t5_wb_ack_i), |
.t4_wb_err_i(t5_wb_err_i), |
|
.t5_wb_cyc_o(t6_wb_cyc_o), |
.t5_wb_stb_o(t6_wb_stb_o), |
.t5_wb_adr_o(t6_wb_adr_o), |
.t5_wb_sel_o(t6_wb_sel_o), |
.t5_wb_we_o(t6_wb_we_o), |
.t5_wb_dat_o(t6_wb_dat_o), |
.t5_wb_dat_i(t6_wb_dat_i), |
.t5_wb_ack_i(t6_wb_ack_i), |
.t5_wb_err_i(t6_wb_err_i), |
|
.t6_wb_cyc_o(t7_wb_cyc_o), |
.t6_wb_stb_o(t7_wb_stb_o), |
.t6_wb_adr_o(t7_wb_adr_o), |
.t6_wb_sel_o(t7_wb_sel_o), |
.t6_wb_we_o(t7_wb_we_o), |
.t6_wb_dat_o(t7_wb_dat_o), |
.t6_wb_dat_i(t7_wb_dat_i), |
.t6_wb_ack_i(t7_wb_ack_i), |
.t6_wb_err_i(t7_wb_err_i), |
|
.t7_wb_cyc_o(t8_wb_cyc_o), |
.t7_wb_stb_o(t8_wb_stb_o), |
.t7_wb_adr_o(t8_wb_adr_o), |
.t7_wb_sel_o(t8_wb_sel_o), |
.t7_wb_we_o(t8_wb_we_o), |
.t7_wb_dat_o(t8_wb_dat_o), |
.t7_wb_dat_i(t8_wb_dat_i), |
.t7_wb_ack_i(t8_wb_ack_i), |
.t7_wb_err_i(t8_wb_err_i) |
|
); |
|
endmodule |
|
// |
// Multiple initiator to single target |
// |
module tc_mi_to_st ( |
wb_clk_i, |
wb_rst_i, |
|
i0_wb_cyc_i, |
i0_wb_stb_i, |
i0_wb_adr_i, |
i0_wb_sel_i, |
i0_wb_we_i, |
i0_wb_dat_i, |
i0_wb_dat_o, |
i0_wb_ack_o, |
i0_wb_err_o, |
|
i1_wb_cyc_i, |
i1_wb_stb_i, |
i1_wb_adr_i, |
i1_wb_sel_i, |
i1_wb_we_i, |
i1_wb_dat_i, |
i1_wb_dat_o, |
i1_wb_ack_o, |
i1_wb_err_o, |
|
i2_wb_cyc_i, |
i2_wb_stb_i, |
i2_wb_adr_i, |
i2_wb_sel_i, |
i2_wb_we_i, |
i2_wb_dat_i, |
i2_wb_dat_o, |
i2_wb_ack_o, |
i2_wb_err_o, |
|
i3_wb_cyc_i, |
i3_wb_stb_i, |
i3_wb_adr_i, |
i3_wb_sel_i, |
i3_wb_we_i, |
i3_wb_dat_i, |
i3_wb_dat_o, |
i3_wb_ack_o, |
i3_wb_err_o, |
|
i4_wb_cyc_i, |
i4_wb_stb_i, |
i4_wb_adr_i, |
i4_wb_sel_i, |
i4_wb_we_i, |
i4_wb_dat_i, |
i4_wb_dat_o, |
i4_wb_ack_o, |
i4_wb_err_o, |
|
i5_wb_cyc_i, |
i5_wb_stb_i, |
i5_wb_adr_i, |
i5_wb_sel_i, |
i5_wb_we_i, |
i5_wb_dat_i, |
i5_wb_dat_o, |
i5_wb_ack_o, |
i5_wb_err_o, |
|
i6_wb_cyc_i, |
i6_wb_stb_i, |
i6_wb_adr_i, |
i6_wb_sel_i, |
i6_wb_we_i, |
i6_wb_dat_i, |
i6_wb_dat_o, |
i6_wb_ack_o, |
i6_wb_err_o, |
|
i7_wb_cyc_i, |
i7_wb_stb_i, |
i7_wb_adr_i, |
i7_wb_sel_i, |
i7_wb_we_i, |
i7_wb_dat_i, |
i7_wb_dat_o, |
i7_wb_ack_o, |
i7_wb_err_o, |
|
t0_wb_cyc_o, |
t0_wb_stb_o, |
t0_wb_adr_o, |
t0_wb_sel_o, |
t0_wb_we_o, |
t0_wb_dat_o, |
t0_wb_dat_i, |
t0_wb_ack_i, |
t0_wb_err_i |
|
); |
|
// |
// Parameters |
// |
parameter t0_addr_w = 2; |
parameter t0_addr = 2'b00; |
parameter multitarg = 1'b0; |
parameter t17_addr_w = 2; |
parameter t17_addr = 2'b00; |
|
// |
// I/O Ports |
// |
input wb_clk_i; |
input wb_rst_i; |
|
// |
// WB slave i/f connecting initiator 0 |
// |
input i0_wb_cyc_i; |
input i0_wb_stb_i; |
input [`TC_AW-1:0] i0_wb_adr_i; |
input [`TC_BSW-1:0] i0_wb_sel_i; |
input i0_wb_we_i; |
input [`TC_DW-1:0] i0_wb_dat_i; |
output [`TC_DW-1:0] i0_wb_dat_o; |
output i0_wb_ack_o; |
output i0_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 1 |
// |
input i1_wb_cyc_i; |
input i1_wb_stb_i; |
input [`TC_AW-1:0] i1_wb_adr_i; |
input [`TC_BSW-1:0] i1_wb_sel_i; |
input i1_wb_we_i; |
input [`TC_DW-1:0] i1_wb_dat_i; |
output [`TC_DW-1:0] i1_wb_dat_o; |
output i1_wb_ack_o; |
output i1_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 2 |
// |
input i2_wb_cyc_i; |
input i2_wb_stb_i; |
input [`TC_AW-1:0] i2_wb_adr_i; |
input [`TC_BSW-1:0] i2_wb_sel_i; |
input i2_wb_we_i; |
input [`TC_DW-1:0] i2_wb_dat_i; |
output [`TC_DW-1:0] i2_wb_dat_o; |
output i2_wb_ack_o; |
output i2_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 3 |
// |
input i3_wb_cyc_i; |
input i3_wb_stb_i; |
input [`TC_AW-1:0] i3_wb_adr_i; |
input [`TC_BSW-1:0] i3_wb_sel_i; |
input i3_wb_we_i; |
input [`TC_DW-1:0] i3_wb_dat_i; |
output [`TC_DW-1:0] i3_wb_dat_o; |
output i3_wb_ack_o; |
output i3_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 4 |
// |
input i4_wb_cyc_i; |
input i4_wb_stb_i; |
input [`TC_AW-1:0] i4_wb_adr_i; |
input [`TC_BSW-1:0] i4_wb_sel_i; |
input i4_wb_we_i; |
input [`TC_DW-1:0] i4_wb_dat_i; |
output [`TC_DW-1:0] i4_wb_dat_o; |
output i4_wb_ack_o; |
output i4_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 5 |
// |
input i5_wb_cyc_i; |
input i5_wb_stb_i; |
input [`TC_AW-1:0] i5_wb_adr_i; |
input [`TC_BSW-1:0] i5_wb_sel_i; |
input i5_wb_we_i; |
input [`TC_DW-1:0] i5_wb_dat_i; |
output [`TC_DW-1:0] i5_wb_dat_o; |
output i5_wb_ack_o; |
output i5_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 6 |
// |
input i6_wb_cyc_i; |
input i6_wb_stb_i; |
input [`TC_AW-1:0] i6_wb_adr_i; |
input [`TC_BSW-1:0] i6_wb_sel_i; |
input i6_wb_we_i; |
input [`TC_DW-1:0] i6_wb_dat_i; |
output [`TC_DW-1:0] i6_wb_dat_o; |
output i6_wb_ack_o; |
output i6_wb_err_o; |
|
// |
// WB slave i/f connecting initiator 7 |
// |
input i7_wb_cyc_i; |
input i7_wb_stb_i; |
input [`TC_AW-1:0] i7_wb_adr_i; |
input [`TC_BSW-1:0] i7_wb_sel_i; |
input i7_wb_we_i; |
input [`TC_DW-1:0] i7_wb_dat_i; |
output [`TC_DW-1:0] i7_wb_dat_o; |
output i7_wb_ack_o; |
output i7_wb_err_o; |
|
// |
// WB master i/f connecting target |
// |
output t0_wb_cyc_o; |
output t0_wb_stb_o; |
output [`TC_AW-1:0] t0_wb_adr_o; |
output [`TC_BSW-1:0] t0_wb_sel_o; |
output t0_wb_we_o; |
output [`TC_DW-1:0] t0_wb_dat_o; |
input [`TC_DW-1:0] t0_wb_dat_i; |
input t0_wb_ack_i; |
input t0_wb_err_i; |
|
// |
// Internal wires & registers |
// |
wire [`TC_IIN_W-1:0] i0_in, i1_in, |
i2_in, i3_in, |
i4_in, i5_in, |
i6_in, i7_in; |
wire [`TC_TIN_W-1:0] i0_out, i1_out, |
i2_out, i3_out, |
i4_out, i5_out, |
i6_out, i7_out; |
wire [`TC_IIN_W-1:0] t0_out; |
wire [`TC_TIN_W-1:0] t0_in; |
wire [7:0] req_i; |
wire [2:0] req_won; |
reg req_cont; |
reg [2:0] req_r; |
|
// |
// Group WB initiator 0 i/f inputs and outputs |
// |
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, |
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; |
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; |
|
// |
// Group WB initiator 1 i/f inputs and outputs |
// |
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, |
i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i}; |
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; |
|
// |
// Group WB initiator 2 i/f inputs and outputs |
// |
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, |
i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i}; |
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; |
|
// |
// Group WB initiator 3 i/f inputs and outputs |
// |
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, |
i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i}; |
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; |
|
// |
// Group WB initiator 4 i/f inputs and outputs |
// |
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, |
i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i}; |
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; |
|
// |
// Group WB initiator 5 i/f inputs and outputs |
// |
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, |
i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i}; |
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; |
|
// |
// Group WB initiator 6 i/f inputs and outputs |
// |
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, |
i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i}; |
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; |
|
// |
// Group WB initiator 7 i/f inputs and outputs |
// |
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, |
i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i}; |
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; |
|
// |
// Group WB target 0 i/f inputs and outputs |
// |
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, |
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; |
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; |
|
// |
// Assign to WB initiator i/f outputs |
// |
// Either inputs from the target are assigned or zeros. |
// |
assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; |
assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; |
|
// |
// Assign to WB target i/f outputs |
// |
// Assign inputs from initiator to target outputs according to |
// which initiator has won. If there is no request for the target, |
// assign zeros. |
// |
assign t0_out = (req_won == 3'd0) ? i0_in : |
(req_won == 3'd1) ? i1_in : |
(req_won == 3'd2) ? i2_in : |
(req_won == 3'd3) ? i3_in : |
(req_won == 3'd4) ? i4_in : |
(req_won == 3'd5) ? i5_in : |
(req_won == 3'd6) ? i6_in : |
(req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; |
|
// |
// Determine if an initiator has address of the target. |
// |
assign req_i[0] = i0_wb_cyc_i & |
((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[1] = i1_wb_cyc_i & |
((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[2] = i2_wb_cyc_i & |
((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[3] = i3_wb_cyc_i & |
((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[4] = i4_wb_cyc_i & |
((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[5] = i5_wb_cyc_i & |
((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[6] = i6_wb_cyc_i & |
((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
assign req_i[7] = i7_wb_cyc_i & |
((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | |
multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); |
|
// |
// Determine who gets current access to the target. |
// |
// If current initiator still asserts request, do nothing |
// (keep current initiator). |
// Otherwise check each initiator's request, starting from initiator 0 |
// (highest priority). |
// If there is no requests from initiators, park initiator 0. |
// |
assign req_won = req_cont ? req_r : |
req_i[0] ? 3'd0 : |
req_i[1] ? 3'd1 : |
req_i[2] ? 3'd2 : |
req_i[3] ? 3'd3 : |
req_i[4] ? 3'd4 : |
req_i[5] ? 3'd5 : |
req_i[6] ? 3'd6 : |
req_i[7] ? 3'd7 : 3'd0; |
|
// |
// Check if current initiator still wants access to the target and if |
// it does, assert req_cont. |
// |
always @(req_r or req_i) |
case (req_r) // synopsys parallel_case |
3'd0: req_cont = req_i[0]; |
3'd1: req_cont = req_i[1]; |
3'd2: req_cont = req_i[2]; |
3'd3: req_cont = req_i[3]; |
3'd4: req_cont = req_i[4]; |
3'd5: req_cont = req_i[5]; |
3'd6: req_cont = req_i[6]; |
3'd7: req_cont = req_i[7]; |
endcase |
|
// |
// Register who has current access to the target. |
// |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
req_r <= 3'd0; |
else |
req_r <= req_won; |
|
endmodule |
|
// |
// Single initiator to multiple targets |
// |
module tc_si_to_mt ( |
|
i0_wb_cyc_i, |
i0_wb_stb_i, |
i0_wb_adr_i, |
i0_wb_sel_i, |
i0_wb_we_i, |
i0_wb_dat_i, |
i0_wb_dat_o, |
i0_wb_ack_o, |
i0_wb_err_o, |
|
t0_wb_cyc_o, |
t0_wb_stb_o, |
t0_wb_adr_o, |
t0_wb_sel_o, |
t0_wb_we_o, |
t0_wb_dat_o, |
t0_wb_dat_i, |
t0_wb_ack_i, |
t0_wb_err_i, |
|
t1_wb_cyc_o, |
t1_wb_stb_o, |
t1_wb_adr_o, |
t1_wb_sel_o, |
t1_wb_we_o, |
t1_wb_dat_o, |
t1_wb_dat_i, |
t1_wb_ack_i, |
t1_wb_err_i, |
|
t2_wb_cyc_o, |
t2_wb_stb_o, |
t2_wb_adr_o, |
t2_wb_sel_o, |
t2_wb_we_o, |
t2_wb_dat_o, |
t2_wb_dat_i, |
t2_wb_ack_i, |
t2_wb_err_i, |
|
t3_wb_cyc_o, |
t3_wb_stb_o, |
t3_wb_adr_o, |
t3_wb_sel_o, |
t3_wb_we_o, |
t3_wb_dat_o, |
t3_wb_dat_i, |
t3_wb_ack_i, |
t3_wb_err_i, |
|
t4_wb_cyc_o, |
t4_wb_stb_o, |
t4_wb_adr_o, |
t4_wb_sel_o, |
t4_wb_we_o, |
t4_wb_dat_o, |
t4_wb_dat_i, |
t4_wb_ack_i, |
t4_wb_err_i, |
|
t5_wb_cyc_o, |
t5_wb_stb_o, |
t5_wb_adr_o, |
t5_wb_sel_o, |
t5_wb_we_o, |
t5_wb_dat_o, |
t5_wb_dat_i, |
t5_wb_ack_i, |
t5_wb_err_i, |
|
t6_wb_cyc_o, |
t6_wb_stb_o, |
t6_wb_adr_o, |
t6_wb_sel_o, |
t6_wb_we_o, |
t6_wb_dat_o, |
t6_wb_dat_i, |
t6_wb_ack_i, |
t6_wb_err_i, |
|
t7_wb_cyc_o, |
t7_wb_stb_o, |
t7_wb_adr_o, |
t7_wb_sel_o, |
t7_wb_we_o, |
t7_wb_dat_o, |
t7_wb_dat_i, |
t7_wb_ack_i, |
t7_wb_err_i |
|
); |
|
// |
// Parameters |
// |
parameter t0_addr_w = 3; |
parameter t0_addr = 3'd0; |
parameter t17_addr_w = 3; |
parameter t1_addr = 3'd1; |
parameter t2_addr = 3'd2; |
parameter t3_addr = 3'd3; |
parameter t4_addr = 3'd4; |
parameter t5_addr = 3'd5; |
parameter t6_addr = 3'd6; |
parameter t7_addr = 3'd7; |
|
// |
// I/O Ports |
// |
|
// |
// WB slave i/f connecting initiator 0 |
// |
input i0_wb_cyc_i; |
input i0_wb_stb_i; |
input [`TC_AW-1:0] i0_wb_adr_i; |
input [`TC_BSW-1:0] i0_wb_sel_i; |
input i0_wb_we_i; |
input [`TC_DW-1:0] i0_wb_dat_i; |
output [`TC_DW-1:0] i0_wb_dat_o; |
output i0_wb_ack_o; |
output i0_wb_err_o; |
|
// |
// WB master i/f connecting target 0 |
// |
output t0_wb_cyc_o; |
output t0_wb_stb_o; |
output [`TC_AW-1:0] t0_wb_adr_o; |
output [`TC_BSW-1:0] t0_wb_sel_o; |
output t0_wb_we_o; |
output [`TC_DW-1:0] t0_wb_dat_o; |
input [`TC_DW-1:0] t0_wb_dat_i; |
input t0_wb_ack_i; |
input t0_wb_err_i; |
|
// |
// WB master i/f connecting target 1 |
// |
output t1_wb_cyc_o; |
output t1_wb_stb_o; |
output [`TC_AW-1:0] t1_wb_adr_o; |
output [`TC_BSW-1:0] t1_wb_sel_o; |
output t1_wb_we_o; |
output [`TC_DW-1:0] t1_wb_dat_o; |
input [`TC_DW-1:0] t1_wb_dat_i; |
input t1_wb_ack_i; |
input t1_wb_err_i; |
|
// |
// WB master i/f connecting target 2 |
// |
output t2_wb_cyc_o; |
output t2_wb_stb_o; |
output [`TC_AW-1:0] t2_wb_adr_o; |
output [`TC_BSW-1:0] t2_wb_sel_o; |
output t2_wb_we_o; |
output [`TC_DW-1:0] t2_wb_dat_o; |
input [`TC_DW-1:0] t2_wb_dat_i; |
input t2_wb_ack_i; |
input t2_wb_err_i; |
|
// |
// WB master i/f connecting target 3 |
// |
output t3_wb_cyc_o; |
output t3_wb_stb_o; |
output [`TC_AW-1:0] t3_wb_adr_o; |
output [`TC_BSW-1:0] t3_wb_sel_o; |
output t3_wb_we_o; |
output [`TC_DW-1:0] t3_wb_dat_o; |
input [`TC_DW-1:0] t3_wb_dat_i; |
input t3_wb_ack_i; |
input t3_wb_err_i; |
|
// |
// WB master i/f connecting target 4 |
// |
output t4_wb_cyc_o; |
output t4_wb_stb_o; |
output [`TC_AW-1:0] t4_wb_adr_o; |
output [`TC_BSW-1:0] t4_wb_sel_o; |
output t4_wb_we_o; |
output [`TC_DW-1:0] t4_wb_dat_o; |
input [`TC_DW-1:0] t4_wb_dat_i; |
input t4_wb_ack_i; |
input t4_wb_err_i; |
|
// |
// WB master i/f connecting target 5 |
// |
output t5_wb_cyc_o; |
output t5_wb_stb_o; |
output [`TC_AW-1:0] t5_wb_adr_o; |
output [`TC_BSW-1:0] t5_wb_sel_o; |
output t5_wb_we_o; |
output [`TC_DW-1:0] t5_wb_dat_o; |
input [`TC_DW-1:0] t5_wb_dat_i; |
input t5_wb_ack_i; |
input t5_wb_err_i; |
|
// |
// WB master i/f connecting target 6 |
// |
output t6_wb_cyc_o; |
output t6_wb_stb_o; |
output [`TC_AW-1:0] t6_wb_adr_o; |
output [`TC_BSW-1:0] t6_wb_sel_o; |
output t6_wb_we_o; |
output [`TC_DW-1:0] t6_wb_dat_o; |
input [`TC_DW-1:0] t6_wb_dat_i; |
input t6_wb_ack_i; |
input t6_wb_err_i; |
|
// |
// WB master i/f connecting target 7 |
// |
output t7_wb_cyc_o; |
output t7_wb_stb_o; |
output [`TC_AW-1:0] t7_wb_adr_o; |
output [`TC_BSW-1:0] t7_wb_sel_o; |
output t7_wb_we_o; |
output [`TC_DW-1:0] t7_wb_dat_o; |
input [`TC_DW-1:0] t7_wb_dat_i; |
input t7_wb_ack_i; |
input t7_wb_err_i; |
|
// |
// Internal wires & registers |
// |
wire [`TC_IIN_W-1:0] i0_in; |
wire [`TC_TIN_W-1:0] i0_out; |
wire [`TC_IIN_W-1:0] t0_out, t1_out, |
t2_out, t3_out, |
t4_out, t5_out, |
t6_out, t7_out; |
wire [`TC_TIN_W-1:0] t0_in, t1_in, |
t2_in, t3_in, |
t4_in, t5_in, |
t6_in, t7_in; |
wire [7:0] req_t; |
|
// |
// Group WB initiator 0 i/f inputs and outputs |
// |
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, |
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; |
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; |
|
// |
// Group WB target 0 i/f inputs and outputs |
// |
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, |
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; |
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; |
|
// |
// Group WB target 1 i/f inputs and outputs |
// |
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, |
t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out; |
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; |
|
// |
// Group WB target 2 i/f inputs and outputs |
// |
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, |
t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out; |
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; |
|
// |
// Group WB target 3 i/f inputs and outputs |
// |
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, |
t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out; |
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; |
|
// |
// Group WB target 4 i/f inputs and outputs |
// |
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, |
t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out; |
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; |
|
// |
// Group WB target 5 i/f inputs and outputs |
// |
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, |
t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out; |
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; |
|
// |
// Group WB target 6 i/f inputs and outputs |
// |
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, |
t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out; |
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; |
|
// |
// Group WB target 7 i/f inputs and outputs |
// |
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, |
t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out; |
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; |
|
// |
// Assign to WB target i/f outputs |
// |
// Either inputs from the initiator are assigned or zeros. |
// |
assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; |
assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; |
|
// |
// Assign to WB initiator i/f outputs |
// |
// Assign inputs from target to initiator outputs according to |
// which target is accessed. If there is no request for a target, |
// assign zeros. |
// |
assign i0_out = req_t[0] ? t0_in : |
req_t[1] ? t1_in : |
req_t[2] ? t2_in : |
req_t[3] ? t3_in : |
req_t[4] ? t4_in : |
req_t[5] ? t5_in : |
req_t[6] ? t6_in : |
req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; |
|
// |
// Determine which target is being accessed. |
// |
assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); |
assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); |
assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); |
assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); |
assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); |
assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); |
assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); |
assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); |
|
endmodule |
soc_maker/trunk/core_lib/cores/wb_connect/minsoc_tc_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: soc_maker/trunk/core_lib/cores/or1200_rel2/01_or1200.yaml
===================================================================
--- soc_maker/trunk/core_lib/cores/or1200_rel2/01_or1200.yaml (nonexistent)
+++ soc_maker/trunk/core_lib/cores/or1200_rel2/01_or1200.yaml (revision 5)
@@ -0,0 +1,196 @@
+SOCM_CORE
+name: or1200
+description: OpenRISC CPU
+version: rel2
+license: LGPL
+licensefile:
+author:
+authormail:
+vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl
+toplevel: or1200_top
+interfaces:
+ :clmode: SOCM_IFC
+ name: single
+ dir: 1
+ version: "1"
+ ports:
+ :clmode_i: SOCM_PORT
+ len: 2
+ defn: single
+
+ :pic_inst: SOCM_IFC
+ name: single
+ dir: 1
+ version: "1"
+ ports:
+ :pic_inst_i: SOCM_PORT
+ len: 2
+ defn: single
+
+ :clk: SOCM_IFC
+ name: clk
+ dir: 1
+ version: "1"
+ ports:
+ :clk_i: SOCM_PORT
+ len: 2
+ defn: clk
+
+ :rst: SOCM_IFC
+ name: rst
+ dir: 1
+ version: "1"
+ ports:
+ :rst_i: SOCM_PORT
+ len: 2
+ defn: rst
+
+ :wb_instruction: SOCM_IFC
+ name: wishbone_ma
+ dir: 1
+ version: "b3"
+ ports:
+ :iwb_cyc_o: SOCM_PORT
+ defn: cyc
+ len: 1
+ :iwb_stb_o: SOCM_PORT
+ defn: stb
+ len: 1
+ :iwb_adr_o: SOCM_PORT
+ defn: adr
+ len: 32
+ :iwb_sel_o: SOCM_PORT
+ defn: sel
+ len: 1
+ :iwb_we_o: SOCM_PORT
+ defn: we
+ len: 1
+ :iwb_dat_o: SOCM_PORT
+ defn: dat_i
+ len: 32
+ :iwb_dat_i: SOCM_PORT
+ defn: dat_o
+ len: 32
+ :iwb_ack_i: SOCM_PORT
+ defn: ack
+ len: 1
+ :iwb_err_i: SOCM_PORT
+ defn: err
+ len: 1
+ :iwb_rty_i: SOCM_PORT
+ defn: err
+ len: 1
+
+ :wb_data: SOCM_IFC
+ name: wishbone_ma
+ dir: 1
+ version: "b3"
+ ports:
+ :dwb_cyc_o: SOCM_PORT
+ defn: cyc
+ len: 1
+ :dwb_stb_o: SOCM_PORT
+ defn: stb
+ len: 1
+ :dwb_adr_o: SOCM_PORT
+ defn: adr
+ len: 32
+ :dwb_sel_o: SOCM_PORT
+ defn: sel
+ len: 1
+ :dwb_we_o: SOCM_PORT
+ defn: we
+ len: 1
+ :dwb_dat_o: SOCM_PORT
+ defn: dat_i
+ len: 32
+ :dwb_dat_i: SOCM_PORT
+ defn: dat_i
+ len: 32
+ :dwb_ack_i: SOCM_PORT
+ defn: ack
+ len: 1
+ :dwb_err_i: SOCM_PORT
+ defn: err
+ len: 1
+ :dwb_rty_i: SOCM_PORT
+ defn: err
+ len: 1
+
+ :ext_debug: SOCM_IFC
+ name: debug
+ dir: 1
+ version: "1"
+ ports:
+ :dbg_stall_i: SOCM_PORT
+ defn: dbg_stall
+ len: 1
+ :dbg_ewt_i: SOCM_PORT
+ len: 1
+ defn: dbg_ewt
+ :dbg_lss_o: SOCM_PORT
+ len: 4
+ defn: dbg_lss
+ :dbg_is_o: SOCM_PORT
+ len: 2
+ defn: dbg_iso
+ :dbg_wp_o: SOCM_PORT
+ len: 11
+ defn: dbg_wpo
+ :dbg_bp_o: SOCM_PORT
+ len: 1
+ defn: dbg_bpo
+ :dbg_stb_i: SOCM_PORT
+ len: 1
+ defn: dbg_stb
+ :dbg_we_i: SOCM_PORT
+ len: 1
+ defn: dbg_we
+ :dbg_adr_i: SOCM_PORT
+ len: 32
+ defn: dbg_adr
+ :dbg_dat_i: SOCM_PORT
+ len: 32
+ defn: dbg_dat
+ :dbg_dat_o: SOCM_PORT
+ len: 32
+ defn: dbg_dat
+ :dbg_ack_o: SOCM_PORT
+ len: 1
+ defn: dbg_ack
+
+ :pow_man: SOCM_IFC
+ name: or_power_management
+ dir: 1
+ version: "1"
+ ports:
+ :pm_cpustall_i: SOCM_PORT
+ len: 1
+ defn: pm_cpustall
+ :pm_clksd_o: SOCM_PORT
+ len: 4
+ defn: pm_clksd
+ :pm_dc_gate_o: SOCM_PORT
+ len: 1
+ defn: pm_dc_gate
+ :pm_ic_gate_o: SOCM_PORT
+ len: 1
+ defn: pm_ic_gate
+ :pm_dmmu_gate_o: SOCM_PORT
+ len: 1
+ defn: pm_dmmu_gate
+ :pm_immu_gate_o: SOCM_PORT
+ len: 1
+ defn: pm_immu_gate
+ :pm_tt_gate_o: SOCM_PORT
+ len: 1
+ defn: pm_tt_gate
+ :pm_cpu_gate_o: SOCM_PORT
+ len: 1
+ defn: pm_cpu_gate
+ :pm_wakeup_o: SOCM_PORT
+ len: 1
+ defn: pm_wakeup
+ :pm_lvolt_o: SOCM_PORT
+ len: 1
+ defn: pm_lvolt
Index: soc_maker/trunk/core_lib/cores/or1200_rel2/02_or1200_files.yaml
===================================================================
--- soc_maker/trunk/core_lib/cores/or1200_rel2/02_or1200_files.yaml (nonexistent)
+++ soc_maker/trunk/core_lib/cores/or1200_rel2/02_or1200_files.yaml (revision 5)
@@ -0,0 +1,418 @@
+hdlfiles:
+ :alu: SOCM_HDL_FILE
+ use_syn: true
+ use_sim: true
+ type: verilog
+ path: rtl/verilog/or1200_alu.v
+
+ :tlb: SOCM_HDL_FILE
+ use_syn: true
+ use_sim: true
+ type: verilog
+ path: rtl/verilog/or1200_dmmu_tlb.v
+
+ :ram: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_ic_ram.v
+
+ :operandmuxes: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_operandmuxes.v
+
+ :spram_1024: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_1024x32.v
+
+ :spram_64_22: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_64x22.v
+
+ :amultp2: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_amultp2_32x32.v
+
+ :dmmu_top: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dmmu_top.v
+
+ :ic_tag: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_ic_tag.v
+
+ :pic: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_pic.v
+
+ :spram_1024_8: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_1024x8.v
+
+ :spram_64_24: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_64x24.v
+
+ :cfgr: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_cfgr.v
+
+ :dpram_256_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dpram_256x32.v
+
+ :ic_top: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_ic_top.v
+
+ :pm: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_pm.v
+
+ :spram_128_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_128x32.v
+
+ :sprs: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_sprs.v
+
+ :cpu: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_cpu.v
+
+ :dpram_32_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dpram_32x32.v
+
+ :if: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_if.v
+
+ :qmem_top: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_qmem_top.v
+
+ :spram_2048_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_2048x32_bw.v
+
+ :top: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_top.v
+
+ :or1200_ctrl: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_ctrl.v
+
+ :du: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_du.v
+
+ :immu_tlb: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_immu_tlb.v
+
+ :reg2mem: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_reg2mem.v
+
+ :spram_2048_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_2048x32.v
+
+ :tpram_32_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_tpram_32x32.v
+
+ :dc_fsm: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dc_fsm.v
+
+ :except: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_except.v
+
+ :immu_top: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_immu_top.v
+
+ :rfram_generic: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_rfram_generic.v
+
+ :spram_2048_8: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_2048x8.v
+
+ :tt: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_tt.v
+
+ :dc_ram: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dc_ram.v
+
+ :freeze: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_freeze.v
+
+ :iwb_biu: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_iwb_biu.v
+
+ :rf: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_rf.v
+
+ :spram_256_21: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_256x21.v
+
+ :wb_biu: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_wb_biu.v
+
+ :dc_tag: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dc_tag.v
+
+ :genpc: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_genpc.v
+
+ :lsu: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_lsu.v
+
+ :fifo: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_sb_fifo.v
+
+ :spram_32_24: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_32x24.v
+
+ :wbmux: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_wbmux.v
+
+ :dc_top: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_dc_top.v
+
+ :gmultp2_32_32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_gmultp2_32x32.v
+
+ :mem2reg: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_mem2reg.v
+
+ :sb: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_sb.v
+
+ :spram_512_20: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_512x20.v
+
+ :xcv_ram32_8d: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_xcv_ram32x8d.v
+
+ :defines: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_defines.v
+
+ :ic_fsm: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_ic_fsm.v
+
+ :mult_mac: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_mult_mac.v
+
+ :spram_2014x32: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_1024x32_bw.v
+
+ :spram_64_14: SOCM_HDL_FILE
+ use_syn: true
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/or1200_spram_64x14.v
+
+ :timescale: SOCM_HDL_FILE
+ use_syn: false
+ use_sys_sim: true
+ use_mod_sim: true
+ type: vhdl
+ path: rtl/verilog/timescale.v