URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
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- This comparison shows the changes necessary to convert path
/
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v
0,0 → 1,95
module port_ring_tap_fsm |
#(parameter rdp_sz = 64, |
parameter portnum = 0) |
( |
input clk, |
input reset, |
|
output reg lfli_drdy, |
output reg lprx_drdy, |
output reg[rdp_sz-1:0] lptx_data, |
output reg lptx_srdy, |
output reg lri_drdy, |
output reg[rdp_sz-1:0] lro_data, |
output reg lro_srdy, |
|
input [rdp_sz-1:0] lfli_data, |
input lfli_srdy, |
input [rdp_sz-1:0] lprx_data, |
input lprx_srdy, |
input lptx_drdy, |
input [rdp_sz-1:0] lri_data, |
input lri_srdy, |
input lro_drdy |
// End of automatics |
); |
|
reg [6:0] state, nxt_state; |
|
wire [`NUM_PORTS-1:0] port_mask; |
reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec; |
|
assign port_mask = 1 << portnum; |
|
parameter s_idle = 0, |
s_rcmd = 1, |
s_rfwd = 2, |
s_rcopy = 3, |
s_rsink = 4, |
s_tcmd = 5, |
s_tdata = 6; |
|
always @* |
begin |
lro_data = lri_data; |
|
case (1'b1) |
state[s_idle] : |
begin |
if (lfli_srdy) |
begin |
end |
else if (lri_srdy) |
begin |
if (lri_data[`PRW_DATA] & port_mask) |
begin |
// packet is for our port |
nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask; |
|
// if enable vector is not empty, send the |
// vector to the next port |
if ((nxt_pe_vec != 0) & lro_drdy) |
begin |
lro_data[`PRW_DATA] = nxt_pe_vec; |
lro_data[`PRW_PVEC] = 1; |
lro_srdy = 1; |
lri_drdy = 1; |
nxt_state = ns_rcopy; |
end |
else |
begin |
lri_drdy = 1; |
nxt_state = ns_rsink; |
end // else: !if((nxt_pe_vec != 0) & lro_drdy) |
end // if (lri_data[`PRW_DATA] & port_mask) |
else |
// packet is not for our port, forward it on the |
// ring |
begin |
if (lro_drdy) |
begin |
lri_drdy = 1; |
lro_srdy = 1; |
nxt_state = ns_rfwd; |
end |
end // else: !if(lri_data[`PRW_DATA] & port_mask) |
end // if (lri_srdy) |
end // case: state[s_idle] |
|
default : nxt_state = ns_idle; |
endcase // case (1'b1) |
end // always @ * |
|
|
|
endmodule // port_ring_tap_fsm |
/srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup_fsm.v
1,7 → 1,8
module fib_lookup_fsm |
(/*AUTOARG*/ |
// Outputs |
lpp_drdy, ft_wdata, ft_rd_n, ft_wr_n, ft_addr, lout_data, lout_srdy, |
lpp_drdy, ft_wdata, ft_rd_en, ft_wr_en, ft_addr, lout_data, |
lout_srdy, lout_dst_vld, |
// Inputs |
clk, reset, lpp_data, lpp_srdy, ft_rdata, lout_drdy |
); |
14,12 → 15,13
|
input [`FIB_ENTRY_SZ-1:0] ft_rdata; |
output reg [`FIB_ENTRY_SZ-1:0] ft_wdata; |
output reg ft_rd_n, ft_wr_n; |
output reg ft_rd_en, ft_wr_en; |
output reg [`FIB_ASZ-1:0] ft_addr; |
|
output reg [`NUM_PORTS-1:0] lout_data; |
output reg lout_srdy; |
input lout_drdy; |
output [`NUM_PORTS-1:0] lout_dst_vld; |
|
wire [`FIB_ASZ-1:0] hf_out; |
reg [47:0] hf_in; |
42,13 → 44,16
s_init0 = 3, s_init1 = 4; |
localparam ns_idle = 1, ns_da_lookup = 2, ns_sa_lookup = 4, |
ns_init0 = 8, ns_init1 = 16; |
|
// send all results back to their originating port |
assign lout_dst_vld = source_port_mask; |
|
always @* |
begin |
hf_in = 0; |
nxt_state = state; |
ft_rd_n = 1; |
ft_wr_n = 1; |
ft_rd_en = 0; |
ft_wr_en = 0; |
ft_addr = hf_out; |
lout_data = 0; |
lout_srdy = 0; |
70,7 → 75,7
else if (lpp_srdy) |
begin |
hf_in = lpp_data[`PAR_MACDA]; |
ft_rd_n = 0; |
ft_rd_en = 1; |
nxt_state = ns_da_lookup; |
end |
end |
99,7 → 104,7
// will bump out current occupant and update |
state[s_sa_lookup] : |
begin |
ft_wr_n = 0; |
ft_wr_en = 1; |
hf_in = lpp_data[`PAR_MACSA]; |
ft_wdata[`FIB_MACADDR] = lpp_data[`PAR_MACSA]; |
ft_wdata[`FIB_AGE] = `FIB_MAX_AGE; |
117,7 → 122,7
state[s_init1] : |
begin |
nxt_init_ctr = init_ctr + 1; |
ft_wr_n = 0; |
ft_wr_en = 1; |
ft_addr = init_ctr; |
ft_wdata = 0; |
if (ft_addr == (`FIB_ENTRIES-1)) |
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge.vh
25,4 → 25,18
|
`define FIB_MAX_AGE 255 // maximum value of age timer |
|
`define MULTICAST 48'h0100000000 // multicast bit |
`define MULTICAST 48'h0100000000 // multicast bit |
|
// Packet control codes |
`define PCC_SOP 2'b01 // Start of packet |
`define PCC_DATA 2'b00 // data word |
`define PCC_EOP 2'b10 // End of packet |
`define PCC_BADEOP 2'b11 // End of packet w/ error |
|
// Packet Ring Word |
|
`define PRW_SZ 70 |
`define PRW_DATA 63:0 // 64 bits of packet data |
`define PRW_PCC 65:64 // packet control code |
`define PRW_VALID 68:66 // # of valid bytes modulo 8 |
`define PRW_PVEC 69 // indicates this is port vector word |
/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap.v
0,0 → 1,116
// Inputs are ri (Ring In), ro (Ring Out), |
// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX) |
|
module port_ring_tap |
#(parameter rdp_sz = 64, |
parameter portnum = 0) |
( |
input clk, |
input reset, |
|
input ri_srdy, |
output ri_drdy, |
input [rdp_sz-1:0] ri_data, |
|
input prx_srdy, |
output prx_drdy, |
input [rdp_sz-1:0] prx_data, |
|
output ro_srdy, |
input ro_drdy, |
output [rdp_sz-1:0] ro_data, |
|
output ptx_srdy, |
input ptx_drdy, |
output [rdp_sz-1:0] ptx_data, |
|
input fli_srdy, |
output fli_drdy, |
input [`NUM_PORTS-1:0] fli_data |
); |
|
/*AUTOWIRE*/ |
|
/* sd_input AUTO_TEMPLATE "tc_\(.*\)" |
( |
.c_\(.*\) (@_\1[]), |
.ip_\(.*\) (l@_\1[]), |
); |
*/ |
|
sd_input #(rdp_sz) tc_ri |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (ri_drdy), // Templated |
.ip_srdy (lri_srdy), // Templated |
.ip_data (lri_data[width-1:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (ri_srdy), // Templated |
.c_data (ri_data[width-1:0]), // Templated |
.ip_drdy (lri_drdy)); // Templated |
|
sd_input #(rdp_sz) tc_prx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (prx_drdy), // Templated |
.ip_srdy (lprx_srdy), // Templated |
.ip_data (lprx_data[width-1:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (prx_srdy), // Templated |
.c_data (prx_data[width-1:0]), // Templated |
.ip_drdy (lprx_drdy)); // Templated |
|
sd_input #(`NUM_PORTS) tc_fli |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (fli_drdy), // Templated |
.ip_srdy (lfli_srdy), // Templated |
.ip_data (lfli_data[width-1:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (fli_srdy), // Templated |
.c_data (fli_data[width-1:0]), // Templated |
.ip_drdy (lfli_drdy)); // Templated |
|
/* sd_output AUTO_TEMPLATE "tc_\(.*\)" |
( |
.ic_\(.*\) (l@_\1[]), |
.p_\(.*\) (@_\1[]), |
); |
*/ |
|
sd_output #(rdp_sz) tc_ptx |
(/*AUTOINST*/ |
// Outputs |
.ic_drdy (lptx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data[width-1:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_srdy (lptx_srdy), // Templated |
.ic_data (lptx_data[width-1:0]), // Templated |
.p_drdy (ptx_drdy)); // Templated |
|
sd_output #(rdp_sz) tc_ro |
(/*AUTOINST*/ |
// Outputs |
.ic_drdy (lro_drdy), // Templated |
.p_srdy (ro_srdy), // Templated |
.p_data (ro_data[width-1:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_srdy (lro_srdy), // Templated |
.ic_data (lro_data[width-1:0]), // Templated |
.p_drdy (ro_drdy)); // Templated |
|
endmodule // port_ring_tap |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks") |
// End: |
/srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup.v
30,11 → 30,12
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [`FIB_ASZ-1:0] ft_addr; // From fsm0 of fib_lookup_fsm.v |
wire ft_rd_n; // From fsm0 of fib_lookup_fsm.v |
wire ft_rd_en; // From fsm0 of fib_lookup_fsm.v |
wire [`FIB_ENTRY_SZ-1:0] ft_wdata; // From fsm0 of fib_lookup_fsm.v |
wire ft_wr_n; // From fsm0 of fib_lookup_fsm.v |
wire ft_wr_en; // From fsm0 of fib_lookup_fsm.v |
wire [`NUM_PORTS-1:0] lout_data; // From fsm0 of fib_lookup_fsm.v |
wire lout_drdy; // From fib_res_out of sd_mirror.v |
wire [`NUM_PORTS-1:0] lout_dst_vld; // From fsm0 of fib_lookup_fsm.v |
wire lout_srdy; // From fsm0 of fib_lookup_fsm.v |
wire lpp_drdy; // From fsm0 of fib_lookup_fsm.v |
wire lpp_srdy; // From port_parse_in of sd_input.v |
72,8 → 73,8
// Outputs |
.d_out (ft_rdata), // Templated |
// Inputs |
.wr_n (ft_wr_n), // Templated |
.rd_n (ft_rd_n), // Templated |
.wr_en (ft_wr_en), // Templated |
.rd_en (ft_rd_en), // Templated |
.clk (clk), // Templated |
.d_in (ft_wdata), // Templated |
.addr (ft_addr)); // Templated |
83,11 → 84,12
// Outputs |
.lpp_drdy (lpp_drdy), |
.ft_wdata (ft_wdata[`FIB_ENTRY_SZ-1:0]), |
.ft_rd_n (ft_rd_n), |
.ft_wr_n (ft_wr_n), |
.ft_rd_en (ft_rd_en), |
.ft_wr_en (ft_wr_en), |
.ft_addr (ft_addr[`FIB_ASZ-1:0]), |
.lout_data (lout_data[`NUM_PORTS-1:0]), |
.lout_srdy (lout_srdy), |
.lout_dst_vld (lout_dst_vld[`NUM_PORTS-1:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
113,6 → 115,10
.reset (reset), |
.c_srdy (lout_srdy), // Templated |
.c_data (lout_data), // Templated |
.c_dst_vld (lout_dst_vld), // Templated |
.p_drdy (flo_drdy)); // Templated |
|
endmodule // fib_lookup |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks") |
// End: |