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Rev 4 → Rev 5

/trunk/rtl/verilog/usb1_top.v File deleted
/trunk/rtl/verilog/usb1_fifo.v File deleted
/trunk/rtl/verilog/usb1_ep.v File deleted
/trunk/rtl/verilog/usb1_ep_out.v File deleted
/trunk/rtl/verilog/usb1_ep_in.v File deleted
/trunk/rtl/verilog/usb1_pd.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usb1_pd.v,v 1.1.1.1 2002-09-19 12:07:17 rudi Exp $
// $Id: usb1_pd.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
//
// $Date: 2002-09-19 12:07:17 $
// $Revision: 1.1.1.1 $
// $Date: 2002-09-25 06:06:49 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/09/19 12:07:17 rudi
// Initial Checkin
//
//
//
55,6 → 57,7
//
//
//
//
 
`include "usb1_defines.v"
 
78,7 → 81,7
rx_data_st, rx_data_valid, rx_data_done, crc16_err,
 
// Misc.
seq_err
seq_err, rx_busy
);
 
input clk, rst;
107,6 → 110,7
output crc16_err; // Data packet CRC 16 error
 
output seq_err; // State Machine Sequence Error
output rx_busy; // Receivig Data Packet
 
///////////////////////////////////////////////////////////////////
//
166,6 → 170,18
// Misc Logic
//
 
reg rx_busy, rx_busy_d;
 
always @(posedge clk or negedge rst)
if(!rst) rx_busy_d <= #1 1'b0;
else
if(rx_valid & (state == DATA)) rx_busy_d <= #1 1'b1;
else
if(state != DATA) rx_busy_d <= #1 1'b0;
 
always @(posedge clk)
rx_busy <= #1 rx_busy_d;
 
// PID Decoding Logic
assign pid_ld_en = pid_le_sm & rx_active & rx_valid;
 
/trunk/rtl/verilog/usb1_ctrl.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usb1_ctrl.v,v 1.1.1.1 2002-09-19 12:07:09 rudi Exp $
// $Id: usb1_ctrl.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
//
// $Date: 2002-09-19 12:07:09 $
// $Revision: 1.1.1.1 $
// $Date: 2002-09-25 06:06:49 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,16 → 48,21
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/09/19 12:07:09 rudi
// Initial Checkin
//
//
//
//
//
//
 
`include "usb1_defines.v"
 
module usb1_ctrl( clk, rst,
 
rom_adr, rom_data,
 
ctrl_setup, ctrl_in, ctrl_out,
 
ep0_din, ep0_dout, ep0_re, ep0_we, ep0_stat,
71,6 → 76,9
 
input clk, rst;
 
output [6:0] rom_adr;
input [7:0] rom_data;
 
input ctrl_setup;
input ctrl_in;
input ctrl_out;
172,10 → 180,10
wire set_halt=0; // FIX_ME
 
// For this implementation we do not implement HALT for the
// device nor for any of the endpoints. This is is useless for
// device nor for any of the endpoints. This is useless for
// this device, but can be added here later ...
// FYI, we report device/endpoint errors via interrupts,
// instead of halting the entire or paret of the device, much
// instead of halting the entire or part of the device, much
// nicer for non-critical errors.
 
assign clr_halt = ctrl_setup;
202,7 → 210,6
// Descriptor ROM
//
reg [6:0] rom_adr;
wire [7:0] rom_dout;
reg rom_sel, rom_sel_r;
wire rom_done;
reg [6:0] rom_size;
210,40 → 217,20
reg fifo_we_rom_r2;
wire fifo_we_rom;
reg [7:0] rom_start_d;
 
reg [6:0] rom_size_dd;
wire [6:0] rom_size_d;
 
parameter ROM_SIZE0 = 7'd018,
ROM_SIZE1 = 7'd053,
ROM_SIZE2A = 7'd004,
ROM_SIZE2B = 7'd010,
ROM_SIZE2C = 7'd010,
ROM_SIZE2D = 7'd010;
 
parameter ROM_START0 = 7'h00,
ROM_START1 = 7'h12,
ROM_START2A = 7'h47,
ROM_START2B = 7'h50,
ROM_START2C = 7'h60,
ROM_START2D = 7'h70;
 
usb1_rom1 rom1( .clk( clk ),
.adr( rom_adr ),
.dout( rom_dout )
);
 
always @(wValue)
case(wValue[11:8]) // synopsys full_case parallel_case
4'h1: rom_start_d = ROM_START0;
4'h2: rom_start_d = ROM_START1;
4'h1: rom_start_d = `ROM_START0;
4'h2: rom_start_d = `ROM_START1;
4'h3:
case(wValue[3:0]) // synopsys full_case parallel_case
4'h00: rom_start_d = ROM_START2A;
4'h01: rom_start_d = ROM_START2B;
4'h02: rom_start_d = ROM_START2C;
4'h03: rom_start_d = ROM_START2D;
default: rom_start_d = ROM_START2A;
4'h00: rom_start_d = `ROM_START2A;
4'h01: rom_start_d = `ROM_START2B;
4'h02: rom_start_d = `ROM_START2C;
4'h03: rom_start_d = `ROM_START2D;
default: rom_start_d = `ROM_START2A;
endcase
default: rom_start_d = 7'h00;
endcase
250,15 → 237,15
 
always @(wValue)
case(wValue[11:8]) // synopsys full_case parallel_case
4'h1: rom_size_dd = ROM_SIZE0;
4'h2: rom_size_dd = ROM_SIZE1;
4'h1: rom_size_dd = `ROM_SIZE0;
4'h2: rom_size_dd = `ROM_SIZE1;
4'h3:
case(wValue[3:0]) // synopsys full_case parallel_case
4'h00: rom_size_dd = ROM_SIZE2A;
4'h01: rom_size_dd = ROM_SIZE2B;
4'h02: rom_size_dd = ROM_SIZE2C;
4'h03: rom_size_dd = ROM_SIZE2D;
default: rom_size_dd = ROM_SIZE2A;
4'h00: rom_size_dd = `ROM_SIZE2A;
4'h01: rom_size_dd = `ROM_SIZE2B;
4'h02: rom_size_dd = `ROM_SIZE2C;
4'h03: rom_size_dd = `ROM_SIZE2D;
default: rom_size_dd = `ROM_SIZE2A;
endcase
default: rom_size_dd = 7'h01;
endcase
351,7 → 338,7
 
always @(posedge clk)
case(data_sel) // synopsys full_case parallel_case
ZERO_DATA: ep0_dout <= #1 rom_sel ? rom_dout : 8'h0;
ZERO_DATA: ep0_dout <= #1 rom_sel ? rom_data : 8'h0;
ZERO_ONE_DATA: ep0_dout <= #1 high_sel ? 8'h1 : 8'h0;
CONFIG_DATA: ep0_dout <= #1 {7'h0, configured}; // return configuration
SYNC_FRAME_DATA: ep0_dout <= #1 high_sel ? {5'h0, frame_no[10:8]} : frame_no[7:0];
372,10 → 359,12
 
 
always @(posedge clk)
write_done_r <= #1 in_size_2 & !fifo_full & fifo_we_d & !write_done_r & !write_done;
write_done_r <= #1 in_size_2 & !fifo_full & fifo_we_d &
!write_done_r & !write_done;
 
always @(posedge clk)
write_done <= #1 in_size_2 & !fifo_full & fifo_we_d & write_done_r & !write_done;
write_done <= #1 in_size_2 & !fifo_full & fifo_we_d &
write_done_r & !write_done;
 
///////////////////////////////////////////////////////////////////
//
399,7 → 388,7
 
assign bmReqType = hdr0;
assign bm_req_dir = bmReqType[7]; // 0-Host to device; 1-device to host
assign bm_req_dir = bmReqType[7]; // 0-Host to device; 1-device to host
assign bm_req_type = bmReqType[6:5]; // 0-standard; 1-class; 2-vendor; 3-RESERVED
assign bm_req_recp = bmReqType[4:0]; // 0-device; 1-interface; 2-endpoint; 3-other
// 4..31-reserved
411,47 → 400,62
always @(posedge clk)
hdr_done_r <= #1 hdr_done;
 
// Standard commands that MUST support
always @(posedge clk)
get_status <= #1 hdr_done & (bRequest == GET_STATUS) & (bm_req_type==2'h0);
get_status <= #1 hdr_done & (bRequest == GET_STATUS) &
(bm_req_type==2'h0);
 
always @(posedge clk)
clear_feature <= #1 hdr_done & (bRequest == CLEAR_FEATURE) & (bm_req_type==2'h0);
clear_feature <= #1 hdr_done & (bRequest == CLEAR_FEATURE) &
(bm_req_type==2'h0);
 
always @(posedge clk)
set_feature <= #1 hdr_done & (bRequest == SET_FEATURE) & (bm_req_type==2'h0);
set_feature <= #1 hdr_done & (bRequest == SET_FEATURE) &
(bm_req_type==2'h0);
 
always @(posedge clk)
set_address <= #1 hdr_done & (bRequest == SET_ADDRESS) & (bm_req_type==2'h0);
set_address <= #1 hdr_done & (bRequest == SET_ADDRESS) &
(bm_req_type==2'h0);
 
always @(posedge clk)
get_descriptor <= #1 hdr_done & (bRequest == GET_DESCRIPTOR) & (bm_req_type==2'h0);
get_descriptor <= #1 hdr_done & (bRequest == GET_DESCRIPTOR) &
(bm_req_type==2'h0);
 
always @(posedge clk)
set_descriptor <= #1 hdr_done & (bRequest == SET_DESCRIPTOR) & (bm_req_type==2'h0);
set_descriptor <= #1 hdr_done & (bRequest == SET_DESCRIPTOR) &
(bm_req_type==2'h0);
 
always @(posedge clk)
get_config <= #1 hdr_done & (bRequest == GET_CONFIG) & (bm_req_type==2'h0);
get_config <= #1 hdr_done & (bRequest == GET_CONFIG) &
(bm_req_type==2'h0);
 
always @(posedge clk)
set_config <= #1 hdr_done & (bRequest == SET_CONFIG) & (bm_req_type==2'h0);
set_config <= #1 hdr_done & (bRequest == SET_CONFIG) &
(bm_req_type==2'h0);
 
always @(posedge clk)
get_interface <= #1 hdr_done & (bRequest == GET_INTERFACE) & (bm_req_type==2'h0);
get_interface <= #1 hdr_done & (bRequest == GET_INTERFACE) &
(bm_req_type==2'h0);
 
always @(posedge clk)
set_interface <= #1 hdr_done & (bRequest == SET_INTERFACE) & (bm_req_type==2'h0);
set_interface <= #1 hdr_done & (bRequest == SET_INTERFACE) &
(bm_req_type==2'h0);
 
always @(posedge clk)
synch_frame <= #1 hdr_done & (bRequest == SYNCH_FRAME) & (bm_req_type==2'h0);
synch_frame <= #1 hdr_done & (bRequest == SYNCH_FRAME) &
(bm_req_type==2'h0);
 
always @(posedge clk)
v_set_int <= #1 hdr_done & (bRequest == V_SET_INT) & (bm_req_type==2'h2);
v_set_int <= #1 hdr_done & (bRequest == V_SET_INT) &
(bm_req_type==2'h2);
 
always @(posedge clk)
v_set_feature <= #1 hdr_done & (bRequest == SET_FEATURE) & (bm_req_type==2'h2);
v_set_feature <= #1 hdr_done & (bRequest == SET_FEATURE) &
(bm_req_type==2'h2);
 
always @(posedge clk)
v_get_status <= #1 hdr_done & (bRequest == GET_STATUS) & (bm_req_type==2'h2);
v_get_status <= #1 hdr_done & (bRequest == GET_STATUS) &
(bm_req_type==2'h2);
 
// A config err must cause the device to send a STALL for an ACK
always @(posedge clk)
461,7 → 465,6
get_interface | set_interface | synch_frame |
v_set_int | v_set_feature | v_get_status);
 
 
always @(posedge clk)
send_stall <= #1 config_err;
 
606,7 → 609,7
SET_DESCRIPTOR_S:
begin
// This doesn't do anything since we do not support
// seting the descriptor
// setting the descriptor
next_state = IDLE;
end
 
/trunk/rtl/verilog/usb1_core.v
0,0 → 1,620
/////////////////////////////////////////////////////////////////////
//// ////
//// USB 1.1 function IP core ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: usb1_core.v,v 1.1 2002-09-25 06:06:49 rudi Exp $
//
// $Date: 2002-09-25 06:06:49 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
//
//
 
`include "usb1_defines.v"
 
/*
 
// USB PHY Interface
tx_dp, tx_dn, tx_oe,
rx_d, rx_dp, rx_dn,
These pins are a semi-standard interface to USB 1.1 transceivers.
Just match up the signal names with the IOs of the transceiver.
 
// USB Misc
phy_tx_mode, usb_rst,
The PHY supports single ended and differential output to the
transceiver Depending on which device you are using, you have
to tie the phy_tx_mode high or low.
usb_rst is asserted whenever the host signals reset on the USB
bus. The USB core will internally reset itself automatically.
This output is provided for external logic that needs to be
reset when the USB bus is reset.
 
// Interrupts
dropped_frame, misaligned_frame,
crc16_err,
dropped_frame, misaligned_frame are interrupt to indicate error
conditions in Block Frame mode.
crc16_err, indicates when a crc 16 error was detected on the
payload of a USB packet.
 
// Vendor Features
v_set_int, v_set_feature, wValue,
wIndex, vendor_data,
This signals allow to control vendor specific registers and logic
that can be manipulated and monitored via the control endpoint
through vendor defined commands.
 
// USB Status
usb_busy, ep_sel,
usb_busy is asserted when the USB core is busy transferring
data ep_sel indicated the endpoint that is currently busy.
This information might be useful if one desires to reset/clear
the attached FIFOs and want to do this when the endpoint is idle.
 
// Endpoint Interface
This implementation supports 8 endpoints. Endpoint 0 is the
control endpoint and used internally. Endpoints 1-7 are available
to the user. replace 'N' with the endpoint number.
 
epN_cfg,
This is a constant input used to configure the endpoint by ORing
these defines together and adding the max packet size for this
endpoint:
`IN and `OUT select the transfer direction for this endpoint
`ISO, `BULK and `INT determine the endpoint type
 
Example: "`BULK | `IN | 14'd064" defines a BULK IN endpoint with
max packet size of 64 bytes
 
epN_din, epN_we, epN_full,
This is the OUT FIFO interface. If this is a IN endpoint, ground
all unused inputs and leave outputs unconnected.
 
epN_dout, epN_re, epN_empty,
this is the IN FIFO interface. If this is a OUT endpoint ground
all unused inputs and leave outputs unconnected.
 
epN_bf_en, epN_bf_size,
These two constant configure the Block Frame feature.
 
*/
 
 
module usb1_core(clk_i, rst_i,
 
// USB PHY Interface
tx_dp, tx_dn, tx_oe,
rx_d, rx_dp, rx_dn,
 
// USB Misc
phy_tx_mode, usb_rst,
 
// Interrupts
dropped_frame, misaligned_frame,
crc16_err,
 
// Vendor Features
v_set_int, v_set_feature, wValue,
wIndex, vendor_data,
 
// USB Status
usb_busy, ep_sel,
 
// Endpoint Interface
ep1_cfg,
ep1_din, ep1_we, ep1_full,
ep1_dout, ep1_re, ep1_empty,
ep1_bf_en, ep1_bf_size,
 
ep2_cfg,
ep2_din, ep2_we, ep2_full,
ep2_dout, ep2_re, ep2_empty,
ep2_bf_en, ep2_bf_size,
 
ep3_cfg,
ep3_din, ep3_we, ep3_full,
ep3_dout, ep3_re, ep3_empty,
ep3_bf_en, ep3_bf_size,
 
ep4_cfg,
ep4_din, ep4_we, ep4_full,
ep4_dout, ep4_re, ep4_empty,
ep4_bf_en, ep4_bf_size,
 
ep5_cfg,
ep5_din, ep5_we, ep5_full,
ep5_dout, ep5_re, ep5_empty,
ep5_bf_en, ep5_bf_size,
 
ep6_cfg,
ep6_din, ep6_we, ep6_full,
ep6_dout, ep6_re, ep6_empty,
ep6_bf_en, ep6_bf_size,
 
ep7_cfg,
ep7_din, ep7_we, ep7_full,
ep7_dout, ep7_re, ep7_empty,
ep7_bf_en, ep7_bf_size
 
);
 
input clk_i;
input rst_i;
 
output tx_dp, tx_dn, tx_oe;
input rx_d, rx_dp, rx_dn;
 
input phy_tx_mode;
output usb_rst;
output dropped_frame, misaligned_frame;
output crc16_err;
 
output v_set_int;
output v_set_feature;
output [15:0] wValue;
output [15:0] wIndex;
input [15:0] vendor_data;
 
output usb_busy;
output [3:0] ep_sel;
 
// Endpoint Interfaces
input [13:0] ep1_cfg;
input [7:0] ep1_din;
output [7:0] ep1_dout;
output ep1_we, ep1_re;
input ep1_empty, ep1_full;
input ep1_bf_en;
input [6:0] ep1_bf_size;
 
input [13:0] ep2_cfg;
input [7:0] ep2_din;
output [7:0] ep2_dout;
output ep2_we, ep2_re;
input ep2_empty, ep2_full;
input ep2_bf_en;
input [6:0] ep2_bf_size;
 
input [13:0] ep3_cfg;
input [7:0] ep3_din;
output [7:0] ep3_dout;
output ep3_we, ep3_re;
input ep3_empty, ep3_full;
input ep3_bf_en;
input [6:0] ep3_bf_size;
 
input [13:0] ep4_cfg;
input [7:0] ep4_din;
output [7:0] ep4_dout;
output ep4_we, ep4_re;
input ep4_empty, ep4_full;
input ep4_bf_en;
input [6:0] ep4_bf_size;
 
input [13:0] ep5_cfg;
input [7:0] ep5_din;
output [7:0] ep5_dout;
output ep5_we, ep5_re;
input ep5_empty, ep5_full;
input ep5_bf_en;
input [6:0] ep5_bf_size;
 
input [13:0] ep6_cfg;
input [7:0] ep6_din;
output [7:0] ep6_dout;
output ep6_we, ep6_re;
input ep6_empty, ep6_full;
input ep6_bf_en;
input [6:0] ep6_bf_size;
 
input [13:0] ep7_cfg;
input [7:0] ep7_din;
output [7:0] ep7_dout;
output ep7_we, ep7_re;
input ep7_empty, ep7_full;
input ep7_bf_en;
input [6:0] ep7_bf_size;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
// UTMI Interface
wire [7:0] DataOut;
wire TxValid;
wire TxReady;
wire [7:0] DataIn;
wire RxValid;
wire RxActive;
wire RxError;
wire [1:0] LineState;
 
wire [7:0] rx_data;
wire rx_valid, rx_active, rx_err;
wire [7:0] tx_data;
wire tx_valid;
wire tx_ready;
wire tx_first;
wire tx_valid_last;
 
// Internal Register File Interface
wire [6:0] funct_adr; // This functions address (set by controller)
wire [3:0] ep_sel; // Endpoint Number Input
wire crc16_err; // Set CRC16 error interrupt
wire int_to_set; // Set time out interrupt
wire int_seqerr_set; // Set PID sequence error interrupt
wire [31:0] frm_nat; // Frame Number and Time Register
wire nse_err; // No Such Endpoint Error
wire pid_cs_err; // PID CS error
wire crc5_err; // CRC5 Error
 
reg [7:0] tx_data_st;
wire [7:0] rx_data_st;
reg [13:0] cfg;
reg ep_empty;
reg ep_full;
wire [7:0] rx_size;
wire rx_done;
 
wire [7:0] ep0_din;
wire [7:0] ep0_dout;
wire ep0_re, ep0_we;
wire [13:0] ep0_cfg;
wire [7:0] ep0_size;
wire [7:0] ep0_ctrl_dout, ep0_ctrl_din;
wire ep0_ctrl_re, ep0_ctrl_we;
wire [3:0] ep0_ctrl_stat;
 
wire ctrl_setup, ctrl_in, ctrl_out;
wire send_stall;
wire token_valid;
reg rst_local; // internal reset
wire dropped_frame;
wire misaligned_frame;
wire v_set_int;
wire v_set_feature;
wire [15:0] wValue;
wire [15:0] wIndex;
 
reg ep_bf_en;
reg [6:0] ep_bf_size;
wire [6:0] rom_adr;
wire [7:0] rom_data;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
// Endpoint type and Max transfer size
assign ep0_cfg = `CTRL | ep0_size;
 
always @(posedge clk_i)
rst_local <= #1 rst_i & ~usb_rst;
 
///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//
 
usb_phy phy(
.clk( clk_i ),
.rst( rst_i ), // ONLY external reset
.phy_tx_mode( phy_tx_mode ),
.usb_rst( usb_rst ),
 
// Transceiver Interface
.rxd( rx_d ),
.rxdp( rx_dp ),
.rxdn( rx_dn ),
.txdp( tx_dp ),
.txdn( tx_dn ),
.txoe( tx_oe ),
 
// UTMI Interface
.DataIn_o( DataIn ),
.RxValid_o( RxValid ),
.RxActive_o( RxActive ),
.RxError_o( RxError ),
.DataOut_i( DataOut ),
.TxValid_i( TxValid ),
.TxReady_o( TxReady ),
.LineState_o( LineState )
);
 
// UTMI Interface
usb1_utmi_if u0(
.phy_clk( clk_i ),
.rst( rst_local ),
.DataOut( DataOut ),
.TxValid( TxValid ),
.TxReady( TxReady ),
.RxValid( RxValid ),
.RxActive( RxActive ),
.RxError( RxError ),
.DataIn( DataIn ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first )
);
 
// Protocol Layer
usb1_pl u1( .clk( clk_i ),
.rst( rst_local ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first ),
.tx_valid_out( TxValid ),
.token_valid( token_valid ),
.fa( funct_adr ),
.ep_sel( ep_sel ),
.x_busy( usb_busy ),
.int_crc16_set( crc16_err ),
.int_to_set( int_to_set ),
.int_seqerr_set( int_seqerr_set ),
.frm_nat( frm_nat ),
.pid_cs_err( pid_cs_err ),
.nse_err( nse_err ),
.crc5_err( crc5_err ),
.rx_size( rx_size ),
.rx_done( rx_done ),
.ctrl_setup( ctrl_setup ),
.ctrl_in( ctrl_in ),
.ctrl_out( ctrl_out ),
.ep_bf_en( ep_bf_en ),
.ep_bf_size( ep_bf_size ),
.dropped_frame( dropped_frame ),
.misaligned_frame( misaligned_frame ),
.csr( cfg ),
.tx_data_st( tx_data_st ),
.rx_data_st( rx_data_st ),
.idma_re( idma_re ),
.idma_we( idma_we ),
.ep_empty( ep_empty ),
.ep_full( ep_full ),
.send_stall( send_stall )
);
 
usb1_ctrl u4( .clk( clk_i ),
.rst( rst_local ),
 
.rom_adr( rom_adr ),
.rom_data( rom_data ),
 
.ctrl_setup( ctrl_setup ),
.ctrl_in( ctrl_in ),
.ctrl_out( ctrl_out ),
 
.ep0_din( ep0_ctrl_dout ),
.ep0_dout( ep0_ctrl_din ),
.ep0_re( ep0_ctrl_re ),
.ep0_we( ep0_ctrl_we ),
.ep0_stat( ep0_ctrl_stat ),
.ep0_size( ep0_size ),
 
.send_stall( send_stall ),
.frame_no( frm_nat[26:16] ),
.funct_adr( funct_adr ),
.configured( ),
.halt( ),
 
.v_set_int( v_set_int ),
.v_set_feature( v_set_feature ),
.wValue( wValue ),
.wIndex( wIndex ),
.vendor_data( vendor_data )
);
 
 
usb1_rom1 rom1( .clk( clk_i ),
.adr( rom_adr ),
.dout( rom_data )
);
 
// CTRL Endpoint FIFO
generic_fifo_sc_a #(8,6,0) u10(
.clk( clk_i ),
.rst( rst_i ),
.clr( usb_rst ),
.din( rx_data_st ),
.we( ep0_we ),
.dout( ep0_ctrl_dout ),
.re( ep0_ctrl_re ),
.full_r( ),
.empty_r( ),
.full( ep0_full ),
.empty( ep0_ctrl_stat[1] ),
.full_n( ),
.empty_n( ),
.full_n_r( ),
.empty_n_r( ),
.level( )
);
 
generic_fifo_sc_a #(8,6,0) u11(
.clk( clk_i ),
.rst( rst_i ),
.clr( usb_rst ),
.din( ep0_ctrl_din ),
.we( ep0_ctrl_we ),
.dout( ep0_dout ),
.re( ep0_re ),
.full_r( ),
.empty_r( ),
.full( ep0_ctrl_stat[2] ),
.empty( ep0_empty ),
.full_n( ),
.empty_n( ),
.full_n_r( ),
.empty_n_r( ),
.level( )
);
 
///////////////////////////////////////////////////////////////////
//
// Endpoint FIFO Interfaces
//
 
always @(ep_sel or ep0_cfg or ep1_cfg or ep2_cfg or ep3_cfg or
ep4_cfg or ep5_cfg or ep6_cfg or ep7_cfg)
case(ep_sel) // synopsys full_case parallel_case
4'h0: cfg = ep0_cfg;
4'h1: cfg = ep1_cfg;
4'h2: cfg = ep2_cfg;
4'h3: cfg = ep3_cfg;
4'h4: cfg = ep4_cfg;
4'h5: cfg = ep5_cfg;
4'h6: cfg = ep6_cfg;
4'h7: cfg = ep7_cfg;
endcase
 
// In endpoints only
always @(posedge clk_i)
case(ep_sel) // synopsys full_case parallel_case
4'h0: tx_data_st <= #1 ep0_dout;
4'h1: tx_data_st <= #1 ep1_din;
4'h2: tx_data_st <= #1 ep2_din;
4'h3: tx_data_st <= #1 ep3_din;
4'h3: tx_data_st <= #1 ep4_din;
4'h5: tx_data_st <= #1 ep5_din;
4'h6: tx_data_st <= #1 ep6_din;
4'h7: tx_data_st <= #1 ep7_din;
endcase
 
// In endpoints only
always @(posedge clk_i)
case(ep_sel) // synopsys full_case parallel_case
4'h0: ep_empty <= #1 ep0_empty;
4'h1: ep_empty <= #1 ep1_empty;
4'h2: ep_empty <= #1 ep2_empty;
4'h3: ep_empty <= #1 ep3_empty;
4'h4: ep_empty <= #1 ep4_empty;
4'h5: ep_empty <= #1 ep5_empty;
4'h6: ep_empty <= #1 ep6_empty;
4'h7: ep_empty <= #1 ep7_empty;
endcase
 
// OUT endpoints only
always @(ep_sel or ep0_full or ep1_full or ep2_full or ep3_full or
ep4_full or ep5_full or ep6_full or ep7_full)
case(ep_sel) // synopsys full_case parallel_case
4'h0: ep_full = ep0_full;
4'h1: ep_full = ep1_full;
4'h2: ep_full = ep2_full;
4'h3: ep_full = ep3_full;
4'h4: ep_full = ep4_full;
4'h5: ep_full = ep5_full;
4'h6: ep_full = ep6_full;
4'h7: ep_full = ep7_full;
endcase
 
always @(posedge clk_i)
case(ep_sel) // synopsys full_case parallel_case
4'h0: ep_bf_en = 1'b0;
4'h1: ep_bf_en = ep1_bf_en;
4'h2: ep_bf_en = ep2_bf_en;
4'h3: ep_bf_en = ep3_bf_en;
4'h4: ep_bf_en = ep4_bf_en;
4'h5: ep_bf_en = ep5_bf_en;
4'h6: ep_bf_en = ep6_bf_en;
4'h7: ep_bf_en = ep7_bf_en;
endcase
 
always @(posedge clk_i)
case(ep_sel) // synopsys full_case parallel_case
4'h1: ep_bf_size = ep1_bf_size;
4'h2: ep_bf_size = ep2_bf_size;
4'h3: ep_bf_size = ep3_bf_size;
4'h4: ep_bf_size = ep4_bf_size;
4'h5: ep_bf_size = ep5_bf_size;
4'h6: ep_bf_size = ep6_bf_size;
4'h7: ep_bf_size = ep7_bf_size;
endcase
 
assign ep1_dout = rx_data_st;
assign ep2_dout = rx_data_st;
assign ep3_dout = rx_data_st;
assign ep4_dout = rx_data_st;
assign ep5_dout = rx_data_st;
assign ep6_dout = rx_data_st;
assign ep7_dout = rx_data_st;
 
assign ep0_re = idma_re & (ep_sel == 4'h00);
assign ep1_re = idma_re & (ep_sel == 4'h01) & !ep1_empty;
assign ep2_re = idma_re & (ep_sel == 4'h02) & !ep2_empty;
assign ep3_re = idma_re & (ep_sel == 4'h03) & !ep3_empty;
assign ep4_re = idma_re & (ep_sel == 4'h04) & !ep4_empty;
assign ep5_re = idma_re & (ep_sel == 4'h05) & !ep5_empty;
assign ep6_re = idma_re & (ep_sel == 4'h06) & !ep6_empty;
assign ep7_re = idma_re & (ep_sel == 4'h07) & !ep7_empty;
 
assign ep0_we = idma_we & (ep_sel == 4'h00);
assign ep1_we = idma_we & (ep_sel == 4'h01) & !ep1_full;
assign ep2_we = idma_we & (ep_sel == 4'h02) & !ep2_full;
assign ep3_we = idma_we & (ep_sel == 4'h03) & !ep3_full;
assign ep4_we = idma_we & (ep_sel == 4'h04) & !ep4_full;
assign ep5_we = idma_we & (ep_sel == 4'h05) & !ep5_full;
assign ep6_we = idma_we & (ep_sel == 4'h06) & !ep6_full;
assign ep7_we = idma_we & (ep_sel == 4'h07) & !ep7_full;
 
endmodule
 
/trunk/rtl/verilog/usb1_idma.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usb1_idma.v,v 1.1.1.1 2002-09-19 12:07:38 rudi Exp $
// $Id: usb1_idma.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
//
// $Date: 2002-09-19 12:07:38 $
// $Revision: 1.1.1.1 $
// $Date: 2002-09-25 06:06:49 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,11 → 48,14
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/09/19 12:07:38 rudi
// Initial Checkin
//
//
//
//
//
//
 
`include "usb1_defines.v"
 
75,10 → 78,14
// Register File Manager Interface
size,
rx_cnt, rx_done,
tx_busy,
 
// Block Frames
ep_bf_en, ep_bf_size,
dropped_frame, misaligned_frame,
 
// Memory Arb interface
mwe, mre, ep_empty, ep_empty_latched, ep_full
mwe, mre, ep_empty, ep_empty_int, ep_full
);
 
 
103,6 → 110,10
input [8:0] size; // MAX PL Size in bytes
output [7:0] rx_cnt;
output rx_done;
output tx_busy;
 
input ep_bf_en;
input [6:0] ep_bf_size;
output dropped_frame;
output misaligned_frame;
 
110,7 → 121,7
output mwe;
output mre;
input ep_empty;
output ep_empty_latched;
output ep_empty_int;
input ep_full;
 
///////////////////////////////////////////////////////////////////
144,39 → 155,33
reg [7:0] rx_cnt_r;
reg ep_empty_r;
reg ep_empty_latched;
wire sp_ep_sel;
wire ep_empty_int;
reg [5:0] ec;
reg [6:0] ec;
wire ec_clr;
reg dropped_frame;
reg [5:0] rc_cnt;
wire sp_ep2_sel;
reg [6:0] rc_cnt;
wire rc_clr;
reg ep_full_latched;
wire ep_full_int;
reg misaligned_frame;
reg tx_valid_r;
wire tx_valid_e;
 
///////////////////////////////////////////////////////////////////
//
// For ISO interface transmit frames in 32 byte quantities
// For IN Block Frames transmit frames in [ep_bf_size] byte quantities
//
 
assign sp_ep_sel = (ep_sel==4'h1); // Special endpoint
`ifdef USB1_BF_ENABLE
 
`ifdef USB1_ISO_CHUNKS
assign ep_empty_int = sp_ep_sel ? ep_empty_latched : ep_empty;
`else
assign ep_empty_int = ep_empty;
`endif
 
always @(posedge clk)
if(!rst) ec <= #1 6'h0;
if(!rst) ec <= #1 7'h0;
else
if(!sp_ep_sel | ec_clr) ec <= #1 6'h0;
if(!ep_bf_en | ec_clr) ec <= #1 7'h0;
else
if(mre) ec <= #1 ec + 6'h1;
if(mre) ec <= #1 ec + 7'h1;
 
assign ec_clr = (ec == 6'd032) | tx_dma_en;
assign ec_clr = (ec == ep_bf_size) | tx_dma_en;
 
always @(posedge clk)
if(!rst) ep_empty_latched <= #1 1'b0;
183,22 → 188,26
else
if(ec_clr) ep_empty_latched <= #1 ep_empty;
 
assign ep_empty_int = ep_bf_en ? ep_empty_latched : ep_empty;
`else
assign ep_empty_int = ep_empty;
`endif
///////////////////////////////////////////////////////////////////
//
// For ISO interface OUT always store in 32 byte chunks
// if fifo can't accept 32 bytes junk the entire 32 byte frame
// For OUT Block Frames always store in [ep_bf_size] byte chunks
// if fifo can't accept [ep_bf_size] bytes junk the entire [ep_bf_size]
// byte frame
//
 
assign sp_ep2_sel = (ep_sel==4'h2); // Special endpoint
 
`ifdef USB1_BF_ENABLE
always @(posedge clk)
if(!rst) rc_cnt <= #1 6'h0;
if(!rst) rc_cnt <= #1 7'h0;
else
if(!sp_ep2_sel | rc_clr) rc_cnt <= #1 6'h0;
if(!ep_bf_en | rc_clr) rc_cnt <= #1 7'h0;
else
if(mwe_r) rc_cnt <= #1 rc_cnt + 6'h1;
if(mwe_r) rc_cnt <= #1 rc_cnt + 7'h1;
 
assign rc_clr = ((rc_cnt == 6'd031) & mwe_r) | rx_dma_en;
assign rc_clr = ((rc_cnt == ep_bf_size) & mwe_r) | rx_dma_en;
 
always @(posedge clk)
if(!rst) ep_full_latched <= #1 1'b0;
205,27 → 214,34
else
if(rc_clr) ep_full_latched <= #1 ep_full;
 
`ifdef USB1_ISO_CHUNKS
assign ep_full_int = sp_ep2_sel ? ep_full_latched : ep_full;
assign ep_full_int = ep_bf_en ? ep_full_latched : ep_full;
 
always @(posedge clk)
dropped_frame <= #1 rc_clr & ep_full & ep_bf_en;
 
always @(posedge clk)
misaligned_frame <= #1 rx_data_done_r & ep_bf_en & (rc_cnt!=7'd00);
`else
assign ep_full_int = ep_full;
`endif
 
always @(posedge clk)
dropped_frame <= #1 rc_clr & ep_full & sp_ep2_sel;
dropped_frame <= #1 1'b0;
 
always @(posedge clk)
misaligned_frame <= #1 rx_data_done_r & sp_ep2_sel & (rc_cnt!=6'd00);
misaligned_frame <= #1 1'b0;
 
`endif
 
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
always @(posedge dropped_frame)
$display("WARNING: Droped one OUT frame (no space in FIFO) (%t)",$time);
$display("WARNING: BF: Droped one OUT frame (no space in FIFO) (%t)",$time);
 
always @(posedge misaligned_frame)
$display("WARNING: Received misaligned frame (%t)",$time);
$display("WARNING: BF: Received misaligned frame (%t)",$time);
`endif
// synopsys translate_on
 
///////////////////////////////////////////////////////////////////
//
// FIFO interface
308,8 → 324,7
// TX Logic
//
 
reg tx_valid_r;
wire tx_valid_e;
assign tx_busy = send_data | tx_dma_en_r | tx_dma_en;
 
always @(posedge clk)
tx_valid_r <= #1 tx_valid;
/trunk/rtl/verilog/usb1_pl.v
40,10 → 40,10
 
// CVS Log
//
// $Id: usb1_pl.v,v 1.1.1.1 2002-09-19 12:07:28 rudi Exp $
// $Id: usb1_pl.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
//
// $Date: 2002-09-19 12:07:28 $
// $Revision: 1.1.1.1 $
// $Date: 2002-09-25 06:06:49 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
50,6 → 50,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/09/19 12:07:28 rudi
// Initial Checkin
//
//
//
58,6 → 60,7
//
//
//
//
 
module usb1_pl( clk, rst,
 
71,7 → 74,7
// Register File Interface
fa,
ep_sel,
 
x_busy,
int_crc16_set, int_to_set, int_seqerr_set,
 
// Misc
80,6 → 83,9
crc5_err,
rx_size, rx_done,
ctrl_setup, ctrl_in, ctrl_out,
 
// Block Frames
ep_bf_en, ep_bf_size,
dropped_frame, misaligned_frame,
 
// EP Interface
105,6 → 111,7
// Register File interface
input [6:0] fa; // Function Address (as set by the controller)
output [3:0] ep_sel; // Endpoint Number Input
output x_busy; // Indicates USB is busy
 
output int_crc16_set; // Set CRC16 error interrupt
output int_to_set; // Set time out interrupt
120,6 → 127,8
output ctrl_setup;
output ctrl_in;
output ctrl_out;
input ep_bf_en;
input [6:0] ep_bf_size;
output dropped_frame, misaligned_frame;
 
// Endpoint Interfaces
192,7 → 201,9
reg ctrl_out;
 
wire idma_we_d;
wire ep_empty_latched;
wire ep_empty_int;
wire rx_busy;
wire tx_busy;
 
///////////////////////////////////////////////////////////////////
//
199,6 → 210,8
// Misc Logic
//
 
assign x_busy = tx_busy | rx_busy;
 
// PIDs we should never receive
assign pid_bad = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
pid_ERR | pid_SPLIT | pid_PING;
205,7 → 218,7
 
assign match_o = !pid_bad & token_valid & !crc5_err;
 
// Recieving Setup
// Receiving Setup
always @(posedge clk)
ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);
 
263,7 → 276,6
// Module Instantiations
//
 
 
//Packet Decoder
usb1_pd u0( .clk( clk ),
.rst( rst ),
298,7 → 310,8
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.crc16_err( crc16_err ),
.seq_err( rx_seq_err )
.seq_err( rx_seq_err ),
.rx_busy( rx_busy )
);
 
// Packet Assembler
315,7 → 328,7
.data_pid_sel( data_pid_sel ),
.tx_data_st( tx_data_st_o ),
.rd_next( rd_next ),
.ep_empty( ep_empty_latched)
.ep_empty( ep_empty_int)
);
 
// Internal DMA / Memory Arbiter Interface
333,9 → 346,13
.tx_data_st_o( tx_data_st_o ),
.ep_sel( ep_sel ),
 
.ep_bf_en( ep_bf_en ),
.ep_bf_size( ep_bf_size ),
.dropped_frame(dropped_frame ),
.misaligned_frame(misaligned_frame),
 
.tx_busy( tx_busy ),
 
.tx_dma_en( tx_dma_en ),
.rx_dma_en( rx_dma_en ),
.idma_done( idma_done ),
345,7 → 362,7
.mwe( idma_we_d ),
.mre( idma_re ),
.ep_empty( ep_empty ),
.ep_empty_latched(ep_empty_latched),
.ep_empty_int( ep_empty_int ),
.ep_full( ep_full )
);
 
390,6 → 407,4
.send_stall( send_stall )
);
 
 
endmodule
 
/trunk/rtl/verilog/usb1_defines.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usb1_defines.v,v 1.2 2002-09-20 11:46:54 rudi Exp $
// $Id: usb1_defines.v,v 1.3 2002-09-25 06:06:49 rudi Exp $
//
// $Date: 2002-09-20 11:46:54 $
// $Revision: 1.2 $
// $Date: 2002-09-25 06:06:49 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/20 11:46:54 rudi
// fixed a type 'define' was missing ...
//
// Revision 1.1.1.1 2002/09/19 12:07:40 rudi
// Initial Checkin
//
64,10 → 67,9
//`define USBF_DEBUG
//`define USBF_VERBOSE_DEBUG
 
// Enable or disable Block Frames
//`define USB1_BF_ENABLE
 
// Enable or disable using chunkc for isochronous endpoints
`define USB1_ISO_CHUNKS
 
/////////////////////////////////////////////////////////////////////
//
// Items below this point should NOT be modified by the end user
76,6 → 78,21
//
/////////////////////////////////////////////////////////////////////
 
`define ROM_SIZE0 7'd018 // Device Descriptor Length
`define ROM_SIZE1 7'd053 // Configuration Descriptor Length
`define ROM_SIZE2A 7'd004 // Language ID Descriptor Start Length
`define ROM_SIZE2B 7'd010 // String Descriptor Length
`define ROM_SIZE2C 7'd010 // for future use
`define ROM_SIZE2D 7'd010 // for future use
 
`define ROM_START0 7'h00 // Device Descriptor Start Address
`define ROM_START1 7'h12 // Configuration Descriptor Start Address
`define ROM_START2A 7'h47 // Language ID Descriptor Start Address
`define ROM_START2B 7'h50 // String Descriptor Start Address
`define ROM_START2C 7'h60 // for future use
`define ROM_START2D 7'h70 // for future use
 
// Endpoint Configuration Constants
`define IN 14'b00_001_000000000
`define OUT 14'b00_010_000000000
`define CTRL 14'b10_100_000000000

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