Subversion Repositories watchdog

/tags/initial/rtl/verilog/watchdog.v File deleted

/tags/initial/rtl/verilog/verilog.log File deleted

/tags/initial/rtl/verilog/timescale.v File deleted

/tags/initial/rtl/verilog/watchdog_defines.v File deleted

/trunk/rtl/verilog/watchdog_defines.v File deleted

/trunk/rtl/verilog/watchdog.v File deleted

/trunk/rtl/verilog/timescale.v File deleted

/watchdog/trunk/rtl/verilog/watchdog_defines.v

/watchdog/trunk/rtl/verilog/watchdog.v

/watchdog/trunk/rtl/verilog/timescale.v

/watchdog/trunk

watchdog/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: watchdog/web_uploads =================================================================== --- watchdog/web_uploads (nonexistent) +++ watchdog/web_uploads (revision 5)

watchdog/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: watchdog/branches =================================================================== --- watchdog/branches (nonexistent) +++ watchdog/branches (revision 5)

watchdog/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: watchdog/tags/initial/rtl/verilog/watchdog_defines.v =================================================================== --- watchdog/tags/initial/rtl/verilog/watchdog_defines.v (nonexistent) +++ watchdog/tags/initial/rtl/verilog/watchdog_defines.v (revision 5) @@ -0,0 +1,42 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant Watchdog timer //// +//// //// +//// //// +//// Author: Marko Mlinar //// +//// markom@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Marko Mlinar //// +//// markom@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +/* Wishbone data width */ +`define WDT_WIDTH 32 + +/* If number is -1, counting is stopped */ +`define WDT_INITIAL (~`WDT_WIDTH'h0) + + + Index: watchdog/tags/initial/rtl/verilog/watchdog.v =================================================================== --- watchdog/tags/initial/rtl/verilog/watchdog.v (nonexistent) +++ watchdog/tags/initial/rtl/verilog/watchdog.v (revision 5) @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant Watchdog timer //// +//// //// +//// //// +//// Author: Marko Mlinar //// +//// markom@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Marko Mlinar //// +//// markom@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +/* + Watchdog time functionality + =========================== + + Watchdog timer has only one wishbone address, holding current counter + value. Countdown timer decreases its contents by 1 each wishbone clock. + When 0 is reached, interrupt is asserted. Interrupt is deasserted upon + next read/write to watchdog timer register. + If contents of the watchdog timer are -1 (e.g. 32'hffff_ffff), counter is + stopped. + Timer can start counting at wisbone reset, if `WDT_INITIAL != -1. + + For typical watchdog timer configuration wb_int_o signal should cause + system reset. +*/ + + +`include "timescale.v" +`include "watchdog_defines.v" + +module watchdog( + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + wb_int_o); + +parameter Tp = 1; + +// wishbone signals +input wb_clk_i; // master clock input +input wb_rst_i; // synchronous active high reset +input [`WDT_WIDTH - 1:0] wb_dat_i; // databus input +output [`WDT_WIDTH - 1:0] wb_dat_o; // databus output +reg [`WDT_WIDTH - 1:0] wb_dat_o; +input wb_we_i; // write enable input +input wb_stb_i; // stobe/core select signal +input wb_cyc_i; // valid bus cycle input +output wb_ack_o; // bus cycle acknowledge output +output wb_int_o; // interrupt request signal output +reg wb_int_o; // interrupt request signal output + +reg stb; +reg we; +reg [`WDT_WIDTH - 1:0] dat_ir; + +assign wb_ack_o = stb; + +/* sample input signals */ +always @(posedge wb_rst_i or posedge wb_clk_i) + if (wb_rst_i) begin + stb <= #Tp 1'b0; + we <= #Tp 1'b0; + dat_ir <= #Tp `WDT_WIDTH'h0; + end else begin + stb <= #Tp wb_stb_i && wb_cyc_i; + we <= #Tp wb_we_i; + dat_ir <= #Tp wb_dat_i; + end + +/* Counter */ +always @(posedge wb_rst_i or posedge wb_clk_i) + if (wb_rst_i) wb_dat_o <= #Tp `WDT_INITIAL; + else if (stb && we) wb_dat_o <= #Tp dat_ir; + else if (~&wb_dat_o) wb_dat_o <= #Tp wb_dat_o - `WDT_WIDTH'h1; + +/* Interrupt */ +always @(posedge wb_rst_i or posedge wb_clk_i) + if (wb_rst_i) wb_int_o <= #Tp 1'b0; + else if (stb) wb_int_o <= #Tp 1'b0; + else if (~|wb_dat_o) wb_int_o <= #Tp 1'b1; + +endmodule + Index: watchdog/tags/initial/rtl/verilog/verilog.log =================================================================== --- watchdog/tags/initial/rtl/verilog/verilog.log (nonexistent) +++ watchdog/tags/initial/rtl/verilog/verilog.log (revision 5) @@ -0,0 +1,49 @@ +Host command: /shared/tools/ncsim/tools/verilog/bin/verilog.exe +Command arguments: + timescale.v + watchdog.v + watchdog_defines.v + +VERILOG-XL 3.30.p001 log file created Sep 12, 2002 12:04:24 +VERILOG-XL 3.30.p001 Sep 12, 2002 12:04:24 + +Copyright (c) 1995 Cadence Design Systems, Inc. All Rights Reserved. +Unpublished -- rights reserved under the copyright laws of the United States. + +Copyright (c) 1995 UNIX Systems Laboratories, Inc. Reproduced with Permission. + +THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION +AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR +REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF +CADENCE DESIGN SYSTEMS, INC. +RESTRICTED RIGHTS LEGEND + +Use, duplication, or disclosure by the Government is subject to +restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in +Technical Data and Computer Software clause at DFARS 252.227-7013 or +subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted +Rights at 48 CFR 52.227-19, as applicable. + + Cadence Design Systems, Inc. + 555 River Oaks Parkway + San Jose, California 95134 + +For technical assistance please contact the Cadence Response Center at +1-877-CDS-4911 or send email to support@cadence.com + +For more information on Cadence's Verilog-XL product line send email to +talkv@cadence.com + +Compiling source file "timescale.v" +Compiling source file "watchdog.v" +Compiling included source file "timescale.v" +Continuing compilation of source file "watchdog.v" +Compiling included source file "watchdog_defines.v" +Continuing compilation of source file "watchdog.v" +Compiling source file "watchdog_defines.v" +Highest level modules: +watchdog + +0 simulation events (use +profile or +listcounts option to count) +CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation +End of VERILOG-XL 3.30.p001 Sep 12, 2002 12:04:24 Index: watchdog/tags/initial/rtl/verilog/timescale.v =================================================================== --- watchdog/tags/initial/rtl/verilog/timescale.v (nonexistent) +++ watchdog/tags/initial/rtl/verilog/timescale.v (revision 5) @@ -0,0 +1,36 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant Watchdog timer //// +//// //// +//// //// +//// Author: Marko Mlinar //// +//// markom@opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Marko Mlinar //// +//// markom@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +// Timescale define + +`timescale 1ns/10ps Index: watchdog/tags =================================================================== --- watchdog/tags (nonexistent) +++ watchdog/tags (revision 5)

watchdog/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##