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URL https://opencores.org/ocsvn/wb2hpi/wb2hpi/trunk

Subversion Repositories wb2hpi

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    from Rev 4 to Rev 5
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Rev 4 → Rev 5

/trunk/apps/pci2dsp/rtl/verilog/top.v
45,8 → 45,8
// CVS History
//
// $Author: gvozden $
// $Date: 2003-02-28 14:10:52 $
// $Revision: 1.2 $
// $Date: 2003-03-18 14:38:34 $
// $Revision: 1.3 $
 
module TOP
(
101,8 → 101,6
CBE2,
CBE3,
WB_CLK,
 
DSP_HAD,
DSP_HCNTL,
DSP_HBIL,
119,8 → 117,6
LED
);
 
input WB_CLK;
 
inout [ 7:0] DSP_HAD;
output [ 1:0] DSP_HCNTL;
output DSP_HBIL;
326,7 → 322,7
pci_bridge32 bridge
(
// WISHBONE system signals
.wb_clk_i(WB_CLK),
.wb_clk_i(CLK),
.wb_rst_i(RST_I),
.wb_rst_o(RST_O),
.wb_int_i(INT_I),

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