URL
https://opencores.org/ocsvn/wb_conmax/wb_conmax/trunk
Subversion Repositories wb_conmax
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/
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/bench/verilog/wb_mast_model.v
9,8 → 9,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
35,10 → 36,10
|
// CVS Log |
// |
// $Id: wb_mast_model.v,v 1.1.1.1 2001-10-19 11:04:23 rudi Exp $ |
// $Id: wb_mast_model.v,v 1.2 2002-10-03 05:40:03 rudi Exp $ |
// |
// $Date: 2001-10-19 11:04:23 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:03 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
45,9 → 46,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:04:23 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_model_defines.v" |
/trunk/bench/verilog/wb_slv_model.v
7,12 → 7,13
//// rudi@asics.ws //// |
//// //// |
//// //// |
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// |
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_slv_model.v,v 1.1.1.1 2001-10-19 11:04:25 rudi Exp $ |
// $Id: wb_slv_model.v,v 1.2 2002-10-03 05:40:03 rudi Exp $ |
// |
// $Date: 2001-10-19 11:04:25 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:03 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 48,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:04:25 rudi |
// WISHBONE CONMAX IP Core |
// |
// Revision 1.1 2001/07/29 08:57:02 rudi |
// |
// |
/trunk/bench/verilog/test_bench_top.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: test_bench_top.v,v 1.1.1.1 2001-10-19 11:04:25 rudi Exp $ |
// $Id: test_bench_top.v,v 1.2 2002-10-03 05:40:03 rudi Exp $ |
// |
// $Date: 2001-10-19 11:04:25 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:03 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,11 → 48,14
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:04:25 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
// |
|
|
`include "wb_conmax_defines.v" |
/trunk/bench/verilog/wb_model_defines.v
9,8 → 9,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
35,10 → 36,10
|
// CVS Log |
// |
// $Id: wb_model_defines.v,v 1.1.1.1 2001-10-19 11:04:23 rudi Exp $ |
// $Id: wb_model_defines.v,v 1.2 2002-10-03 05:40:03 rudi Exp $ |
// |
// $Date: 2001-10-19 11:04:23 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:03 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
45,10 → 46,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:04:23 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
// |
|
`timescale 1ns / 10ps |
/trunk/rtl/verilog/wb_conmax_pri_enc.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_pri_enc.v,v 1.1.1.1 2001-10-19 11:01:41 rudi Exp $ |
// $Id: wb_conmax_pri_enc.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:41 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:41 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
/trunk/rtl/verilog/wb_conmax_msel.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_msel.v,v 1.1.1.1 2001-10-19 11:01:38 rudi Exp $ |
// $Id: wb_conmax_msel.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:38 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:38 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
/trunk/rtl/verilog/wb_conmax_top.v
7,12 → 7,13
//// rudi@asics.ws //// |
//// //// |
//// //// |
//// Downloaded from: http://www.opencores.org/cores/wb_ic/ //// |
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_top.v,v 1.1.1.1 2001-10-19 11:01:38 rudi Exp $ |
// $Id: wb_conmax_top.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:38 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:38 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
1812,7 → 1816,7
// Master Interfaces |
// |
|
wb_conmax_master_if #(aw,dw,sw) m0( |
wb_conmax_master_if #(dw,aw,sw) m0( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m0_data_i ), |
1987,7 → 1991,7
.s15_rty_i( m0s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m1( |
wb_conmax_master_if #(dw,aw,sw) m1( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m1_data_i ), |
2162,7 → 2166,7
.s15_rty_i( m1s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m2( |
wb_conmax_master_if #(dw,aw,sw) m2( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m2_data_i ), |
2337,7 → 2341,7
.s15_rty_i( m2s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m3( |
wb_conmax_master_if #(dw,aw,sw) m3( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m3_data_i ), |
2512,7 → 2516,7
.s15_rty_i( m3s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m4( |
wb_conmax_master_if #(dw,aw,sw) m4( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m4_data_i ), |
2687,7 → 2691,7
.s15_rty_i( m4s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m5( |
wb_conmax_master_if #(dw,aw,sw) m5( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m5_data_i ), |
2862,7 → 2866,7
.s15_rty_i( m5s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m6( |
wb_conmax_master_if #(dw,aw,sw) m6( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m6_data_i ), |
3037,7 → 3041,7
.s15_rty_i( m6s15_rty ) |
); |
|
wb_conmax_master_if #(aw,dw,sw) m7( |
wb_conmax_master_if #(dw,aw,sw) m7( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.wb_data_i( m7_data_i ), |
4753,7 → 4757,7
.m7_rty_o( m7s15_rty ) |
); |
|
wb_conmax_rf #(rf_addr,aw,dw,sw) rf( |
wb_conmax_rf #(rf_addr,dw,aw,sw) rf( |
.clk_i( clk_i ), |
.rst_i( rst_i ), |
.i_wb_data_i( i_s15_data_o ), |
/trunk/rtl/verilog/wb_conmax_arb.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_arb.v,v 1.1.1.1 2001-10-19 11:01:40 rudi Exp $ |
// $Id: wb_conmax_arb.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:40 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,11 → 48,14
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:40 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
/trunk/rtl/verilog/wb_conmax_pri_dec.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_pri_dec.v,v 1.1.1.1 2001-10-19 11:01:42 rudi Exp $ |
// $Id: wb_conmax_pri_dec.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:42 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:42 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
/trunk/rtl/verilog/wb_conmax_rf.v
7,12 → 7,13
//// rudi@asics.ws //// |
//// //// |
//// //// |
//// Downloaded from: http://www.opencores.org/cores/wb_ic/ //// |
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_rf.v,v 1.1.1.1 2001-10-19 11:01:42 rudi Exp $ |
// $Id: wb_conmax_rf.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:42 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:42 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
/trunk/rtl/verilog/wb_conmax_slave_if.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_slave_if.v,v 1.1.1.1 2001-10-19 11:01:39 rudi Exp $ |
// $Id: wb_conmax_slave_if.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:39 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:39 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
101,8 → 105,8
// |
|
parameter [1:0] pri_sel = 2'd2; |
parameter aw = 32; // Address bus Width |
parameter dw = 32; // Data bus Width |
parameter aw = 32; // Address bus Width |
parameter sw = dw / 8; // Number of Select Lines |
|
//////////////////////////////////////////////////////////////////// |
/trunk/rtl/verilog/wb_conmax_master_if.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_master_if.v,v 1.1.1.1 2001-10-19 11:01:41 rudi Exp $ |
// $Id: wb_conmax_master_if.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:41 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,10 → 48,13
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:41 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
// |
// |
|
`include "wb_conmax_defines.v" |
|
358,6 → 362,16
reg wb_rty_o; |
wire [3:0] slv_sel; |
|
wire s0_cyc_o_next, s1_cyc_o_next, s2_cyc_o_next, s3_cyc_o_next; |
wire s4_cyc_o_next, s5_cyc_o_next, s6_cyc_o_next, s7_cyc_o_next; |
wire s8_cyc_o_next, s9_cyc_o_next, s10_cyc_o_next, s11_cyc_o_next; |
wire s12_cyc_o_next, s13_cyc_o_next, s14_cyc_o_next, s15_cyc_o_next; |
|
reg s0_cyc_o, s1_cyc_o, s2_cyc_o, s3_cyc_o; |
reg s4_cyc_o, s5_cyc_o, s6_cyc_o, s7_cyc_o; |
reg s8_cyc_o, s9_cyc_o, s10_cyc_o, s11_cyc_o; |
reg s12_cyc_o, s13_cyc_o, s14_cyc_o, s15_cyc_o; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Select logic |
467,23 → 481,87
assign s14_we_o = wb_we_i; |
assign s15_we_o = wb_we_i; |
|
assign s0_cyc_o = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0); |
assign s1_cyc_o = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0); |
assign s2_cyc_o = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0); |
assign s3_cyc_o = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0); |
assign s4_cyc_o = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0); |
assign s5_cyc_o = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0); |
assign s6_cyc_o = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0); |
assign s7_cyc_o = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0); |
assign s8_cyc_o = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0); |
assign s9_cyc_o = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0); |
assign s10_cyc_o = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0); |
assign s11_cyc_o = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0); |
assign s12_cyc_o = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0); |
assign s13_cyc_o = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0); |
assign s14_cyc_o = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0); |
assign s15_cyc_o = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0); |
assign s0_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0); |
assign s1_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0); |
assign s2_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0); |
assign s3_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0); |
assign s4_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0); |
assign s5_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0); |
assign s6_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0); |
assign s7_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0); |
assign s8_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0); |
assign s9_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0); |
assign s10_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0); |
assign s11_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0); |
assign s12_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0); |
assign s13_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0); |
assign s14_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0); |
assign s15_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0); |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s0_cyc_o <= #1 1'b0; |
else s0_cyc_o <= #1 s0_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s1_cyc_o <= #1 1'b0; |
else s1_cyc_o <= #1 s1_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s2_cyc_o <= #1 1'b0; |
else s2_cyc_o <= #1 s2_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s3_cyc_o <= #1 1'b0; |
else s3_cyc_o <= #1 s3_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s4_cyc_o <= #1 1'b0; |
else s4_cyc_o <= #1 s4_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s5_cyc_o <= #1 1'b0; |
else s5_cyc_o <= #1 s5_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s6_cyc_o <= #1 1'b0; |
else s6_cyc_o <= #1 s6_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s7_cyc_o <= #1 1'b0; |
else s7_cyc_o <= #1 s7_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s8_cyc_o <= #1 1'b0; |
else s8_cyc_o <= #1 s8_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s9_cyc_o <= #1 1'b0; |
else s9_cyc_o <= #1 s9_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s10_cyc_o <= #1 1'b0; |
else s10_cyc_o <= #1 s10_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s11_cyc_o <= #1 1'b0; |
else s11_cyc_o <= #1 s11_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s12_cyc_o <= #1 1'b0; |
else s12_cyc_o <= #1 s12_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s13_cyc_o <= #1 1'b0; |
else s13_cyc_o <= #1 s13_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s14_cyc_o <= #1 1'b0; |
else s14_cyc_o <= #1 s14_cyc_o_next; |
|
always @(posedge clk_i or posedge rst_i) |
if(rst_i) s15_cyc_o <= #1 1'b0; |
else s15_cyc_o <= #1 s15_cyc_o_next; |
|
assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0; |
assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0; |
assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0; |
/trunk/rtl/verilog/wb_conmax_defines.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: wb_conmax_defines.v,v 1.1.1.1 2001-10-19 11:01:40 rudi Exp $ |
// $Id: wb_conmax_defines.v,v 1.2 2002-10-03 05:40:07 rudi Exp $ |
// |
// $Date: 2001-10-19 11:01:40 $ |
// $Revision: 1.1.1.1 $ |
// $Date: 2002-10-03 05:40:07 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 48,8
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/10/19 11:01:40 rudi |
// WISHBONE CONMAX IP Core |
// |
// |
// |
53,6 → 56,7
// |
// |
// |
// |
|
`timescale 1ns / 10ps |
|
/trunk/doc/STATUS.txt
13,6 → 13,11
STATUS |
====== |
|
Second Release (Oct. 3, 2002) |
----------------------------- |
- Fixed small bug in the core |
- Fixed two typos in the Spec. |
|
Initial Release (10/19/2001) |
--------------------------- |
- No known problems |
/trunk/doc/conmax.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/sim/rtl_sim/bin/Makefile
37,9 → 37,8
# |
########################################################################## |
|
INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" |
LOGF=-LOGFILE .nclog |
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT |
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/ |
LOGF=-l .nclog |
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v |
GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v |
|
57,44 → 56,21
$(_TARGETS_) $(_TB_) |
|
simw: |
@$(MAKE) $(MS) sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES" |
@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES" |
|
|
sim: |
@echo "" |
@echo "----- Running NCVLOG ... ----------" |
@$(MAKE) $(MS) vlog \ |
TARGETS="$(_TARGETS_)" \ |
TB="$(_TB_)" \ |
INCDIR=$(INCDIR) \ |
WAVES="$(WAVES)" |
@echo "" |
@echo "----- Running NCELAB ... ----------" |
@$(MAKE) $(MS) elab \ |
ACCESS="$(ACCESS)" TOP=$(_TOP_) |
@echo "" |
@echo "----- Running NCSIM ... ----------" |
@$(MAKE) $(MS) ncsim TOP=$(_TOP_) |
@echo "" |
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \ |
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \ |
+ncuid+`hostname` |
|
gatew: |
@$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" |
@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES" |
|
gate: |
@echo "" |
@echo "----- Running NCVLOG ... ----------" |
@$(MAKE) $(MS) vlog \ |
TARGETS="$(UMC_LIB) $(GATE_NETLIST)" \ |
TB="$(_TB_)" \ |
INCDIR=$(INCDIR) \ |
WAVES="$(WAVES)" |
@echo "" |
@echo "----- Running NCELAB ... ----------" |
@$(MAKE) $(MS) elab \ |
ACCESS="$(ACCESS)" TOP=$(_TOP_) |
@echo "" |
@echo "----- Running NCSIM ... ----------" |
@$(MAKE) $(MS) ncsim TOP=$(_TOP_) |
@echo "" |
ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \ |
$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \ |
$(LOGF) +ncstatus +ncuid+`hostname` |
|
hal: |
@echo "" |
109,40 → 85,4
./verilog.* .nclog hal.log |
|
########################################################################## |
# |
# NCVLOG |
# |
########################################################################## |
|
vhdl: |
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-WORK count -V93 hdl/counter.vhd |
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-WORK work -V93 $(TARGETS) |
|
vlog: |
ncvlog $(NCCOMMON) $(LOGF) \ |
-WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR) |
|
########################################################################## |
# |
# NCELAB |
# |
########################################################################## |
|
elab: |
ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-WORK work $(ACCESS) -NOTIMINGCHECKS \ |
work.$(TOP) |
|
########################################################################## |
# |
# NCSIM |
# |
########################################################################## |
|
ncsim: |
ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-EXIT -ERRORMAX 10 work.$(TOP) |
|
|
/trunk/syn/bin/comp.dc
86,8 → 86,8
set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file |
set_load 0.2 [all_outputs] |
|
set_input_delay -max 0 -clock clk_i [all_inputs] |
set_output_delay -max 0 -clock clk_i [all_outputs] |
set_input_delay -max 2 -clock clk_i [all_inputs] |
set_output_delay -max 2 -clock clk_i [all_outputs] |
|
# ============================================== |
# Setup Area Constrains |
104,8 → 104,8
# Compile Design |
|
echo "+++++++++ Starting Compile ..." >> $log_file |
#compile -map_effort low -area_effort low >> $log_file |
compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file |
compile -map_effort low -area_effort low -auto_ungroup >> $log_file |
#compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file |
|
# ============================================== |
# Write Out the optimized design |