URL
https://opencores.org/ocsvn/wb_prefetch_spram/wb_prefetch_spram/trunk
Subversion Repositories wb_prefetch_spram
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- from Rev 4 to Rev 5
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Rev 4 → Rev 5
/trunk/bench/verilog/tb_defines.v
44,7 → 44,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
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// |
// Half of clock period |
63,6 → 66,11
`define RAM_WORDS (2<<`RAM_ADDRWIDTH) |
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// |
// RAM data width |
// |
`define RAM_DATAWIDTH 32 |
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// |
// Define to get VCD output |
// |
//`define VCD_DUMP |
`define VCD_DUMP |
/trunk/bench/verilog/wb_master.v
113,8 → 113,8
write_flag = 0; |
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GO <= 1; |
@(posedge CLK_I); |
GO <= 0; // DL |
// @(posedge CLK_I); |
// GO <= 0; // DL |
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// wait for cycle to start |
while (~CYC_O) |
143,8 → 143,8
data = dat; |
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GO <= 1; |
@(posedge CLK_I); |
GO <= 0; // DL |
// @(posedge CLK_I); |
// GO <= 0; // DL |
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// wait for cycle to start |
while (~CYC_O) |
170,8 → 170,8
cycle_end = end_flag; |
address = adr; |
GO <= 1; |
@(posedge CLK_I); |
GO <= 0; // DL |
// @(posedge CLK_I); |
// GO <= 0; // DL |
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while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
194,12 → 194,12
data = dat; |
selects = sel; |
GO <= 1; |
@(posedge CLK_I); |
GO <= 0; // DL |
// @(posedge CLK_I); |
// GO <= 0; // DL |
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while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
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end |
endtask // blkwr |
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/trunk/bench/verilog/tb_top.v
44,7 → 44,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
`include "timescale.v" |
|
54,7 → 57,7
// Width of address and data buses |
// |
parameter aw = `RAM_ADDRWIDTH; |
parameter dw = 16; |
parameter dw = `RAM_DATAWIDTH; |
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// |
// Internal wires |