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URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

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Rev 40 → Rev 41

/trunk/rtl/verilog/rx_engine/counter.v
1,23 → 1,52
`timescale 100ps / 10ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
`include "timescale.v"
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: counter ////
//// ////
//// DESCRIPTION: 8bit counter ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Create Date: 15:53:19 11/22/05
// Design Name:
// Module Name: counter
// Project Name:
// Target Device:
// Tool versions:
// Description:
// CVS REVISION HISTORY:
//
// Dependencies:
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////
module counter(clk, reset, load, en, value);
input clk;
input reset;
/trunk/rtl/verilog/rx_engine/rxReceiveEngine.v
57,7 → 57,7
input reset_in; //Globle reset of receive engine
input [31:0] rxd_in; //XGMII RXD
input [3:0] rxc_in; //XGMII RXC
output [17:0] rxStatRegPlus; //Signals for statistics
output [18:0] rxStatRegPlus; //Signals for statistics
input [64:0] cfgRxRegData_in; //Signals for configuration
output [63:0] rx_data; //Received data sent to upper layer
output [7:0] rx_data_valid; //Receive data valid indicator
/trunk/rtl/verilog/rx_engine/rxStatModule.v
75,11 → 75,11
input length_1024_max;
input jumbo_frame;
input get_error_code;
output [17:0] rxStatRegPlus;
output [18:0] rxStatRegPlus;
 
parameter TP =1;
 
wire[17:0] rxStatRegPlus_tmp;
wire[18:0] rxStatRegPlus_tmp;
 
////////////////////////////////////////////
// Count for Frames Received OK
140,38 → 140,44
// Count for Length/Type Out of Range
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[11] = large_error;
//////////////////////////////////////////////
// Count for Pause Frames Received OK
//////////////////////////////////////////////
// assign rxStatRegPlus_tmp[12] = tagged_frame & good_frame_get;
 
//////////////////////////////////////////////
// Count for Pause Frames Received OK
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[12] = pause_frame & good_frame_get;
assign rxStatRegPlus_tmp[13] = pause_frame & good_frame_get;
 
/////////////////////////////////////////////////////////////
// Count for Control Frames Received with Unsupported Opcode.
/////////////////////////////////////////////////////////////
// assign rxStatRegPlus_tmp[13] = pause_frame & good_frame_get;
// assign rxStatRegPlus_tmp[14] = pause_frame & good_frame_get;
 
///////////////////////////////////////////////
// Count for Oversize Frames Received OK
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[14] = jumbo_frame & good_frame_get;
assign rxStatRegPlus_tmp[15] = jumbo_frame & good_frame_get;
 
///////////////////////////////////////////////
// Count for Undersized Frames Received
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[15] = small_error;
assign rxStatRegPlus_tmp[16] = small_error;
 
///////////////////////////////////////////////
// Count for Fragment Frames Received
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[16] = receiving & get_error_code;
assign rxStatRegPlus_tmp[17] = receiving & get_error_code;
 
///////////////////////////////////////////////
// Count for Number of Bytes Received
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[17] = receiving;
assign rxStatRegPlus_tmp[18] = receiving;
 
reg[17:0] rxStatRegPlus;
reg[18:0] rxStatRegPlus;
always@(posedge rxclk or posedge reset) begin
if(reset)
rxStatRegPlus <=#TP 0;

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