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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

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Rev 40 → Rev 41

/ft816float/trunk/rtl/positVerilog/positDecompose.sv
28,17 → 28,18
// Decompose a posit number.
module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
`include "positSize.sv"
localparam rs = $clog2(PSTWID-1);
input [PSTWID-1:0] i;
output sgn; // sign of number
output rgs; // sign of regime
output [$clog2(PSTWID)-1:0] rgm; // regime (absolute value)
output [rs:0] rgm; // regime (absolute value)
output [es-1:0] exp; // exponent
output [PSTWID-es-1:0] sig; // significand
output [PSTWID-1-es:0] sig; // significand
output zer; // number is zero
output inf; // number is infinite
 
wire [$clog2(PSTWID-2):0] lzcnt;
wire [$clog2(PSTWID-2):0] locnt;
wire [rs:0] lzcnt;
wire [rs:0] locnt;
 
 
assign sgn = i[PSTWID-1];
51,7 → 52,7
positCntlo #(PSTWID) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
 
assign rgm = rgs ? locnt - 1 : lzcnt;
wire [$clog2(PSTWID)-1:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
wire [PSTWID-1:0] tmp = ii << shamt;
assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
assign sig = {~zer,tmp[PSTWID-2-es:0]};
/ft816float/trunk/rtl/positVerilog/positMul.sv
29,7 → 29,7
 
module positMul(a, b, o, zero, inf);
`include "positSize.sv"
localparam rs = $clog2(PSTWID-1)-1;
localparam rs = $clog2(PSTWID-1);
input [PSTWID-1:0] a;
input [PSTWID-1:0] b;
output reg [PSTWID-1:0] o;
90,8 → 90,8
wire srxtmp = rxtmp[rs+es+1];
wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
// Compute the length of the regime bit string, +1 for positive regime
wire [rs:0] rgml = srxtmp ? rxtmp2c[rs+es:es] : rxtmp2c[rs+es:es] + 2'd1;
//assign r_o = (~exp_o[es+Bs+1] || |(exp_oN[es-1:0])) ? exp_oN[es+Bs:es] + 1 : exp_oN[es+Bs:es];
wire [rs+es+1:0] rxn = rxtmp[rs+es+1] ? rxtmp2c : rxtmp;
wire [rs:0] rgml = (~srxtmp | |(rxn[es-1:0])) ? rxtmp2c[rs+es:es] + 2'd1 : rxtmp2c[rs+es:es];
// Build expanded posit number:
// trim one leading bit off the product bits
// and keep guard, round bits, and create sticky bit
100,7 → 100,7
wire [PSTWID*3-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgml;
 
// Rounding
// Gaurd, Round, and Sticky
// Guard, Round, and Sticky
wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
ulp = ((G & (R | St)) | (L & G & ~(R | St)));
wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
/ft816float/trunk/rtl/positVerilog/positSqrt.sv
9,14 → 9,7
// - posit number square root function
// - parameterized width
//
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
// This function currently only seems to work with even sizes of
// exponents.
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
68,6 → 61,14
);
 
assign so = si; // square root of positive numbers only
// Compute length of significand. This length is needed to align the
// significand input to the square root module.
//wire [rs+1:0] rgml1 = rgsi ? rgmi + 2'd2 : rgmi + 2'd1;
//wire [rs+1:0] sigl = PSTWID-rgml1-es-1;
// The length could be zero or less
//wire [rs:0] sigl1 = sigl[rs+1] ? {rs{1'b0}} : sigl;
 
// Compute exponent
wire [rs+1:0] rgm1 = rgsi ? rgmi : -rgmi;
wire [rs+es+1:0] rx1 = {rgm1,expi};
// If exponent is odd, make it even. May need to shift the significand later.
76,7 → 77,7
assign sqrinf = infi;
assign sqrneg = so;
// If the exponent was made even, shift the significand left.
wire [PSTWID-1:0] sig1 = rx1[0] ? {sigi,1'b0} : {1'b0,sigi};
wire [PSTWID-1:0] sig1 = (rx1[0] ^ ~es[0]) ? {sigi,1'b0} : {1'b0,sigi};
 
wire ldd;
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(start), .o(ldd));
91,7 → 92,8
.clk(clk),
.ce(ce),
.ld(ldd),
.a({sig1,{(PSTWID/2+1-(PSTWID%2)){1'b0}}}),
// Align the input according to odd/even length
.a({sig1,{PSTWID/2{1'b0}}}),
.o(sqrto),
.done(done),
.lzcnt(lzcnt)

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