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URL https://opencores.org/ocsvn/ps2/ps2/trunk

Subversion Repositories ps2

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Rev 40 → Rev 41

/trunk/sim/rtl_sim/log/ncelab.log
0,0 → 1,56
TOOL: ncelab 04.10-b001: Started on Nov 30, 2003 at 12:53:31
ncelab
-f ncelab.args
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-LOGFILE ../log/ncelab.log
-TIMESCALE 1ns/100ps
-SNAPSHOT worklib.ps2_test_bench:rtl
-NO_TCHK_MSG
-ACCESS +RWC
worklib.ps2_test_bench
 
Elaborating the design hierarchy:
Caching library 'worklib' ....... Done
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.WB_MASTER32:v <0x285dcd5e>
streams: 14, words: 37673
worklib.WB_MASTER_BEHAVIORAL:v <0x4011829a>
streams: 6, words: 64972
worklib.ps2_io_ctrl:v <0x1a9cfb7e>
streams: 7, words: 4237
worklib.ps2_keyboard:v <0x48cda7c5>
streams: 107, words: 77889
worklib.ps2_keyboard_model:v <0x64c1328f>
streams: 13, words: 19418
worklib.ps2_sim_top:v <0x3261324c>
streams: 4, words: 1087
worklib.ps2_test_bench:v <0x1e73bec9>
streams: 46, words: 159235
worklib.ps2_top:v <0x758f909c>
streams: 3, words: 782
worklib.ps2_translation_table:v <0x726febd5>
streams: 14, words: 9671
worklib.ps2_wb_if:v <0x2138f2f1>
streams: 101, words: 78860
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 10 10
Primitives: 2 1
Registers: 254 254
Scalar wires: 74 -
Expanded wires: 32 1
Vectored wires: 16 -
Always blocks: 41 41
Initial blocks: 4 4
Parallel blocks: 14 14
Cont. assignments: 40 56
Pseudo assignments: 5 59
Simulation timescale: 1ps
Writing initial simulation snapshot: worklib.ps2_test_bench:rtl
TOOL: ncelab 04.10-b001: Exiting on Nov 30, 2003 at 12:53:33 (total: 00:00:02)
/trunk/sim/rtl_sim/log/ncvlog.log
0,0 → 1,59
TOOL: ncvlog 04.10-b001: Started on Nov 30, 2003 at 12:53:30
ncvlog
-f ncvlog.args
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-MESSAGES
-INCDIR ../../../bench/verilog
-INCDIR ../../../rtl/verilog
-NOCOPYRIGHT
-LOGFILE ../log/ncvlog.log
-DEFINE PS2_NUM_OF_NORMAL_SCANCODES 85
-DEFINE PS2_NUM_OF_EXTENDED_SCANCODES 38
-DEFINE SIM
../../../rtl/verilog/ps2_keyboard.v
../../../rtl/verilog/ps2_mouse.v
../../../rtl/verilog/ps2_top.v
../../../rtl/verilog/ps2_translation_table.v
../../../rtl/verilog/ps2_wb_if.v
../../../rtl/verilog/ps2_io_ctrl.v
../../../bench/verilog/ps2_keyboard_model.v
../../../bench/verilog/ps2_test_bench.v
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../bench/verilog/ps2_sim_top.v
 
file: ../../../rtl/verilog/ps2_keyboard.v
module worklib.ps2_keyboard:v
errors: 0, warnings: 0
file: ../../../rtl/verilog/ps2_mouse.v
module worklib.ps2_mouse:v
errors: 0, warnings: 0
file: ../../../rtl/verilog/ps2_top.v
module worklib.ps2_top:v
errors: 0, warnings: 0
file: ../../../rtl/verilog/ps2_translation_table.v
module worklib.ps2_translation_table:v
errors: 0, warnings: 0
file: ../../../rtl/verilog/ps2_wb_if.v
module worklib.ps2_wb_if:v
errors: 0, warnings: 0
file: ../../../rtl/verilog/ps2_io_ctrl.v
module worklib.ps2_io_ctrl:v
errors: 0, warnings: 0
file: ../../../bench/verilog/ps2_keyboard_model.v
module worklib.ps2_keyboard_model:v
errors: 0, warnings: 0
file: ../../../bench/verilog/ps2_test_bench.v
module worklib.ps2_test_bench:v
errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master32.v
module worklib.WB_MASTER32:v
errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master_behavioral.v
module worklib.WB_MASTER_BEHAVIORAL:v
errors: 0, warnings: 0
file: ../../../bench/verilog/ps2_sim_top.v
module worklib.ps2_sim_top:v
errors: 0, warnings: 0
TOOL: ncvlog 04.10-b001: Exiting on Nov 30, 2003 at 12:53:30 (total: 00:00:00)
/trunk/sim/rtl_sim/log/ncsim.log
0,0 → 1,27
TOOL: ncsim 04.10-b001: Started on Nov 30, 2003 at 12:53:34
ncsim
-LICQUEUE
-f ./ncsim.args
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-INPUT ncsim.tcl
-LOGFILE ../log/ncsim.log
worklib.ps2_test_bench:rtl
 
Loading snapshot worklib.ps2_test_bench:rtl .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> database -open waves -shm -into ../out/waves.shm
Created SHM database waves
ncsim> probe -create -database waves ps2_test_bench -shm -all -depth all
Created probe 1
ncsim> run
 
 
status: Testbench done
report (deaddead)
exit (00000000)
/projects/highland/gorand/tmp/ps2/bench/verilog/ps2_test_bench.v:289 $finish(0);
ncsim> quit
TOOL: ncsim 04.10-b001: Exiting on Nov 30, 2003 at 13:02:41 (total: 00:09:07)

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