URL
https://opencores.org/ocsvn/raptor64/raptor64/trunk
Subversion Repositories raptor64
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 40 to Rev 41
- ↔ Reverse comparison
Rev 40 → Rev 41
/raptor64/trunk/rtl/verilog/Raptor64_shift.v
27,16 → 27,17
// |
//============================================================================= |
// |
module Raptor64_shift(xIR, a, b, mask, o); |
input [41:0] xIR; |
module Raptor64_shift(xIR, a, b, mask, o, rolo); |
input [31:0] xIR; |
input [63:0] a; |
input [63:0] b; |
input [63:0] mask; |
output [63:0] o; |
reg [63:0] o; |
output [63:0] rolo; |
|
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xFunc = xIR[6:0]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [5:0] xFunc = xIR[5:0]; |
wire [4:0] xFunc5 = xIR[4:0]; |
|
wire [127:0] shlxo = {64'd0,a} << b[5:0]; |
43,7 → 44,7
wire [127:0] shruxo = {a,64'd0} >> b[5:0]; |
wire [63:0] shlo = shlxo[63:0]; |
wire [63:0] shruo = shruxo[127:64]; |
wire [63:0] rolo = {shlxo[127:64]|shlxo[63:0]}; |
assign rolo = {shlxo[127:64]|shlxo[63:0]}; |
wire [63:0] roro = {shruxo[127:64]|shruxo[63:0]}; |
wire [63:0] shro = ~(~a >> b[5:0]); |
|
52,6 → 53,7
`RR: |
case(xFunc) |
`SHL: o = shlo; |
`SHLU: o = shlo; |
`SHRU: o = shruo; |
`ROL: o = rolo; |
`ROR: o = roro; |
62,6 → 64,7
`SHFTI: |
case(xFunc5) |
`SHLI: o = shlo; |
`SHLUI: o = shlo; |
`SHRUI: o = shruo; |
`ROLI: o = rolo; |
`RORI: o = roro; |
/raptor64/trunk/rtl/verilog/Raptor64_BranchHistory.v
2,7 → 2,7
`timescale 1ns / 1ps |
//============================================================================= |
// __ |
// \\__/ o\ (C) 2011,2012 Robert Finch |
// \\__/ o\ (C) 2011-2013 Robert Finch, Stratford |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@opencores.org |
// || |
30,7 → 30,7
input rst; |
input clk; |
input advanceX; |
input [41:0] xIR; |
input [31:0] xIR; |
input [63:0] pc; |
input [63:0] xpc; |
input takb; |
45,14 → 45,14
for (n = 0; n < 256; n = n + 1) |
branch_history_table[n] = 0; |
end |
wire [7:0] bht_wa = {xpc[5:0],gbl_branch_hist[2:1]}; // write address |
wire [7:0] bht_ra1 = {xpc[5:0],gbl_branch_hist[2:1]}; // read address (EX stage) |
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage) |
wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]}; // write address |
wire [7:0] bht_ra1 = {xpc[7:2],gbl_branch_hist[2:1]}; // read address (EX stage) |
wire [7:0] bht_ra2 = {pc[7:2],gbl_branch_hist[2:1]}; // read address (IF stage) |
wire [1:0] bht_xbits = branch_history_table[bht_ra1]; |
wire [1:0] bht_ibits = branch_history_table[bht_ra2]; |
assign predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1; |
|
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI || |
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI || |
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI) |
/raptor64/trunk/rtl/verilog/insn_dumpsc.v
1,5 → 1,6
$display("Fetched pc=%h.%h insn: %h", {pc[63:4],4'h0},pc[3:2], insn); |
casex(insn[41:35]) |
// $display("%d Fetched pc=%h.%h insn: %h", $time, {pc[63:4],4'h0},pc[3:2], insn); |
$display("Fetched pc=%h insn: %h", {pc[63:2],2'h0}, insn); |
casex(insn[31:25]) |
`MISC: |
begin |
$display("MISC"); |
20,93 → 21,131
endcase |
end |
`R: |
case(insn[6:0]) |
case(insn[5:0]) |
// `SGN: $display("SGN"); |
`NEG: $display("NEG r%d,r%d",insn[29:25],insn[34:30]); |
`COM: $display("COM r%d,r%d",insn[29:25],insn[34:30]); |
`ABS: $display("ABS r%d,r%d",insn[29:25],insn[34:30]); |
`SQRT: $display("SQRT r%d,r%d",insn[29:25],insn[34:30]); |
`OMGI: $display("OMG r%d,#%d",insn[29:25],insn[12:7]); |
`NEG: $display("NEG r%d,r%d",insn[19:15],insn[24:20]); |
`COM: $display("COM r%d,r%d",insn[19:15],insn[24:20]); |
`ABS: $display("ABS r%d,r%d",insn[19:15],insn[24:20]); |
`SQRT: $display("SQRT r%d,r%d",insn[19:15],insn[24:20]); |
`OMGI: $display("OMG r%d,#%d",insn[19:15],insn[12:7]); |
`MOV: $display("MOV r%r,r%d",insn[19:15],insn[24:20]); |
default: ; |
endcase |
`RR: |
case(insn[6:0]) |
`ADD: $display("ADD r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`ADDU: $display("ADDU r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`SUB: $display("SUB r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`SUBU: $display("SUBU r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`CMP: $display("CMP r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`AND: $display("AND r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`ANDC: $display("ANDC r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`OR: $display("OR r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`ORC: $display("ORC r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`XOR: $display("XOR r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`NAND: $display("NAND r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`NOR: $display("NOR r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`XNOR: $display("XNOR r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
`MULU: $display("MULU r%d,r%d,r%d",insn[24:20],insn[34:30],insn[29:25]); |
case(insn[5:0]) |
`ADD: $display("ADD r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`ADDU: $display("ADDU r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`SUB: $display("SUB r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`SUBU: $display("SUBU r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`CMP: $display("CMP r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`AND: $display("AND r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`ANDC: $display("ANDC r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`OR: $display("OR r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`ORC: $display("ORC r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`XOR: $display("XOR r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`NAND: $display("NAND r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`NOR: $display("NOR r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`XNOR: $display("XNOR r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
`MULU: $display("MULU r%d,r%d,r%d",insn[14:10],insn[24:20],insn[19:15]); |
default: ; |
endcase |
`SHFTI: |
case(insn[4:0]) |
`SHLI: $display("SHLI r%d,r%d,#%d",insn[29:25],insn[34:30],insn[24:19]); |
`SHRUI: $display("SHRUI r%d,r%d,#%d",insn[29:25],insn[34:30],insn[24:19]); |
`SHRI: $display("SHRI r%d,r%d,#%d",insn[29:25],insn[34:30],insn[24:19]); |
`ROLI: $display("ROLI r%d,r%d,#%d",insn[29:25],insn[34:30],insn[24:19]); |
`RORI: $display("RORI r%d,r%d,#%d",insn[29:25],insn[34:30],insn[24:19]); |
`ROLAMI: $display("ROLAMI r%d,r%d,#%d",insn[29:25],insn[34:30],insn[24:19]); |
`SHLI: $display("SHLI r%d,r%d,#%d",insn[19:15],insn[24:20],insn[14:9]); |
`SHRUI: $display("SHRUI r%d,r%d,#%d",insn[19:15],insn[24:20],insn[14:9]); |
`SHRI: $display("SHRI r%d,r%d,#%d",insn[19:15],insn[24:20],insn[14:9]); |
`ROLI: $display("ROLI r%d,r%d,#%d",insn[19:15],insn[24:20],insn[14:9]); |
`RORI: $display("RORI r%d,r%d,#%d",insn[19:15],insn[24:20],insn[14:9]); |
`ROLAMI: $display("ROLAMI r%d,r%d,#%d",insn[19:15],insn[24:20],insn[14:9]); |
endcase |
`BTRR: |
case(insn[4:0]) |
`BEQ: $display("BEQ r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BNE: $display("BNE r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BLT: $display("BLT r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BLE: $display("BLE r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BGT: $display("BGT r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BGE: $display("BGE r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BLTU: $display("BLTU r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BLEU: $display("BLEU r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BGTU: $display("BGTU r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BGEU: $display("BGEU r%d,r%d,%h.%h)",insn[34:30],insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BRA: $display("BRA %h.%h)",{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`LOOP: $display("LOOP r%d,%h.%h)",insn[29:25],{{44{insn[24]}},insn[24:7]},insn[6:5]); |
`BEQ: $display("BEQ r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BNE: $display("BNE r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BLT: $display("BLT r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BLE: $display("BLE r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BGT: $display("BGT r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BGE: $display("BGE r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BLTU: $display("BLTU r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BLEU: $display("BLEU r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BGTU: $display("BGTU r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BGEU: $display("BGEU r%d,r%d,%h)",insn[24:20],insn[19:15],{{54{insn[14]}},insn[14:5]}); |
`BRA: $display("BRA %h)",{{54{insn[14]}},insn[14:5]}); |
`LOOP: $display("LOOP r%d,%h)",insn[19:15],{{54{insn[14]}},insn[14:5]}); |
default: ; |
endcase |
`SETLO: $display("SETLO r%d,#%h", insn[36:32],{{32{insn[31]}},insn[31:0]}); |
`ADDI: $display("ADDI r%d,r%d,#%d",insn[29:25],insn[34:30],{{39{insn[24]}},insn[24:0]}); |
`ADDUI: $display("ADDUI r%d,r%d,#%d",insn[29:25],insn[34:30],{{39{insn[24]}},insn[24:0]}); |
`SUBI: $display("SUBI r%d,r%d,#%d",insn[29:25],insn[34:30],{{39{insn[24]}},insn[24:0]}); |
`SUBUI: $display("SUBUI r%d,r%d,#%d",insn[29:25],insn[34:30],{{39{insn[24]}},insn[24:0]}); |
`ANDI: $display("ANDI r%d,r%d,#%d",insn[29:25],insn[34:30],{39'h7FFFFFFFFF,insn[24:0]}); |
`ORI: $display("ORI r%d,r%d,#%d",insn[29:25],insn[34:30],{39'd0,insn[24:0]}); |
`XORI: $display("XORI r%d,r%d,#%d",insn[29:25],insn[34:30],{39'd0,insn[24:0]}); |
`JMP: $display("JMP %h.%d",{insn[34:2],4'b0000},insn[1:0]); |
`CALL: $display("CALL %h.%d",{insn[34:2],4'b0000},insn[1:0]); |
`SETLO: $display("SETLO r%d,#%h", insn[26:22],insn[21:0]); |
`SETMID: $display("SETMID r%d,#%h", insn[26:22],insn[21:0]); |
`SETHI: $display("SETHI r%d,#%h", insn[26:22],insn[19:0]); |
`ADDI: $display("ADDI r%d,r%d,#%d",insn[19:15],insn[24:20],{{49{insn[14]}},insn[14:0]}); |
`ADDUI: $display("ADDUI r%d,r%d,#%d",insn[19:15],insn[24:20],{{49{insn[14]}},insn[14:0]}); |
`SUBI: $display("SUBI r%d,r%d,#%d",insn[19:15],insn[24:20],{{49{insn[14]}},insn[14:0]}); |
`SUBUI: $display("SUBUI r%d,r%d,#%d",insn[19:15],insn[24:20],{{49{insn[14]}},insn[14:0]}); |
`ANDI: $display("ANDI r%d,r%d,#%d",insn[19:15],insn[24:20],{{49{insn[14]}},insn[14:0]}); |
`ORI: $display("ORI r%d,r%d,#%d",insn[19:15],insn[24:20],{49'd0,insn[14:0]}); |
`XORI: $display("XORI r%d,r%d,#%d",insn[19:15],insn[24:20],{49'd0,insn[14:0]}); |
`JMP: $display("JMP %h",{insn[24:0],2'b00}); |
`CALL: $display("CALL %h",{insn[24:0],2'b00}); |
`JAL: $display("JAL"); |
`RET: $display("RET R%d,R%d,#%h",insn[34:30],insn[29:25],{{39{insn[24]}},insn[24:0]}); |
`BEQI: $display("BEQI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BNEI: $display("BNEI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BLTI: $display("BLTI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BLEI: $display("BLEI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BGTI: $display("BGTI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BGEI: $display("BGEI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BLTUI: $display("BLTUI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BLEUI: $display("BLEUI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BGTUI: $display("BGTUI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`BGEUI: $display("BGEUI r%d,#%d,%h.%h)",insn[34:30],insn[17:0],{{50{insn[29]}},insn[29:20]},insn[19:18]); |
`RET: $display("RET R%d,R%d,#%h",insn[24:20],insn[19:15],{{49{insn[14]}},insn[14:0]}); |
`BEQI: $display("BEQI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BNEI: $display("BNEI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BLTI: $display("BLTI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BLEI: $display("BLEI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BGTI: $display("BGTI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BGEI: $display("BGEI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BLTUI: $display("BLTUI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BLEUI: $display("BLEUI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BGTUI: $display("BGTUI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`BGEUI: $display("BGEUI r%d,#%d,%h)",insn[24:20],insn[7:0],{{50{insn[19]}},insn[19:8]}); |
`NOPI: $display("NOP"); |
`SB: $display("SB r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`SC: $display("SC r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`SH: $display("SH r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`SW: $display("SW r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LEA: $display("LEA r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LB: $display("LB r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LBU: $display("LBU r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LC: $display("LC r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LCU: $display("LCU r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LH: $display("LH r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LHU: $display("LHU r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
`LW: $display("LW r%d,%d[r%d]",insn[29:25],{{39{insn[24]}},insn[24:0]},insn[34:30]); |
7'b111xxxx: $display("IMM %h", {insn[38:0],25'd0}); |
`SB: $display("SB r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`SC: $display("SC r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`SH: $display("SH r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`SW: $display("SW r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LEA: $display("LEA r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LB: $display("LB r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LBU: $display("LBU r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LC: $display("LC r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LCU: $display("LCU r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LH: $display("LH r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LHU: $display("LHU r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`LW: $display("LW r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INB: $display("INB r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INBU: $display("INBU r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INCH: $display("INCH r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INCU: $display("INCU r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INH: $display("INH r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INHU: $display("INHU r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`INW: $display("INW r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`OUTB: $display("OUTB r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`OUTC: $display("OUTC r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`OUTH: $display("OUTH r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`OUTW: $display("OUTW r%d,%d[r%d]",insn[19:15],{{49{insn[24]}},insn[14:0]},insn[24:20]); |
`MEMNDX: |
case(insn[5:0]+32) |
`SB: $display("SB r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`SC: $display("SC r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`SH: $display("SH r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`SW: $display("SW r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LB: $display("LB r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LC: $display("LC r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LH: $display("LH r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LBU: $display("LBU r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LHU: $display("LHU r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LW: $display("LW r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`LEA: $display("LEA"); |
`OUTB: $display("OUTB r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`OUTC: $display("OUTC r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`OUTH: $display("OUTH r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`OUTW: $display("OUTW r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INB: $display("INB r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INCH: $display("INCH r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INH: $display("INH r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INW: $display("INW r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INBU: $display("INBU r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INCU: $display("INCU r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
`INHU: $display("INHU r%d,[r%d+r%d<<%d]",insn[14:10],insn[24:20],insn[19:15],insn[9:8]); |
endcase |
default: ; |
endcase |
/raptor64/trunk/rtl/verilog/Raptor64_bitfield.v
28,7 → 28,7
//============================================================================= |
// |
module Raptor64_bitfield(xIR, rolo, b, o, masko); |
input [41:0] xIR; |
input [31:0] xIR; |
input [63:0] rolo; |
input [63:0] b; |
output [63:0] o; |
36,14 → 36,14
output [63:0] masko; |
|
reg [63:0] o1; |
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [4:0] xFunc5 = xIR[4:0]; |
|
// generate mask |
reg [63:0] mask; |
assign masko = mask; |
wire [5:0] mb = xIR[12:7]; |
wire [5:0] me = xIR[18:13]; |
wire [5:0] mb = xIR[10:5]; |
wire [5:0] me = xIR[16:11]; |
integer nn,n; |
always @(mb or me or nn) |
for (nn = 0; nn < 64; nn = nn + 1) |
/raptor64/trunk/rtl/verilog/Raptor64_SetOperandRegs.v
23,6 → 23,9
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// |
// If a register field is not used by an instruction, then the register |
// selected is forced to r0 for that field. This causes load stalls to be |
// avoided, which would otherwise occur. |
//============================================================================= |
|
module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc); |
33,8 → 36,8
input advanceX; |
input [63:0] b; |
input [3:0] AXC; |
input [41:0] insn; |
input [41:0] xIR; |
input [31:0] insn; |
input [31:0] xIR; |
output [8:0] dRa; |
reg [8:0] dRa; |
output [8:0] dRb; |
42,9 → 45,10
output [8:0] dRc; |
reg [8:0] dRc; |
|
wire [6:0] iOpcode = insn[41:35]; |
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xFunc = xIR[6:0]; |
wire [6:0] iOpcode = insn[31:25]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [5:0] xFunc = xIR[5:0]; |
wire [6:0] iFunc7 = insn[6:0]; |
|
always @(posedge clk) |
if (rst) begin |
55,55 → 59,58
else begin |
if (advanceI) begin |
// Default settings, to be overridden |
dRa <= {AXC,insn[34:30]}; |
dRb <= {AXC,insn[29:25]}; |
dRc <= {AXC,insn[24:20]}; |
dRa <= {AXC,insn[24:20]}; |
dRb <= {AXC,insn[19:15]}; |
dRc <= {AXC,insn[14:10]}; |
casex(iOpcode) |
`MISC: |
case(iFunc7) |
`IRET: begin |
dRa <= {AXC,5'd25}; |
dRb <= 9'd0; |
dRc <= 9'd0; |
end |
`ERET: begin |
dRa <= {AXC,5'd24}; |
dRb <= 9'd0; |
dRc <= 9'd0; |
end |
default: |
begin |
dRa <= 9'd0; |
dRb <= 9'd0; |
dRc <= 9'd0; |
end |
endcase |
`CALL,`JMP,`NOPI: |
begin |
dRa <= 9'd0; |
dRb <= 9'd0; |
dRc <= 9'd0; |
end |
`RET: begin |
dRa <= {AXC,5'd30}; |
dRb <= {AXC,5'd31}; |
dRc <= 9'd0; |
end |
`SETLO: dRa <= {AXC,insn[36:32]}; |
`SETHI: dRa <= {AXC,insn[36:32]}; |
`SM,`LM: |
begin |
dRa <= {AXC,1'b1,insn[34:31]}; |
casex(insn[30:0]) |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: dRb <= {AXC,5'd1}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: dRb <= {AXC,5'd2}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: dRb <= {AXC,5'd3}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: dRb <= {AXC,5'd4}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: dRb <= {AXC,5'd5}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: dRb <= {AXC,5'd6}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: dRb <= {AXC,5'd7}; |
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: dRb <= {AXC,5'd8}; |
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: dRb <= {AXC,5'd9}; |
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: dRb <= {AXC,5'd10}; |
31'bxxxxxxxxxxxxxxxxxxxx10000000000: dRb <= {AXC,5'd11}; |
31'bxxxxxxxxxxxxxxxxxxx100000000000: dRb <= {AXC,5'd12}; |
31'bxxxxxxxxxxxxxxxxxx1000000000000: dRb <= {AXC,5'd13}; |
31'bxxxxxxxxxxxxxxxxx10000000000000: dRb <= {AXC,5'd14}; |
31'bxxxxxxxxxxxxxxxx100000000000000: dRb <= {AXC,5'd15}; |
31'bxxxxxxxxxxxxxxx1000000000000000: dRb <= {AXC,5'd16}; |
31'bxxxxxxxxxxxxxx10000000000000000: dRb <= {AXC,5'd17}; |
31'bxxxxxxxxxxxxx100000000000000000: dRb <= {AXC,5'd18}; |
31'bxxxxxxxxxxxx1000000000000000000: dRb <= {AXC,5'd19}; |
31'bxxxxxxxxxxx10000000000000000000: dRb <= {AXC,5'd20}; |
31'bxxxxxxxxxx100000000000000000000: dRb <= {AXC,5'd21}; |
31'bxxxxxxxxx1000000000000000000000: dRb <= {AXC,5'd22}; |
31'bxxxxxxxx10000000000000000000000: dRb <= {AXC,5'd23}; |
31'bxxxxxxx100000000000000000000000: dRb <= {AXC,5'd24}; |
31'bxxxxxx1000000000000000000000000: dRb <= {AXC,5'd25}; |
31'bxxxxx10000000000000000000000000: dRb <= {AXC,5'd26}; |
31'bxxxx100000000000000000000000000: dRb <= {AXC,5'd27}; |
31'bxxx1000000000000000000000000000: dRb <= {AXC,5'd28}; |
31'bxx10000000000000000000000000000: dRb <= {AXC,5'd29}; |
31'bx100000000000000000000000000000: dRb <= {AXC,5'd30}; |
31'b1000000000000000000000000000000: dRb <= {AXC,5'd31}; |
default: dRb <= {AXC,5'd0}; |
endcase |
end |
default: dRa <= {AXC,insn[34:30]}; |
`BLTI,`BLEI,`BGTI,`BGEI, |
`BLTUI,`BLEUI,`BGTUI,`BGEUI, |
`BEQI,`BNEI: |
begin |
dRb <= 9'd0; |
dRc <= 9'd0; |
end |
`SLTI,`SLEI,`SGTI,`SGEI, |
`SLTUI,`SLEUI,`SGTUI,`SGEUI, |
`SEQI,`SNEI: |
begin |
dRb <= 9'd0; |
dRc <= 9'd0; |
end |
`SETLO: dRa <= {AXC,insn[26:22]}; |
`SETMID: dRa <= {AXC,insn[26:22]}; |
`SETHI: dRa <= {AXC,insn[26:22]}; |
default: dRa <= {AXC,insn[24:20]}; |
endcase |
end |
else if (advanceR) begin |
115,9 → 122,9
if (advanceX) begin |
if (xOpcode==`R) begin |
if (xFunc==`EXEC) begin |
dRa <= b[34:30]; |
dRb <= b[29:25]; |
dRc <= b[24:20]; |
dRa <= b[24:20]; |
dRb <= b[19:15]; |
dRc <= b[14:10]; |
end |
end |
end |
/raptor64/trunk/rtl/verilog/cntlz.v
0,0 → 1,117
// ============================================================================ |
// (C) 2012 Robert Finch |
// robfinch@<remove>opencores.org |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// ============================================================================ |
// |
module cntlz8( |
input clk, |
input [7:0] i, |
output reg [3:0] o |
); |
|
always @(posedge clk) |
casex (i) |
8'b00000000: o = 8; |
8'b00000001: o = 7; |
8'b0000001x: o = 6; |
8'b000001xx: o = 5; |
8'b00001xxx: o = 4; |
8'b0001xxxx: o = 3; |
8'b001xxxxx: o = 2; |
8'b01xxxxxx: o = 1; |
8'b1xxxxxxx: o = 0; |
endcase |
|
endmodule |
|
|
module cntlz16( |
input clk, |
input [15:0] i, |
output reg [4:0] o |
); |
wire [3:0] cnt1, cnt2; |
|
cntlz8 u1 (clk,i[ 7:0],cnt1); |
cntlz8 u2 (clk,i[15:8],cnt2); |
|
always @(posedge clk) |
o <= cnt2[3] ? cnt1 + 4'h8 : cnt2; |
|
endmodule |
|
|
// 88 slices / 154 LUTs / 22.5 ns |
module cntlz64( |
input clk, |
input [63:0] i, |
output reg [6:0] o |
); |
|
wire [4:0] cnt1, cnt2, cnt3, cnt4; |
|
cntlz16 u1 (clk,i[15: 0],cnt1); |
cntlz16 u2 (clk,i[31:16],cnt2); |
cntlz16 u3 (clk,i[47:32],cnt3); |
cntlz16 u4 (clk,i[63:48],cnt4); |
|
always @(posedge clk) |
o <= |
!cnt4[4] ? cnt4 : |
!cnt3[4] ? cnt3 + 7'd16 : |
!cnt2[4] ? cnt2 + 7'd32 : |
cnt1 + 7'd48; |
|
endmodule |
|
|
|
// 5 slices / 10 LUTs / 7.702 ns |
module cntlo8( |
input clk, |
input [7:0] i, |
output [3:0] o |
); |
|
cntlz8 u1 (clk,~i,o); |
|
endmodule |
|
|
module cntlo16( |
input clk, |
input [15:0] i, |
output [4:0] o |
); |
|
cntlz16 u1 (clk,~i,o); |
|
endmodule |
|
|
// 59 slices / 99 LUTs / 14.065 ns |
module cntlo64( |
input clk, |
input [63:0] i, |
output [6:0] o |
); |
|
cntlz64 u1 (clk,~i,o); |
|
endmodule |
|
|
/raptor64/trunk/rtl/verilog/Raptor64_set.v
28,7 → 28,7
//============================================================================= |
// |
module Raptor64_set(xIR, a, b, imm, o); |
input [41:0] xIR; |
input [31:0] xIR; |
input [63:0] a; |
input [63:0] b; |
input [63:0] imm; |
35,8 → 35,8
output [63:0] o; |
reg [63:0] o; |
|
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xFunc = xIR[6:0]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [5:0] xFunc = xIR[5:0]; |
|
wire eqi = a==imm; |
wire lti = $signed(a) < $signed(imm); |
/raptor64/trunk/rtl/verilog/Raptor64_opcodes.v
40,8 → 40,8
`define DCACHE_ON 7'd12 |
`define DCACHE_OFF 7'd13 |
`define PCCAP_OFF 7'd14 |
`define IEPP 7'd15 |
`define FIP 7'd20 |
`define SYSJMP 7'd22 |
`define SYSCALL 7'd23 |
`define IRET 7'd32 |
`define ERET 7'd33 |
55,24 → 55,24
`define GRAN 7'd80 |
`define GRAFD 7'd82 |
`define R 7'd1 |
`define COM 7'd4 |
`define NOT 7'd5 |
`define NEG 7'd6 |
`define ABS 7'd7 |
`define SGN 7'd8 |
`define MOV 7'd9 |
`define SWAP 7'd13 |
`define CTLZ 7'd16 |
`define CTLO 7'd17 |
`define CTPOP 7'd18 |
`define SEXT8 7'd19 |
`define SEXT16 7'd20 |
`define SEXT32 7'd21 |
`define SQRT 7'd24 |
`define REDOR 7'd30 |
`define REDAND 7'd31 |
`define MFSPR 7'd40 |
`define MTSPR 7'd41 |
`define COM 6'd4 |
`define NOT 6'd5 |
`define NEG 6'd6 |
`define ABS 6'd7 |
`define SGN 6'd8 |
`define MOV 6'd9 |
`define SWAP 6'd13 |
`define CTLZ 6'd16 |
`define CTLO 6'd17 |
`define CTPOP 6'd18 |
`define SEXT8 6'd19 |
`define SEXT16 6'd20 |
`define SEXT32 6'd21 |
`define SQRT 6'd24 |
`define REDOR 6'd30 |
`define REDAND 6'd31 |
`define MFSPR 6'd40 |
`define MTSPR 6'd41 |
`define SR 6'd00 |
`define TLBIndex 6'd01 |
`define TLBRandom 6'd02 |
103,62 → 103,67
`define INSNKEY 6'd37 |
`define PCHI 6'd62 |
`define PCHISTORIC 6'd63 |
`define OMG 7'd50 |
`define CMG 7'd51 |
`define OMGI 7'd52 |
`define CMGI 7'd53 |
`define EXEC 7'd58 |
`define MYST 7'd59 |
`define OMG 6'd50 |
`define CMG 6'd51 |
`define OMGI 6'd52 |
`define CMGI 6'd53 |
`define EXEC 6'd58 |
`define RR 7'd2 |
`define ADD 7'd2 |
`define ADDU 7'd3 |
`define SUB 7'd4 |
`define SUBU 7'd5 |
`define CMP 7'd6 |
`define CMPU 7'd7 |
`define AND 7'd8 |
`define OR 7'd9 |
`define XOR 7'd10 |
`define ANDC 7'd11 |
`define NAND 7'd12 |
`define NOR 7'd13 |
`define XNOR 7'd14 |
`define ORC 7'd15 |
`define MIN 7'd20 |
`define MAX 7'd21 |
`define MULU 7'd24 |
`define MULS 7'd25 |
`define DIVU 7'd26 |
`define DIVS 7'd27 |
`define MODU 7'd28 |
`define MODS 7'd29 |
`define MOVZ 7'd30 |
`define MOVNZ 7'd31 |
`define ADD 6'd2 |
`define ADDU 6'd3 |
`define SUB 6'd4 |
`define SUBU 6'd5 |
`define CMP 6'd6 |
`define CMPU 6'd7 |
`define AND 6'd8 |
`define OR 6'd9 |
`define XOR 6'd10 |
`define ANDC 6'd11 |
`define NAND 6'd12 |
`define NOR 6'd13 |
`define XNOR 6'd14 |
`define ORC 6'd15 |
`define MIN 6'd20 |
`define MAX 6'd21 |
`define MULU 6'd24 |
`define MULS 6'd25 |
`define DIVU 6'd26 |
`define DIVS 6'd27 |
`define MODU 6'd28 |
`define MODS 6'd29 |
`define MOVZ 6'd30 |
`define MOVNZ 6'd31 |
`define MOVPL 6'd32 |
`define MOVMI 6'd33 |
|
`define SHL 7'd40 |
`define SHRU 7'd41 |
`define ROL 7'd42 |
`define ROR 7'd43 |
`define SHR 7'd44 |
`define ROLAM 7'd45 |
`define SHL 6'd40 |
`define SHRU 6'd41 |
`define ROL 6'd42 |
`define ROR 6'd43 |
`define SHR 6'd44 |
`define ROLAM 6'd45 |
`define SHLU 6'd46 |
|
`define NOP 7'd60 |
//`define NOP 7'd60 |
|
`define SLT 7'd96 |
`define SLE 7'd97 |
`define SGT 7'd98 |
`define SGE 7'd99 |
`define SLTU 7'd100 |
`define SLEU 7'd101 |
`define SGTU 7'd102 |
`define SGEU 7'd103 |
`define SEQ 7'd104 |
`define SNE 7'd105 |
`define SLT 6'd48 |
`define SLE 6'd49 |
`define SGT 6'd50 |
`define SGE 6'd51 |
`define SLTU 6'd52 |
`define SLEU 6'd53 |
`define SGTU 6'd54 |
`define SGEU 6'd55 |
`define SEQ 6'd56 |
`define SNE 6'd57 |
|
`define BCD_MUL 7'd109 |
`define BCD_ADD 7'd110 |
`define BCD_SUB 7'd111 |
`define MTEP 6'd58 |
`define MFEP 6'd59 |
|
`define BCD_MUL 6'd60 |
`define BCD_ADD 6'd61 |
`define BCD_SUB 6'd62 |
|
`define SHFTI 7'd3 |
`define SHLI 5'd0 |
`define SHRUI 5'd1 |
166,6 → 171,7
`define SHRI 5'd3 |
`define RORI 5'd4 |
`define ROLAMI 5'd5 |
`define SHLUI 5'd6 |
`define BFINS 5'd8 |
`define BFSET 5'd9 |
`define BFCLR 5'd10 |
212,14 → 218,13
`define TGTUI 5'd9 |
`define TRAI 5'd10 |
`define TRNI 5'd11 |
// SETLO=20 to 23 |
`define SETLO 7'b00101xx |
`define MUX 7'd22 |
`define MYST 7'd23 |
`define CALL 7'd24 |
`define JMP 7'd25 |
`define JAL 7'd26 |
`define RET 7'd27 |
// SETLO=28 to 31 |
`define SETHI 7'b00111xx |
`define LB 7'd32 |
`define LC 7'd33 |
`define LH 7'd34 |
308,8 → 313,12
`define OUTH 7'd74 |
`define OUTW 7'd75 |
`define CACHE 7'd76 |
`define INVIL 5'd0 |
`define INVIALL 5'd1 |
`define INVIL 5'd0 |
`define INVIALL 5'd1 |
`define ICACHEON 5'd14 |
`define ICACHEOFF 5'd15 |
`define DCACHEON 5'd30 |
`define DCACHEOFF 5'd31 |
`define LEA 7'd77 |
`define LM 7'd78 |
`define SM 7'd79 |
402,7 → 411,9
`define FPZL 7'd110 |
`define NOPI 7'd111 |
|
`define IMM 3'd7 |
`define SETLO 7'b11100xx |
`define SETMID 7'b11101xx |
`define SETHI 7'b11110xx |
|
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000 |
`define NOP_INSN 32'b1101111_0_00000000_00000000_00000000 |
|
/raptor64/trunk/rtl/verilog/Raptor64_logic.v
28,7 → 28,7
//============================================================================= |
// |
module Raptor64_logic(xIR, a, b, imm, o); |
input [41:0] xIR; |
input [31:0] xIR; |
input [63:0] a; |
input [63:0] b; |
input [63:0] imm; |
35,8 → 35,8
output [63:0] o; |
reg [63:0] o; |
|
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xFunc = xIR[6:0]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [5:0] xFunc = xIR[5:0]; |
|
always @(xOpcode or xFunc or a or b or imm) |
case (xOpcode) |
/raptor64/trunk/rtl/verilog/lib/math/BCDMath.v
1,5 → 1,30
|
|
`timescale 1ns / 1ps |
//============================================================================= |
// __ |
// \\__/ o\ (C) 2012 Robert Finch |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@opencores.org |
// || |
// |
// BCDMath.v |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// |
//============================================================================= |
// |
module BCDAdd(ci,a,b,o,c); |
input ci; // carry input |
input [7:0] a; |
61,6 → 86,7
5'h10: begin o = 4'h6; c = 1'b1; end |
5'h11: begin o = 4'h7; c = 1'b1; end |
5'h12: begin o = 4'h8; c = 1'b1; end |
5'h13: begin o = 4'h9; c = 1'b1; end |
default: begin o = 4'h9; c = 1'b1; end |
endcase |
endmodule |
83,6 → 109,7
5'h7: begin o = 4'h7; c = 1'b0; end |
5'h8: begin o = 4'h8; c = 1'b0; end |
5'h9: begin o = 4'h9; c = 1'b0; end |
5'h16: begin 0 = 4'h0; c = 1'b1; end |
5'h17: begin o = 4'h1; c = 1'b1; end |
5'h18: begin o = 4'h2; c = 1'b1; end |
5'h19: begin o = 4'h3; c = 1'b1; end |
/raptor64/trunk/rtl/verilog/Raptor64_addsub.v
28,7 → 28,7
//============================================================================= |
// |
module Raptor64_addsub(xIR, a, b, imm, o); |
input [41:0] xIR; |
input [31:0] xIR; |
input [63:0] a; |
input [63:0] b; |
input [63:0] imm; |
35,8 → 35,8
output [63:0] o; |
reg [63:0] o; |
|
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xFunc = xIR[6:0]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [5:0] xFunc = xIR[5:0]; |
wire [7:0] bcdaddo,bcdsubo; |
|
BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c()); |
/raptor64/trunk/rtl/verilog/Raptor64_tb.v
29,7 → 29,7
wire [15:0] pic_dato; |
wire tc_ack; |
wire pic_ack; |
reg pulse1000Hz; |
reg pulse1000Hz,pulse100Hz; |
|
wire uart_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_0A); |
wire rast_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDA_01); |
36,13 → 36,17
wire AC97_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_10); |
wire spr_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hD8); |
wire Led_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_06); |
wire dt_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_04); |
wire p100ack = sys_iocyc && sys_stb && (sys_adr[63:0]==64'hFFFFFFFF_FFFF0010); |
wire p1000ack = sys_iocyc && sys_stb && (sys_adr[63:0]==64'hFFFFFFFF_FFFF0000); |
|
assign ram_ack = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1); |
assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|AC97_ack|spr_ack|Led_ack; |
assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|AC97_ack|spr_ack|Led_ack|dt_ack|p100ack|p1000ack; |
|
initial begin |
clk = 1; |
pulse1000Hz = 0; |
pulse100Hz = 0; |
rst = 0; |
nmi = 0; |
#100 rst = 1; |
51,23 → 55,32
#100 nmi = 0; |
end |
|
always #10 clk = ~clk; // 50 MHz |
always #290930 pulse1000Hz = 1; |
always #20 clk = ~clk; // 25 MHz |
always #29930 pulse1000Hz = 1; |
always #130 pulse1000Hz = 0; |
always #299030 pulse100Hz = 1; |
always #130 pulse100Hz = 0; |
|
|
reg pulse1000HzB; |
reg pulse1000HzB,pulse100HzB; |
always @(posedge clk) |
if (rst) begin |
pulse1000HzB <= 1'b0; |
pulse100HzB <= 1'b0; |
end |
else begin |
if (pulse1000Hz) |
pulse1000HzB <= 1'b1; |
else begin |
if (sys_adr==64'hFFFFFFFF_FFFF0000) |
if (p1000ack) |
pulse1000HzB <= 1'b0; |
end |
if (pulse100Hz) |
pulse100HzB <= 1'b1; |
else begin |
if (p100ack) |
pulse100HzB <= 1'b0; |
end |
end |
|
|
145,7 → 158,8
.vol_o(), // volatile register selected |
.i1(), |
.i2(pulse1000HzB), |
.i3(), .i4(), .i5(), .i6(), .i7(), |
.i3(pulse100HzB), |
.i4(), .i5(), .i6(), .i7(), |
.i8(), .i9(), .i10(), .i11(), .i12(), .i13(), .i14(), |
.i15(), |
.irqo(cpu_irq), // normally connected to the processor irq |
/raptor64/trunk/rtl/verilog/Raptor64sc.v
1,8 → 1,10
`timescale 1ns / 1ps |
// ============================================================================ |
// (C) 2012 Robert Finch |
// All Rights Reserved. |
// robfinch<remove>@opencores.org |
// __ |
// \\__/ o\ (C) 2011-2013 Robert Finch, Stratford |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@opencores.org |
// || |
// |
// Raptor64sc.v |
// - 64 bit CPU |
20,6 → 22,8
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// 15848 LUT's / 3591 ff's / 48.215 MHz |
// 29 Block RAMs |
// ============================================================================ |
// |
`define ADDRESS_RESERVATION 1 |
58,7 → 62,8
parameter DCIDLE = 5'd20; |
parameter DCACT = 5'd21; |
parameter AMSB = 31; |
|
parameter RESET = 4'd0; |
parameter RUN = 4'd1; |
input rst_i; |
input clk_i; |
input nmi_i; |
93,6 → 98,7
input sys_adv; |
input [63:5] sys_adr; |
|
reg [3:0] state; |
reg [5:0] fltctr; |
wire fltdone = fltctr==6'd0; |
reg resetA; |
102,8 → 108,8
reg FXE; // fp exception enable |
wire KernelMode; |
wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,2'b00,10'b0}; |
reg [41:0] dIR,xIR,m1IR,m2IR,wIR; |
reg [41:0] ndIR; // next dIR |
reg [31:0] dIR,xIR,m1IR,m2IR,wIR; |
reg [31:0] ndIR; // next dIR |
reg [63:0] pc; |
wire [63:0] pchistoric; |
reg pccap; |
122,11 → 128,13
reg [63:0] TBA; // Trap Base Address |
reg [1:0] dhwxtype,xhwxtype,m1hwxtype,m2hwxtype,whwxtype; |
reg [8:0] dextype,xextype,m1extype,m2extype,wextype,textype; |
reg [3:0] AXC,dAXC,xAXC; |
reg [3:0] epat [0:255]; |
reg [7:0] eptr; |
reg [3:0] dAXC,xAXC,m1AXC,m2AXC; |
wire [3:0] AXC = epat[eptr]; |
reg dtinit; |
reg dcache_on; |
reg [63:32] nonICacheSeg; |
|
reg [1:0] FPC_rm; |
reg FPC_SL; // result is negative (and non-zero) |
reg FPC_SE; // result is zero |
146,7 → 154,7
}; |
wire [63:0] cdat; |
reg [63:0] wr_addr; |
reg [41:0] insn; |
reg [31:0] insn; |
reg clk_en; |
reg cpu_clk_en; |
reg StatusERL; // 1= in error processing |
159,27 → 167,28
reg [63:13] PageTableAddr; |
reg [63:0] errorAddress; |
|
wire [6:0] iOpcode = insn[41:35]; |
wire [6:0] iOpcode = insn[31:25]; |
wire [6:0] iFunc = insn[6:0]; |
wire [6:0] dOpcode = dIR[41:35]; |
wire [6:0] dOpcode = dIR[31:25]; |
wire [6:0] dFunc = dIR[6:0]; |
wire [5:0] dFunc6 = dIR[5:0]; |
wire [6:0] xOpcode = xIR[41:35]; |
wire [6:0] xOpcode = xIR[31:25]; |
wire [6:0] xFunc = xIR[6:0]; |
wire [5:0] xFunc6 = xIR[5:0]; |
wire [4:0] xFunc5 = xIR[4:0]; |
reg [6:0] m1Opcode,m2Opcode,wOpcode; |
reg [6:0] m1Func,m2Func,wFunc; |
wire [5:0] m1Func6 = m1Func[5:0]; |
reg [63:0] m1Data,m2Data,wData,tData; |
reg [63:0] m2Addr; |
reg [63:0] tick; |
reg [63:0] a,b,c,imm,m1b; |
reg [1:0] scale; |
reg prev_ihit; |
reg rsf; |
reg [63:5] resv_address; |
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf; |
reg xirqf; |
reg wLdPC,m2LdPC; |
wire advanceX_edge; |
wire takb; |
wire advanceX,advanceM1,advanceW; |
189,17 → 198,12
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff; |
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip; |
reg cyc1; |
reg LoadNOPs; |
|
|
function [63:0] fnIncPC; |
input [63:0] fpc; |
begin |
case(fpc[3:2]) |
2'd0: fnIncPC = {fpc[63:4],4'b0100}; |
2'd1: fnIncPC = {fpc[63:4],4'b1000}; |
2'd2: fnIncPC = {fpc[63:4]+60'd1,4'b0000}; |
2'd3: fnIncPC = {fpc[63:4]+60'd1,4'b0000}; |
endcase |
fnIncPC = fpc + 64'd4; |
end |
endfunction |
|
313,8 → 317,6
// |
//----------------------------------------------------------------------------- |
//reg lfdir; |
wire lfdir = (((dOpcode==`LM || dOpcode==`SM) && dIR[31:0]!=32'd0) && ndIR[31:0]!=32'd0) || (dIsLSPair && dIR[25]!=1'b1); |
wire ldnop = (((dOpcode==`LM || dOpcode==`SM) && (dIR[31:0]==32'd0 || ndIR[31:0]==32'd0)) || (dIsLSPair && dIR[25]==1'b1)); |
reg icaccess; |
reg ICacheOn; |
wire ibufrdy; |
325,12 → 327,12
wire isICached = ppc[63:32]!=nonICacheSeg; |
//wire isEncrypted = ppc[63:32]==encryptedArea; |
wire ICacheAct = ICacheOn & isICached; |
reg [41:0] insn1; |
reg [41:0] insnkey; |
reg [31:0] insn1; |
reg [31:0] insnkey; |
|
// SYSCALL 509 |
wire syscall509 = 42'b00_00000000_00000000_00000000_11111110_10010111; |
wire [127:0] bevect = {2'b00,syscall509,syscall509,syscall509}; |
wire syscall509 = 32'b0000000_11000_0000_11111110_10010111; |
wire [63:0] bevect = {syscall509,syscall509}; |
|
Raptor64_icache_ram u1 |
( |
337,29 → 339,27
.clka(clk), // input clka |
.wea(icaccess & (ack_i|err_i)), // input [0 : 0] wea |
.addra(adr_o[12:3]), // input [9 : 0] addra |
.dina(err_i ? (adr_o[3] ? bevect[127:64] : bevect[63:0]) : dat_i), // input [63 : 0] dina |
.dina(err_i ? bevect : dat_i), // input [63 : 0] dina |
.clkb(~clk), // input clkb |
.addrb(pc[12:4]), // input [8 : 0] addrb |
.doutb(insnbundle) // output [127 : 0] doutb |
); |
|
always @(ppc or insnbundle or ICacheAct or insnbuf0 or insnbuf1 or ndIR or lfdir or ldnop) |
always @(ppc or insnbundle or ICacheAct or insnbuf0 or insnbuf1) |
begin |
casex({ldnop,lfdir,ICacheAct,ibuftag1==ppc[63:4],pc[3:2]}) |
6'b1xxxxx: insn1 <= `NOP_INSN; |
6'b01xxxx: insn1 <= ndIR; |
6'b001x00: insn1 <= insnbundle[ 41: 0]; |
6'b001x01: insn1 <= insnbundle[ 83:42]; |
6'b001x10: insn1 <= insnbundle[125:84]; |
6'b001x11: insn1 <= `NOP_INSN; |
6'b000000: insn1 <= insnbuf0[ 41: 0]; |
6'b000001: insn1 <= insnbuf0[ 83:42]; |
6'b000010: insn1 <= insnbuf0[125:84]; |
6'b000011: insn1 <= `NOP_INSN; |
6'b000100: insn1 <= insnbuf1[ 41: 0]; |
6'b000101: insn1 <= insnbuf1[ 83:42]; |
6'b000110: insn1 <= insnbuf1[125:84]; |
6'b000111: insn1 <= `NOP_INSN; |
casex({ICacheAct,ibuftag1==ppc[63:4],pc[3:2]}) |
4'b0000: insn1 <= insnbuf0[ 31: 0]; |
4'b0001: insn1 <= insnbuf0[ 63:32]; |
4'b0010: insn1 <= insnbuf0[ 95:64]; |
4'b0011: insn1 <= insnbuf0[127:96]; |
4'b0100: insn1 <= insnbuf1[ 31: 0]; |
4'b0101: insn1 <= insnbuf1[ 63:32]; |
4'b0110: insn1 <= insnbuf1[ 95:64]; |
4'b0111: insn1 <= insnbuf1[127:96]; |
4'b1x00: insn1 <= insnbundle[ 31: 0]; |
4'b1x01: insn1 <= insnbundle[ 63:32]; |
4'b1x10: insn1 <= insnbundle[ 95:64]; |
4'b1x11: insn1 <= insnbundle[127:96]; |
endcase |
end |
|
609,35 → 609,35
end |
if (advanceX) begin |
if (xOpcode==`FP) begin |
if (xFunc[5:0]==6'b000000) // FDADD |
if (xFunc6==6'b000000) // FDADD |
fltctr <= 6'd12; |
else if (xFunc[5:0]==6'b000001) // FDSUB |
else if (xFunc6==6'b000001) // FDSUB |
fltctr <= 6'd12; |
else if (xFunc[5:0]==6'b000010) // FDMUL |
else if (xFunc6==6'b000010) // FDMUL |
fltctr <= 6'd12; |
else if (xFunc[5:0]==6'b000011) // FDDIV |
else if (xFunc6==6'b000011) // FDDIV |
fltctr <= 6'd12; |
else if (xFunc[5:0]==6'b000100) // unordered |
else if (xFunc6==6'b000100) // unordered |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b001100) // less than |
else if (xFunc6==6'b001100) // less than |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b010100) // equal |
else if (xFunc6==6'b010100) // equal |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b011100) // less than or equal |
else if (xFunc6==6'b011100) // less than or equal |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b100100) // greater than |
else if (xFunc6==6'b100100) // greater than |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b101100) // not equal |
else if (xFunc6==6'b101100) // not equal |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b110100) // greater than or equal |
else if (xFunc6==6'b110100) // greater than or equal |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b000101) // ItoFD |
else if (xFunc6==6'b000101) // ItoFD |
fltctr <= 6'd7; |
else if (xFunc[5:0]==6'b000110) // FFtoI |
else if (xFunc6==6'b000110) // FFtoI |
fltctr <= 6'd6; |
else if (xFunc[5:0]==6'b000111) // FtoD |
else if (xFunc6==6'b000111) // FtoD |
fltctr <= 6'd2; |
else if (xFunc[5:0]==6'b001000) // DtoF |
else if (xFunc6==6'b001000) // DtoF |
fltctr <= 6'd2; |
else |
fltctr <= 6'd0; |
733,7 → 733,7
end |
endfunction |
|
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00}; |
wire [63:0] jmp_tgt = {pc[63:27],insn[24:0],2'b00}; |
|
//----------------------------------------------------------------------------- |
// Stack for return address predictor |
800,7 → 800,7
Raptor64_logic u9 (xIR,a,b,imm,xLogico); |
Raptor64_set u15 (xIR,a,b,imm,xSeto); |
Raptor64_bitfield u16(xIR, rolo, b, xBitfieldo, masko); |
Raptor64_shift u17 (xIR, a, b, masko, xShifto); |
Raptor64_shift u17 (xIR, a, b, masko, xShifto, rolo); |
BCDMul2 u22 (a[7:0],b[7:0],bcdmulo); |
|
wire aeqz = a==64'd0; |
823,7 → 823,7
) |
casex(xOpcode) |
`R: |
casex(xFunc) |
casex(xFunc6) |
`COM: xData1 = ~a; |
`NOT: xData1 = ~|a; |
`NEG: xData1 = -a; |
856,7 → 856,7
|
`MTSPR: xData1 = a; |
`MFSPR: |
case(xIR[12:7]) |
case(xIR[11:6]) |
`ifdef TLB |
`TLBWired: xData1 = tlbo; |
`TLBIndex: xData1 = tlbo; |
894,14 → 894,14
`OMG: xData1 = mutex_gate[a[5:0]]; |
`CMG: xData1 = mutex_gate[a[5:0]]; |
`OMGI: begin |
xData1 = mutex_gate[xIR[12:7]]; |
$display("mutex_gate[%d]=%d",xIR[12:7],mutex_gate[xIR[12:7]]); |
xData1 = mutex_gate[xIR[11:6]]; |
$display("mutex_gate[%d]=%d",xIR[11:6],mutex_gate[xIR[11:6]]); |
end |
`CMGI: xData1 = mutex_gate[xIR[12:7]]; |
`CMGI: xData1 = mutex_gate[xIR[11:6]]; |
default: xData1 = 64'd0; |
endcase |
`RR: |
case(xFunc) |
case(xFunc6) |
`CMP: xData1 = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1; |
`CMPU: xData1 = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1; |
`MIN: xData1 = lt ? a : b; |
908,6 → 908,8
`MAX: xData1 = lt ? b : a; |
`MOVZ: xData1 = b; |
`MOVNZ: xData1 = b; |
`MOVPL: xData1 = b; |
`MOVMI: xData1 = b; |
`MULS: xData1 = mult_out[63:0]; |
`MULU: xData1 = mult_out[63:0]; |
`DIVS: xData1 = div_q; |
915,6 → 917,7
`MODU: xData1 = div_r; |
`MODS: xData1 = div_r; |
`BCD_MUL: xData1 = bcdmulo; |
`MFEP: xData1 = epat[a[7:0]]; |
default: xData1 = 64'd0; |
endcase |
`BTRR: |
922,8 → 925,14
`LOOP: xData1 = b - 64'd1; |
default: xData1 = 64'd0; |
endcase |
`SETLO: xData1 = {{32{xIR[31]}},xIR[31:0]}; |
`SETHI: xData1 = {xIR[31:0],a[31:0]}; |
`MUX: |
begin |
for (n = 0; n < 64; n = n + 1) |
xData1[n] = c[n] ? b[n] : a[n]; |
end |
`SETLO: xData1 = {{42{xIR[21]}},xIR[21:0]}; |
`SETMID: xData1 = {{20{xIR[21]}},xIR[21:0],a[21:0]}; |
`SETHI: xData1 = {xIR[19:0],a[43:0]}; |
`CMPI: xData1 = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1; |
`CMPUI: xData1 = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1; |
`MULSI: xData1 = mult_out[63:0]; |
939,13 → 948,11
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SP,`SFP,`SFDP: |
xData1 = a + imm; |
`MEMNDX: |
xData1 = a + b + imm; |
`SM: xData1 = a + {popcnt36(xIR[31:0]),3'b000}-64'd8; |
`LM: xData1 = a + {popcnt36(xIR[31:0]),3'b000}-64'd8; |
xData1 = a + (b << scale) + imm; |
`TRAPcc: xData1 = fnIncPC(xpc); |
`TRAPcci: xData1 = fnIncPC(xpc); |
`CALL: xData1 = fnIncPC(xpc); |
`JAL: xData1 = xpc + {xIR[29:25],2'b00}; |
`JAL: xData1 = fnIncPC(xpc);//???xpc + {xIR[19:15],2'b00}; |
`RET: xData1 = a + imm; |
`FPLOO: xData1 = fpLooOut; |
`FPZL: xData1 = fpZLOut; |
978,8 → 985,8
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xAddsubo[63]), .v(v_ri)); |
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xAddsubo[63]), .v(v_rr)); |
|
wire dbz_error = ((xOpcode==`DIVSI||xOpcode==`DIVUI) && imm==64'd0) || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU) && b==64'd0); |
wire ovr_error = ((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc==`SUB || xFunc==`ADD)) && v_rr); |
wire dbz_error = ((xOpcode==`DIVSI||xOpcode==`DIVUI) && imm==64'd0) || (xOpcode==`RR && (xFunc6==`DIVS || xFunc6==`DIVU) && b==64'd0); |
wire ovr_error = ((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc6==`SUB || xFunc6==`ADD)) && v_rr); |
wire priv_violation = !KernelMode && (xOpcode==`MISC && |
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI || |
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI |
989,14 → 996,57
; |
|
//----------------------------------------------------------------------------- |
//----------------------------------------------------------------------------- |
//wire dIsLoad = |
// dOpcode==`LW || dOpcode==`LH || dOpcode==`LB || dOpcode==`LWR || |
// dOpcode==`LHU || dOpcode==`LBU || |
// dOpcode==`LC || dOpcode==`LCU || dOpcode==`LM || |
// dOpcode==`LF || dOpcode==`LFD || dOpcode==`LP || dOpcode==`LFP || dOpcode==`LFDP || |
// dOpcode==`LSH || dOpcode==`LSW || |
// (dOpcode==`MEMNDX && ( |
// dFunc6==`LWX || dFunc6==`LHX || dFunc6==`LBX || dFunc6==`LWRX || |
// dFunc6==`LHUX || dFunc6==`LBUX || |
// dFunc6==`LCX || dFunc6==`LCUX || |
// dFunc6==`LFX || dFunc6==`LFDX || dFunc6==`LPX || |
// dFunc6==`LSHX || dFunc6==`LSWX |
// )) || |
// (dOpcode==`MISC && (dFunc==`SYSJMP || dFunc==`SYSCALL || dFunc==`SYSINT)) |
// ; |
//wire dIsStore = |
// dOpcode==`SW || dOpcode==`SH || dOpcode==`SB || dOpcode==`SC || dOpcode==`SWC || dOpcode==`SM || |
// dOpcode==`SF || dOpcode==`SFD || dOpcode==`SP || dOpcode==`SFP || dOpcode==`SFDP || |
// dOpcode==`SSH || dOpcode==`SSW || |
// (dOpcode==`MEMNDX && ( |
// dFunc6==`SWX || dFunc6==`SHX || dFunc6==`SBX || dFunc6==`SCX || dFunc6==`SWCX || |
// dFunc6==`SFX || dFunc6==`SFDX || dFunc6==`SPX || |
// dFunc6==`SSHX || dFunc6==`SSWX |
// )) |
// ; |
//wire dIsIn = |
// dOpcode==`INW || dOpcode==`INH || dOpcode==`INCH || dOpcode==`INB || |
// dOpcode==`INHU || dOpcode==`INCU || dOpcode==`INBU || |
// (dOpcode==`MEMNDX && ( |
// dFunc6==`INWX || dFunc6==`INHX || dFunc6==`INCX || dFunc6==`INBX || |
// dFunc6==`INHUX || dFunc6==`INCUX || dFunc6==`INBUX |
// )) |
// ; |
//wire dIsOut = dOpcode==`OUTW || dOpcode==`OUTH || dOpcode==`OUTC || dOpcode==`OUTB || |
// (dOpcode==`MEMNDX && ( |
// dFunc6==`OUTWX || dFunc6==`OUTHX || dFunc6==`OUTCX || dFunc6==`OUTBX |
// )) |
// ; |
|
|
//----------------------------------------------------------------------------- |
// Pipeline advance and stall logic |
//----------------------------------------------------------------------------- |
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT; |
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) || xOpcode==`MULSI || xOpcode==`MULUI; |
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS || xFunc==`MODU || xFunc==`MODS)) || xOpcode==`DIVSI || xOpcode==`DIVUI; |
wire xIsCnt = xOpcode==`R && (xFunc==`CTLZ || xFunc==`CTLO || xFunc==`CTPOP); |
wire xIsSqrt = xOpcode==`R && xFunc6==`SQRT; |
wire xIsMult = (xOpcode==`RR && (xFunc6==`MULU || xFunc6==`MULS)) || xOpcode==`MULSI || xOpcode==`MULUI; |
wire xIsDiv = (xOpcode==`RR && (xFunc6==`DIVU || xFunc6==`DIVS || xFunc6==`MODU || xFunc6==`MODS)) || xOpcode==`DIVSI || xOpcode==`DIVUI; |
wire xIsCnt = xOpcode==`R && (xFunc6==`CTLZ || xFunc6==`CTLO || xFunc6==`CTPOP); |
reg m1IsCnt,m2IsCnt; |
|
|
wire xIsLoad = |
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR || |
xOpcode==`LHU || xOpcode==`LBU || |
1010,7 → 1060,7
xFunc6==`LFX || xFunc6==`LFDX || xFunc6==`LPX || |
xFunc6==`LSHX || xFunc6==`LSWX |
)) || |
(xOpcode==`MISC && (xFunc==`SYSJMP || xFunc==`SYSCALL)) |
(xOpcode==`MISC && (xFunc==`SYSCALL)) |
; |
|
wire xIsStore = |
1026,19 → 1076,31
wire xIsSWC = xOpcode==`SWC; |
wire xIsIn = |
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB || |
xOpcode==`INHU || xOpcode==`INCU || xOpcode==`INBU |
xOpcode==`INHU || xOpcode==`INCU || xOpcode==`INBU || |
(xOpcode==`MEMNDX && ( |
xFunc6==`INWX || xFunc6==`INHX || xFunc6==`INCX || xFunc6==`INBX || |
xFunc6==`INHUX || xFunc6==`INCUX || xFunc6==`INBUX |
)) |
; |
wire xIsOut = xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB || |
(xOpcode==`MEMNDX && ( |
xFunc6==`OUTWX || xFunc6==`OUTHX || xFunc6==`OUTCX || xFunc6==`OUTBX |
)) |
; |
|
//wire mIsSWC = mOpcode==`SWC; |
//reg m1IsIn; |
|
wire m1IsIn = |
m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB || |
m1Opcode==`INHU || m1Opcode==`INCU || m1Opcode==`INBU |
m1Opcode==`INHU || m1Opcode==`INCU || m1Opcode==`INBU || |
(m1Opcode==`MEMNDX && ( |
m1Func6==`INWX || m1Func6==`INHX || m1Func6==`INCX || m1Func6==`INBX || |
m1Func6==`INHUX || m1Func6==`INCUX || m1Func6==`INBUX |
)) |
; |
wire m2IsInW = m2Opcode==`INW; |
wire xIsIO = |
xIsIn || |
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB |
; |
wire xIsIO = xIsIn || xIsOut; |
|
|
wire xIsFPLoo = xOpcode==`FPLOO; |
1052,6 → 1114,7
wire m2Rtz = m2Rt[4:0]==5'd0; |
|
// Stall on SWC allows rsf flag to be loaded for the next instruction |
// Could check for dRa,dRb,dRc==0, for non-stalling |
wire StallR = (((xIsLoad||xIsIn||xIsCnt) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRc)) && !xRtz) || xIsSWC) || |
(((m1IsLoad||m1IsIn||m1IsCnt) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRc)) && !m1Rtz)) || |
(((m2IsLoad||m2IsCnt) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRc)) && !m2Rtz)) |
1088,8 → 1151,8
// Cache loading control |
//----------------------------------------------------------------------------- |
wire pipelineEmpty = |
(dOpcode==`NOPI || dOpcode[6:4]==`IMM) && // and the pipeline is flushed |
(xOpcode==`NOPI || xOpcode[6:4]==`IMM) && |
(dOpcode==`NOPI) && // and the pipeline is flushed |
(xOpcode==`NOPI) && |
m1Opcode==`NOPI && |
m2Opcode==`NOPI |
; |
1118,85 → 1181,6
reg prev_nmi,nmi_edge; |
|
//----------------------------------------------------------------------------- |
//----------------------------------------------------------------------------- |
|
always @(dOpcode or dIR or dIsLSPair) |
begin |
ndIR <= dIR; |
if (dIsLSPair) begin |
ndIR[25] <= 1'b1; |
ndIR[3] <= 1'b1; |
end |
else if ((dOpcode==`LM || dOpcode==`SM) && dIR[31:0]!=32'd0) begin |
$display("LM/SM %h",dIR[31:0]); |
if (dIR[0]) |
ndIR[0] <= 1'b0; |
else if (dIR[1]) |
ndIR[1] <= 1'b0; |
else if (dIR[2]) |
ndIR[2] <= 1'b0; |
else if (dIR[3]) |
ndIR[3] <= 1'b0; |
else if (dIR[4]) |
ndIR[4] <= 1'b0; |
else if (dIR[5]) |
ndIR[5] <= 1'b0; |
else if (dIR[6]) |
ndIR[6] <= 1'b0; |
else if (dIR[7]) |
ndIR[7] <= 1'b0; |
else if (dIR[8]) |
ndIR[8] <= 1'b0; |
else if (dIR[9]) |
ndIR[9] <= 1'b0; |
else if (dIR[10]) |
ndIR[10] <= 1'b0; |
else if (dIR[11]) |
ndIR[11] <= 1'b0; |
else if (dIR[12]) |
ndIR[12] <= 1'b0; |
else if (dIR[13]) |
ndIR[13] <= 1'b0; |
else if (dIR[14]) |
ndIR[14] <= 1'b0; |
else if (dIR[15]) |
ndIR[15] <= 1'b0; |
else if (dIR[16]) |
ndIR[16] <= 1'b0; |
else if (dIR[17]) |
ndIR[17] <= 1'b0; |
else if (dIR[18]) |
ndIR[18] <= 1'b0; |
else if (dIR[19]) |
ndIR[19] <= 1'b0; |
else if (dIR[20]) |
ndIR[20] <= 1'b0; |
else if (dIR[21]) |
ndIR[21] <= 1'b0; |
else if (dIR[22]) |
ndIR[22] <= 1'b0; |
else if (dIR[23]) |
ndIR[23] <= 1'b0; |
else if (dIR[24]) |
ndIR[24] <= 1'b0; |
else if (dIR[25]) |
ndIR[25] <= 1'b0; |
else if (dIR[26]) |
ndIR[26] <= 1'b0; |
else if (dIR[27]) |
ndIR[27] <= 1'b0; |
else if (dIR[28]) |
ndIR[28] <= 1'b0; |
else if (dIR[29]) |
ndIR[29] <= 1'b0; |
else if (dIR[30]) |
ndIR[30] <= 1'b0; |
else |
ndIR[31] <= 1'b0; |
end |
end |
|
//----------------------------------------------------------------------------- |
// Register file. |
//----------------------------------------------------------------------------- |
|
1274,7 → 1258,9
sel_o <= 8'h00; |
adr_o <= 64'd0; |
dat_o <= 64'd0; |
|
|
state <= RESET; |
cstate <= IDLE; |
pccap <= 1'b1; |
nonICacheSeg <= 32'hFFFF_FFFD; |
TBA <= 64'd0; |
1292,8 → 1278,6
wData <= 64'd0; |
m1Data <= 64'd0; |
m2Data <= 64'd0; |
m2LdPC <= 1'b0; |
wLdPC <= 1'b0; |
m1IsLoad <= 1'b0; |
m2IsLoad <= 1'b0; |
m1IsStore <= 1'b0; |
1321,7 → 1305,6
wpcv <= 1'b0; |
tick <= 64'd0; |
cstate <= IDLE; |
AXC <= 4'd0; |
dAXC <= 4'd0; |
xirqf <= 1'b0; |
dextype <= 9'h00; |
1353,7 → 1336,9
// We set them here in case the user doesn't bother to set them. |
m_z <= 64'h0123456789ABCDEF; |
m_w <= 64'h8888888877777777; |
insnkey <= 42'd0; |
insnkey <= 32'd0; |
LoadNOPs <= 1'b0; |
eptr <= 8'h00; |
end |
else begin |
|
1360,15 → 1345,23
//--------------------------------------------------------- |
// Initialize program counters |
// Initialize data tags to zero. |
// Initialize execution pattern register to zero. |
//--------------------------------------------------------- |
if (resetA) begin |
pc <= `RESET_VECTOR; |
adr_o[14:6] <= adr_o[14:6]+9'd1; |
if (adr_o[14:6]==9'h1FF) begin |
dtinit <= 1'b0; |
resetA <= 1'b0; |
case(state) |
RESET: |
begin |
pc <= `RESET_VECTOR; |
adr_o[14:6] <= adr_o[14:6]+9'd1; |
if (adr_o[14:6]==9'h1FF) begin |
dtinit <= 1'b0; |
resetA <= 1'b0; |
state <= RUN; |
end |
epat[a[7:0]] <= b[3:0]; /// b=0, to make this line the same as MTEP |
a[7:0] <= a[7:0] + 8'h1; |
end |
end |
RUN: |
begin |
|
tick <= tick + 64'd1; |
|
1400,7 → 1393,7
dpcv <= 1'b1; |
dAXC <= AXC; |
dextype <= `EX_NON; |
if (nmi_edge & !StatusHWI & !im1) begin |
if (nmi_edge & !StatusHWI) begin |
$display("*****************"); |
$display("NMI edge detected"); |
$display("*****************"); |
1409,8 → 1402,9
dhwxtype <= 2'b01; |
dextype <= `EX_NMI; |
dIR <= `NOP_INSN; |
LoadNOPs <= 1'b1; |
end |
else if (irq_i & !im & !StatusHWI & !im1) begin |
else if (irq_i & !im & !StatusHWI) begin |
$display("*****************"); |
$display("IRQ detected"); |
$display("*****************"); |
1420,10 → 1414,11
dhwxtype <= 2'b10; |
dextype <= `EX_IRQ; |
dIR <= `NOP_INSN; |
LoadNOPs <= 1'b1; |
end |
// Are we filling the pipeline with NOP's as a result of a previous |
// hardware interrupt ? |
else if (|dhwxtype|dFip) |
else if (|dhwxtype|dFip|LoadNOPs) |
dIR <= `NOP_INSN; |
`ifdef TLB |
else if (ITLBMiss) |
1430,26 → 1425,10
dIR <= `NOP_INSN; |
`endif |
else begin |
if (((iOpcode==`SM || iOpcode==`LM) && insn[31:0]!=32'd0) || (iIsLSPair && !insn[25])) |
im1 <= 1'b1; |
else |
im1 <= 1'b0; |
if (iIsLSPair && insn[25]==1'b1) begin |
dIR <= `NOP_INSN; |
pc <= fnIncPC(pc); |
end |
else if ((iOpcode==`SM || iOpcode==`LM) && insn[31:0]==32'd0) begin |
dIR <= `NOP_INSN; |
pc <= fnIncPC(pc); |
end |
else |
dIR <= insn; |
dIR <= insn; |
`include "insn_dumpsc.v" |
end |
// Cause the prefixed instruction to inherit the address of the immediate |
// prefix, by not resetting the address. |
if (dOpcode[6:4]!=`IMM) |
dpc <= pc; |
dpc <= pc; |
`ifdef TLB |
if (ITLBMiss) begin |
$display("TLB miss on instruction fetch."); |
1462,14 → 1441,8
`endif |
begin |
dbranch_taken <= 1'b0; |
if (iIsLSPair && !insn[25]) |
; |
else if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0) |
; |
else begin |
if (pc!=64'hC) |
pc <= fnIncPC(pc); |
end |
// if (!LoadNOPs) |
pc <= fnIncPC(pc); |
case(iOpcode) |
`MISC: |
case(iFunc) |
1491,8 → 1464,6
begin |
pc <= ras[ras_sp + 6'd1]; |
ras_sp <= ras_sp + 6'd1; |
if (ras[ras_sp+6'd1]==64'hFFFF_FFFF_FFFF_C100) |
$display("****** C100 reached *****"); |
end |
`JMP: |
begin |
1505,10 → 1476,18
if (predict_taken) begin |
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00}); |
dbranch_taken <= 1'b1; |
pc <= {pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00}; |
pc <= pc + {{52{insn[14]}},insn[14:5],2'b00}; |
end |
default: ; |
endcase |
|
// If doing a JAL that stores a return address in the link register, save off the return address |
// in the return address predictor stack. |
`JAL: |
if (insn[19:15]==5'd31) begin |
ras[ras_sp] <= fnIncPC(pc); |
ras_sp <= ras_sp - 6'd1; |
end |
`ifdef BTB |
`JAL: pc <= btb[pc[7:2]]; |
`BTRI: |
1521,7 → 1500,7
begin |
if (predict_taken) begin |
dbranch_taken <= 1'b1; |
pc <= {pc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00}; |
pc <= pc + {{50{insn[19]}},insn[19:8],2'b00}; |
end |
end |
default: ; |
1533,14 → 1512,9
else if (advanceR) begin |
dbranch_taken <= 1'b0; |
dextype <= `EX_NON; |
// IMM is "sticky" |
if (dOpcode[6:4]!=`IMM && dOpcode!=`LM && dOpcode!=`SM && !dIsLSPair) begin |
dIR <= `NOP_INSN; |
dpcv <= 1'b0; |
dpc <= `RESET_VECTOR; |
end |
if ((((dOpcode==`SM || dOpcode==`LM) && dIR[31:0]!=32'd0)) || (dIsLSPair && !dIR[25])) |
dIR <= ndIR; |
dIR <= `NOP_INSN; |
dpcv <= 1'b0; |
dpc <= `RESET_VECTOR; |
end |
|
|
1570,24 → 1544,18
a <= nxt_a; |
b <= nxt_b; |
if (dOpcode==`SHFTI) |
b <= {58'd0,dIR[24:19]}; |
b <= {58'd0,dIR[14:9]}; |
c <= nxt_c; |
|
// Set immediate value |
if (xOpcode[6:4]==`IMM) begin |
imm <= {xIR[38:0],dIR[24:0]}; |
end |
else |
case(dOpcode) |
`BTRI: imm <= {{44{dIR[19]}},dIR[19:0]}; |
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI: |
imm <= {{46{dIR[17]}},dIR[17:0]}; |
`ORI: imm <= {39'h0000000000,dIR[24:0]}; |
`XORI: imm <= {39'h0000000000,dIR[24:0]}; |
`RET: imm <= {39'h00000000,dIR[24:3],3'b000}; |
`MEMNDX: imm <= {{50{dIR[19]}},dIR[19:6]}; |
default: imm <= {{39{dIR[24]}},dIR[24:0]}; |
endcase |
case(dOpcode) |
`BTRI: imm <= {{53{dIR[10]}},dIR[10:0]}; |
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI: |
imm <= {{56{dIR[7]}},dIR[7:0]}; |
`RET: imm <= {49'h00000000,dIR[14:3],3'b000}; |
`MEMNDX: imm <= dIR[7:6]; |
default: imm <= {{49{dIR[14]}},dIR[14:0]}; |
endcase |
scale <= dIR[9:8]; |
end |
// Stage tail |
// Pipeline annul for when a bubble in the pipeline occurs. |
1595,11 → 1563,9
xRtZero <= 1'b1; |
xextype <= `EX_NON; |
xbranch_taken <= 1'b0; |
if (xOpcode[6:4]!=`IMM) begin |
xIR <= `NOP_INSN; |
xpcv <= 1'b0; |
xpc <= `RESET_VECTOR; |
end |
xIR <= `NOP_INSN; |
xpcv <= 1'b0; |
xpc <= `RESET_VECTOR; |
end |
|
//--------------------------------------------------------- |
1625,14 → 1591,25
m1Rt <= xRtZero ? 9'd0 : xRt; |
m1Data <= xData; |
m1IsCacheElement <= xisCacheElement; |
if (xOpcode==`MOVZ && !aeqz) begin |
m1Rt <= 9'd0; |
m1Data <= 64'd0; |
m1AXC <= xAXC; |
if (xOpcode==`RR) begin |
if (xFunc6==`MOVZ && !aeqz) begin |
m1Rt <= 9'd0; |
m1Data <= 64'd0; |
end |
if (xFunc6==`MOVNZ && aeqz) begin |
m1Rt <= 9'd0; |
m1Data <= 64'd0; |
end |
if (xFunc6==`MOVPL && a[63]) begin |
m1Rt <= 9'd0; |
m1Data <= 64'd0; |
end |
if (xFunc6==`MOVMI && !a[63]) begin |
m1Rt <= 9'd0; |
m1Data <= 64'd0; |
end |
end |
if (xOpcode==`MOVNZ && aeqz) begin |
m1Rt <= 9'd0; |
m1Data <= 64'd0; |
end |
|
case(xOpcode) |
`MISC: |
1644,6 → 1621,7
`ICACHE_OFF: ICacheOn <= 1'b0; |
`DCACHE_ON: dcache_on <= 1'b1; |
`DCACHE_OFF: dcache_on <= 1'b0; |
`IEPP: eptr <= eptr + 8'd1; |
`GRAN: begin |
rando <= rand; |
m_z <= next_m_z; |
1658,7 → 1636,7
if (StatusHWI) begin |
StatusHWI <= 1'b0; |
im <= 1'b0; |
pc <= IPC; |
pc <= a; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
1668,7 → 1646,7
`ERET: |
if (StatusEXL) begin |
StatusEXL <= 1'b0; |
pc <= EPC; |
pc <= a; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
1675,12 → 1653,15
xpcv <= 1'b0; |
dpcv <= 1'b0; |
end |
`SYSJMP: |
`SYSCALL: |
begin |
if (xIR[15:7]!=`EX_NMI && xIR[15:7]!=`EX_IRQ) begin |
StatusEXL <= 1'b1; |
end |
pc <= 64'hC; |
if (xIR[15:7]==`EX_NMI || xIR[15:7]==`EX_IRQ) |
m1Data <= xpc; |
else |
m1Data <= fnIncPC(xpc); |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
1687,20 → 1668,8
xpcv <= 1'b0; |
dpcv <= 1'b0; |
ea <= {TBA[63:12],xIR[15:7],3'b000}; |
$display("EX SYSCALL thru %h",{TBA[63:12],xIR[15:7],3'b000}); |
end |
// SYSCALL EX_IRQ won't work. |
`SYSCALL: |
begin |
StatusEXL <= 1'b1; |
EPC <= fnIncPC(xpc); |
pc <= 64'hC; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
xpcv <= 1'b0; |
dpcv <= 1'b0; |
ea <= {TBA[63:12],xIR[15:7],3'b000}; |
end |
`ifdef TLB |
`TLBP: ea <= TLBVirtPage; |
`endif |
1707,7 → 1676,7
default: ; |
endcase |
`R: |
case(xFunc) |
case(xFunc6) |
`EXEC: |
begin |
pc <= fnIncPC(xpc); |
1726,7 → 1695,7
`ASID: ASID <= a[7:0]; |
`EPC: EPC <= a; |
`TBA: TBA <= {a[63:12],12'h000}; |
`AXC: AXC <= a[3:0]; |
// `AXC: AXC <= a[3:0]; |
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32]; |
`FPCR: rm <= a[31:30]; |
`IPC: IPC <= a; |
1746,10 → 1715,16
`CMGI: mutex_gate[xIR[12:7]] <= 1'b0; |
default: ; |
endcase |
`RR: |
case(xFunc6) |
`MTEP: epat[a[7:0]] <= b[3:0]; |
default: ; |
endcase |
// JMP and CALL change the program counter immediately in the IF stage. |
// There's no work to do here. The pipeline does not need to be cleared. |
`JMP: ; |
`CALL: m1Data <= fnIncPC(xpc); |
|
`JAL: |
`ifdef BTB |
if (dpc[63:2] != a[63:2] + imm[63:2]) begin |
1777,7 → 1752,6
// we need to branch to the RET location. |
`RET: |
if (dpc[63:2]!=b[63:2]) begin |
// $display("returning to: %h.%h", {b[63:4],4'b0},b[3:2]); |
pc[63:2] <= b[63:2]; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
1799,9 → 1773,8
dpcv <= 1'b0; |
end |
else if (takb & !xbranch_taken) begin |
$display("Taking branch %h.%h",{xpc[63:4] + {{42{xIR[24]}},xIR[24:7]},4'b0000},xIR[6:5]); |
pc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]}; |
pc[3:2] <= xIR[6:5]; |
$display("Taking branch %h",{xpc[63:2] + {{52{xIR[14]}},xIR[14:5]},2'b00}); |
pc[63:2] <= xpc[63:2] + {{52{xIR[14]}},xIR[14:5]}; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
1863,8 → 1836,7
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI: |
if (takb) begin |
if (!xbranch_taken) begin |
pc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]}; |
pc[3:2] <= xIR[19:18]; |
pc[63:2] <= xpc[63:2] + {{50{xIR[19]}},xIR[19:8]}; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
1887,7 → 1859,6
if (takb) begin |
StatusEXL <= 1'b1; |
xextype <= `EX_TRAP; |
pc <= 64'hC; |
dIR <= `NOP_INSN; |
xIR <= `NOP_INSN; |
xRtZero <= 1'b1; |
1900,32 → 1871,32
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= {xData[63:3],3'b000}; |
adr_o <= xData1; |
end |
`INH,`INHU: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= {xData[63:2],2'b00}; |
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= xData1; |
end |
`INCH,`INCU: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
case(xData[2:1]) |
case(xData1[2:1]) |
2'b00: sel_o <= 8'b00000011; |
2'b01: sel_o <= 8'b00001100; |
2'b10: sel_o <= 8'b00110000; |
2'b11: sel_o <= 8'b11000000; |
endcase |
adr_o <= {xData[63:1],1'b0}; |
adr_o <= xData1; |
end |
`INB,`INBU: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
case(xData[2:0]) |
case(xData1[2:0]) |
3'b000: sel_o <= 8'b00000001; |
3'b001: sel_o <= 8'b00000010; |
3'b010: sel_o <= 8'b00000100; |
1943,7 → 1914,7
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= {xData[63:3],3'b000}; |
adr_o <= xData1; |
dat_o <= b; |
end |
`OUTH: |
1951,8 → 1922,8
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= {xData[63:2],2'b00}; |
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= xData1; |
dat_o <= {2{b[31:0]}}; |
end |
`OUTC: |
1960,13 → 1931,13
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
case(xData[2:1]) |
case(xData1[2:1]) |
2'b00: sel_o <= 8'b00000011; |
2'b01: sel_o <= 8'b00001100; |
2'b10: sel_o <= 8'b00110000; |
2'b11: sel_o <= 8'b11000000; |
endcase |
adr_o <= {xData[63:1],1'b0}; |
adr_o <= xData1; |
dat_o <= {4{b[15:0]}}; |
end |
`OUTB: |
1974,7 → 1945,7
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
case(xData[2:0]) |
case(xData1[2:0]) |
3'b000: sel_o <= 8'b00000001; |
3'b001: sel_o <= 8'b00000010; |
3'b010: sel_o <= 8'b00000100; |
1984,15 → 1955,19
3'b110: sel_o <= 8'b01000000; |
3'b111: sel_o <= 8'b10000000; |
endcase |
adr_o <= xData; |
adr_o <= xData1; |
dat_o <= {8{b[7:0]}}; |
end |
`LEA: m1Data <= xData; |
`LEA: begin |
$display("LEA %h", xData1); |
m1Data <= xData1; |
end |
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`LF,`LFD,`LM,`LSH,`LSW,`LP,`LFP,`LFDP, |
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SM,`SSH,`SSW,`SP,`SFP,`SFDP: |
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SM,`SSW,`SP,`SFP,`SFDP: |
begin |
m1Data <= b; |
ea <= xData; |
ea <= xData1; |
$display("EX MEMOP %h", xData1); |
end |
`SSH: begin |
case(xRt) |
1999,14 → 1974,19
`SR: m1Data <= {2{sr}}; |
default: m1Data <= 64'd0; |
endcase |
ea <= xData; |
ea <= xData1; |
end |
`CACHE: |
begin |
m1Data <= b; |
ea <= xData; |
case(xIR[29:25]) |
ea <= xData1; |
case(xIR[19:15]) |
`INVIL: ; // handled in M1 stage |
`INVIALL: tvalid <= 128'd0; |
`ICACHEON: ICacheOn <= 1'b1; |
`ICACHEOFF: ICacheOn <= 1'b0; |
`DCACHEON: dcache_on <= 1'b1; |
`DCACHEOFF: dcache_on <= 1'b0; |
default: ; |
endcase |
end |
2016,12 → 1996,105
case(xFunc6) |
`LEAX: |
begin |
m1Data <= xData; |
$display("LEAX %h", xData1); |
m1Data <= xData1; |
end |
`INWX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= xData1; |
end |
`INHX,`INHUX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= xData1; |
end |
`INCX,`INCUX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
case(xData1[2:1]) |
2'b00: sel_o <= 8'b00000011; |
2'b01: sel_o <= 8'b00001100; |
2'b10: sel_o <= 8'b00110000; |
2'b11: sel_o <= 8'b11000000; |
endcase |
adr_o <= xData1; |
end |
`INBX,`INBUX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
case(xData1[2:0]) |
3'b000: sel_o <= 8'b00000001; |
3'b001: sel_o <= 8'b00000010; |
3'b010: sel_o <= 8'b00000100; |
3'b011: sel_o <= 8'b00001000; |
3'b100: sel_o <= 8'b00010000; |
3'b101: sel_o <= 8'b00100000; |
3'b110: sel_o <= 8'b01000000; |
3'b111: sel_o <= 8'b10000000; |
endcase |
adr_o <= xData1; |
end |
`OUTWX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= xData1; |
dat_o <= c; |
end |
`OUTHX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= xData1; |
dat_o <= {2{c[31:0]}}; |
end |
`OUTCX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
case(xData1[2:1]) |
2'b00: sel_o <= 8'b00000011; |
2'b01: sel_o <= 8'b00001100; |
2'b10: sel_o <= 8'b00110000; |
2'b11: sel_o <= 8'b11000000; |
endcase |
adr_o <= xData1; |
dat_o <= {4{c[15:0]}}; |
end |
`OUTBX: |
begin |
iocyc_o <= 1'b1; |
stb_o <= 1'b1; |
we_o <= 1'b1; |
case(xData1[2:0]) |
3'b000: sel_o <= 8'b00000001; |
3'b001: sel_o <= 8'b00000010; |
3'b010: sel_o <= 8'b00000100; |
3'b011: sel_o <= 8'b00001000; |
3'b100: sel_o <= 8'b00010000; |
3'b101: sel_o <= 8'b00100000; |
3'b110: sel_o <= 8'b01000000; |
3'b111: sel_o <= 8'b10000000; |
endcase |
adr_o <= xData1; |
dat_o <= {8{c[7:0]}}; |
end |
default: |
begin |
m1Data <= c; |
ea <= xData; |
ea <= xData1; |
end |
endcase |
end |
2072,10 → 2145,8
`endif |
if (dbz_error) begin |
$display("Divide by zero error"); |
xIR <= {`MISC,19'd0,`EX_DBZ,`SYSJMP}; |
pc <= 64'hC; |
EPC <= xpc; |
dIR <= `NOP_INSN; |
m1extype <= `EX_DBZ; |
LoadNOPs <= 1'b1; |
xRtZero <= 1'b1; |
xpcv <= 1'b0; |
dpcv <= 1'b0; |
2082,10 → 2153,8
end |
else if (ovr_error) begin |
$display("Overflow error"); |
xIR <= {`MISC,19'd0,`EX_OFL,`SYSJMP}; |
pc <= 64'hC; |
EPC <= xpc; |
dIR <= `NOP_INSN; |
m1extype <= `EX_OFL; |
LoadNOPs <= 1'b1; |
xRtZero <= 1'b1; |
xpcv <= 1'b0; |
dpcv <= 1'b0; |
2092,20 → 2161,16
end |
else if (priv_violation) begin |
$display("Priviledge violation"); |
xIR <= {`MISC,19'd0,`EX_PRIV,`SYSJMP}; |
dIR <= `NOP_INSN; |
m1extype <= `EX_PRIV; |
LoadNOPs <= 1'b1; |
xRtZero <= 1'b1; |
xpcv <= 1'b0; |
dpcv <= 1'b0; |
pc <= 64'hC; |
EPC <= xpc; |
end |
else if (illegal_insn) begin |
$display("Unimplemented Instruction"); |
xIR <= {`MISC,19'd0,`EX_UNIMP_INSN,`SYSJMP}; |
pc <= 64'hC; |
EPC <= xpc; |
dIR <= `NOP_INSN; |
m1extype <= `EX_UNIMP_INSN; |
LoadNOPs <= 1'b1; |
xRtZero <= 1'b1; |
xpcv <= 1'b0; |
dpcv <= 1'b0; |
2161,7 → 2226,7
m2Func <= m1Func; |
m2Rt <= m1Rt; |
m2clkoff <= m1clkoff; |
m2LdPC <= 1'b0; |
m2AXC <= m1AXC; |
if (m1IsIO & err_i) begin |
m2extype <= `EX_DBERR; |
errorAddress <= adr_o; |
2171,22 → 2236,21
case(m1Opcode) |
`MISC: |
case(m1Func) |
`SYSJMP,`SYSCALL: |
begin |
m2LdPC <= 1'b1; |
`SYSCALL: |
if (!m1IsCacheElement) begin |
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= {pea[63:3],3'b000}; |
m2Addr <= {pea[63:3],3'b000}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin // dhit must be true |
$display("fetched vector: %h", {cdat[63:2],2'b00}); |
m2IsLoad <= 1'b0; |
m2Opcode <= `NOPI; |
m2Data <= {cdat[63:2],2'b00}; |
pc <= {cdat[63:2],2'b00}; |
LoadNOPs <= 1'b0; |
end |
end |
endcase |
`INW: |
begin |
2277,8 → 2341,8
sel_o <= #1 8'h00; |
end |
`CACHE: |
case(m1IR[29:25]) |
`INVIL: tvalid[ea[12:6]] <= 1'b0; |
case(m1IR[19:15]) |
`INVIL: tvalid[pea[12:6]] <= 1'b0; |
default: ; |
endcase |
|
2288,8 → 2352,8
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= {pea[63:3],3'b000}; |
m2Addr <= {pea[63:3],3'b000}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin |
m2IsLoad <= 1'b0; |
2304,14 → 2368,14
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= 8'hFF; |
adr_o <= {pea[63:3],3'b000}; |
m2Addr <= {pea[63:3],3'b000}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin |
m2IsLoad <= 1'b0; |
m2Opcode <= `NOPI; |
m2Data <= cdat; |
rsv_o <= 1'b1; |
rsv_o <= 1'b1; // ??? |
resv_address <= pea[63:5]; |
end |
`endif |
2320,13 → 2384,13
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= {pea[63:2],2'b00}; |
m2Addr <= {pea[63:2],2'b00}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin |
m2IsLoad <= 1'b0; |
m2Opcode <= `NOPI; |
if (pea[1]) |
if (pea[2]) |
m2Data <= {{32{cdat[31]}},cdat[31:0]}; |
else |
m2Data <= {{32{cdat[63]}},cdat[63:32]}; |
2337,13 → 2401,13
cyc_o <= 1'b1; |
stb_o <= 1'b1; |
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= {pea[63:2],2'b00}; |
m2Addr <= {pea[63:2],2'b00}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin |
m2IsLoad <= 1'b0; |
m2Opcode <= `NOPI; |
if (pea[1]) |
if (pea[2]) |
m2Data <= {32'd0,cdat}; |
else |
m2Data <= {32'd0,cdat[63:32]}; |
2359,8 → 2423,8
2'b10: sel_o <= 8'b00110000; |
2'b11: sel_o <= 8'b11000000; |
endcase |
adr_o <= {pea[63:1],1'b0}; |
m2Addr <= {pea[63:1],1'b0}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin |
$display("dhit=1, cdat=%h",cdat); |
2384,8 → 2448,8
2'b10: sel_o <= 8'b00110000; |
2'b11: sel_o <= 8'b11000000; |
endcase |
adr_o <= {pea[63:1],1'b0}; |
m2Addr <= {pea[63:1],1'b0}; |
adr_o <= pea; |
m2Addr <= pea; |
end |
else begin |
m2IsLoad <= 1'b0; |
2455,7 → 2519,7
3'b000: m2Data <= {56'd0,cdat[ 7: 0]}; |
3'b001: m2Data <= {56'd0,cdat[15: 8]}; |
3'b010: m2Data <= {56'd0,cdat[23:16]}; |
3'b011: m2Data <= {56'd0,cdat[31:23]}; |
3'b011: m2Data <= {56'd0,cdat[31:24]}; |
3'b100: m2Data <= {56'd0,cdat[39:32]}; |
3'b101: m2Data <= {56'd0,cdat[47:40]}; |
3'b110: m2Data <= {56'd0,cdat[55:48]}; |
2465,8 → 2529,8
|
`SW,`SM,`SFD,`SSW,`SP,`SFDP: |
begin |
$display("SW/SM"); |
m2Addr <= #1 {pea[63:3],3'b000}; |
$display("%d SW/SM %h",tick,{pea[63:3],3'b000}); |
m2Addr <= pea; |
wrhit <= #1 dhit; |
`ifdef ADDRESS_RESERVATION |
if (resv_address==pea[63:5]) |
2476,7 → 2540,7
stb_o <= #1 1'b1; |
we_o <= #1 1'b1; |
sel_o <= #1 8'hFF; |
adr_o <= #1 {pea[63:3],3'b000}; |
adr_o <= pea; |
dat_o <= #1 m1Data; |
end |
|
2483,7 → 2547,7
`SH,`SF,`SSH,`SFP: |
begin |
wrhit <= #1 dhit; |
m2Addr <= #1 {pea[63:2],2'b00}; |
m2Addr <= pea; |
`ifdef ADDRESS_RESERVATION |
if (resv_address==pea[63:5]) |
resv_address <= #1 59'd0; |
2492,7 → 2556,7
stb_o <= #1 1'b1; |
we_o <= #1 1'b1; |
sel_o <= #1 pea[2] ? 8'b11110000 : 8'b00001111; |
adr_o <= #1 {pea[63:2],2'b00}; |
adr_o <= pea; |
dat_o <= #1 {2{m1Data[31:0]}}; |
end |
|
2500,7 → 2564,7
begin |
$display("Storing char to %h, ea=%h",pea,ea); |
wrhit <= #1 dhit; |
m2Addr <= #1 {pea[63:2],2'b00}; |
m2Addr <= pea; |
`ifdef ADDRESS_RESERVATION |
if (resv_address==pea[63:5]) |
resv_address <= #1 59'd0; |
2514,7 → 2578,7
2'b10: sel_o <= #1 8'b00110000; |
2'b11: sel_o <= #1 8'b11000000; |
endcase |
adr_o <= #1 {pea[63:1],1'b0}; |
adr_o <= pea; |
dat_o <= #1 {4{m1Data[15:0]}}; |
end |
|
2521,7 → 2585,7
`SB: |
begin |
wrhit <= #1 dhit; |
m2Addr <= #1 {pea[63:2],2'b00}; |
m2Addr <= pea; |
`ifdef ADDRESS_RESERVATION |
if (resv_address==pea[63:5]) |
resv_address <= #1 59'd0; |
2539,7 → 2603,7
3'b110: sel_o <= #1 8'b01000000; |
3'b111: sel_o <= #1 8'b10000000; |
endcase |
adr_o <= #1 {pea[63:2],2'b00}; |
adr_o <= pea; |
dat_o <= #1 {8{m1Data[7:0]}}; |
end |
|
2549,12 → 2613,12
rsf <= #1 1'b0; |
if (resv_address==pea[63:5]) begin |
wrhit <= #1 dhit; |
m2Addr <= #1 {pea[63:3],3'b00}; |
m2Addr <= pea; |
cyc_o <= #1 1'b1; |
stb_o <= #1 1'b1; |
we_o <= #1 1'b1; |
sel_o <= #1 8'hFF; |
adr_o <= #1 {pea[63:3],3'b000}; |
adr_o <= pea; |
dat_o <= #1 m1Data; |
resv_address <= #1 59'd0; |
rsf <= #1 1'b1; |
2605,13 → 2669,12
m2IsStore <= #1 1'b0; |
m2IsCnt <= #1 1'b0; |
m2Func <= #1 7'd0; |
m2Addr <= #1 64'd0; |
m2Addr <= 64'd0; |
m2Data <= #1 64'd0; |
m2clkoff <= #1 1'b0; |
m2pcv <= #1 1'b0; |
m2pc <= #1 `RESET_VECTOR; |
m2extype <= #1 `EX_NON; |
m2LdPC <= #1 1'b0; |
end |
|
|
2637,7 → 2700,6
wData <= #1 m2Data; |
wRt <= #1 m2Rt; |
wclkoff <= #1 m2clkoff; |
wLdPC <= #1 m2LdPC; |
|
// There's not an error is a prefetch is taking place (m2Rt=0). |
if (((m2IsLoad&&m2Rt[4:0]!=5'd0)|m2IsStore)&err_i) begin |
2644,20 → 2706,21
wextype <= #1 `EX_DBERR; |
errorAddress <= #1 adr_o; |
end |
|
|
if (m2extype==`EX_NON) begin |
case(m2Opcode) |
`MISC: |
if (m2Func==`SYSJMP || m2Func==`SYSCALL) |
if (m2Func==`SYSCALL) |
begin |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
sel_o <= #1 8'h00; |
wData <= #1 {dat_i[63:2],2'b00}; |
pc <= #1 {dat_i[63:2],2'b00}; |
LoadNOPs <= 1'b0; |
$display("M2 Fetched vector: %h",{dat_i[63:2],2'b00}); |
end |
`SH,`SC,`SB,`SW,`SWC,`SM,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP: |
`SH,`SC,`SB,`SW,`SWC,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP: |
begin |
$display("negating write signals"); |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
we_o <= #1 1'b0; |
2670,7 → 2733,7
sel_o <= #1 8'h00; |
wData <= #1 sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]}; |
end |
`LW,`LWR,`LM,`LFD,`LSW,`LP,`LFDP: |
`LW,`LWR,`LFD,`LSW,`LP,`LFDP: |
begin |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
2746,6 → 2809,9
end |
default: ; |
endcase |
// Force stack pointer to word alignment |
if (m2Rt[4:0]==5'b11110) |
wData[2:0] <= 3'b000; |
end |
end |
// Stage tail |
2757,7 → 2823,6
wIR <= `NOP_INSN; |
wOpcode <= `NOPI; |
wIsStore <= 1'b0; |
wLdPC <= 1'b0; |
wclkoff <= 1'b0; |
wpcv <= 1'b0; |
wpc <= `RESET_VECTOR; |
2834,20 → 2899,16
// Hardware exceptions |
`EX_NMI,`EX_IRQ: |
begin |
$display("Stuffing SYSJMP"); |
xIR <= {`MISC,19'd0,wextype,`SYSJMP}; |
pc <= 64'hC; |
$display("Stuffing SYSCALL %d",wextype); |
dIR <= {`MISC,5'd25,4'd0,wextype,`SYSCALL}; |
// One of the following three pc's MUST be valid. |
// wpc will be valid if the interrupt occurred outside of a branch |
// shadow. m1pc or m2pc (the branch target address) will be valid |
// depending on where in the branch shadow the interrupt falls. |
case(1'b1) |
wpcv: IPC <= wpc; |
m2pcv: IPC <= m2pc; |
default: IPC <= m1pc; |
// xpcv: IPC <= xpc; |
// dpcv: IPC <= dpc; |
// default: IPC <= pc; |
wpcv: dpc <= wpc; |
m2pcv: dpc <= m2pc; |
default: dpc <= m1pc; |
endcase |
end |
// Software exceptions |
2855,21 → 2916,15
`EX_TLBD,`EX_DBERR: |
begin |
pccap <= 1'b0; |
xIR <= {`MISC,19'd0,wextype,`SYSJMP}; |
pc <= 64'hC; |
EPC <= wpc; |
dIR <= {`MISC,5'd24,4'd0,wextype,`SYSCALL}; |
dpc <= wpc; |
end |
default: |
begin |
xIR <= {`MISC,19'd0,wextype,`SYSJMP}; |
pc <= 64'hC; |
EPC <= fnIncPC(wpc); |
dIR <= {`MISC,5'd24,4'd0,wextype,`SYSCALL}; |
dpc <= wpc; |
end |
endcase |
if (wLdPC) begin |
$display("Loading PC"); |
pc <= wData; |
end |
end |
// Stage tail |
// Pipeline annul for when a bubble in the pipeline occurs. |
2886,10 → 2941,6
//============================================================================= |
// Cache loader |
//============================================================================= |
if (rst_i) begin |
cstate <= IDLE; |
end |
else begin |
case(cstate) |
IDLE: |
if (triggerDCacheLoad) begin |
2936,21 → 2987,21
cstate <= IDLE; |
end |
end |
//SYSCALL 509: 00_00000000_00000000_00000000_11111110_10010111 |
//SYSCALL 509: 00000000_00000000_11111110_10010111 |
ICACT2: |
if (ack_i|err_i) begin |
adr_o <= adr_o + 64'd8; |
if (adr_o[3]==1'b0) begin |
cti_o <= 3'b111; // Last cycle ahead |
tmpbuf <= err_i ? bevect[63:0] : dat_i; |
tmpbuf <= err_i ? bevect : dat_i; |
end |
else begin |
if (tick[0]) begin |
insnbuf0 <= {err_i ? bevect[127:64] : dat_i,tmpbuf}; |
insnbuf0 <= {err_i ? bevect : dat_i,tmpbuf}; |
ibuftag0 <= adr_o[63:4]; |
end |
else begin |
insnbuf1 <= {err_i ? bevect[127:64] : dat_i,tmpbuf}; |
insnbuf1 <= {err_i ? bevect : dat_i,tmpbuf}; |
ibuftag1 <= adr_o[63:4]; |
end |
cti_o <= 3'b000; // back to non-burst mode |
2975,9 → 3026,9
end |
end |
|
endcase // cstate |
end // RUN |
endcase |
end |
|
end |
|
endmodule |
/raptor64/trunk/rtl/verilog/Raptor64_SetTargetRegister.v
25,17 → 25,20
// |
//============================================================================= |
|
`define EX_IRQ 9'd449 // interrupt |
`define EX_NMI 9'd510 // non-maskable interrupt |
|
module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dAXC,xRt); |
input rst; |
input clk; |
input advanceR; |
input advanceX; |
input [41:0] dIR; |
input [31:0] dIR; |
input [3:0] dAXC; |
output [8:0] xRt; |
reg [8:0] xRt; |
|
wire [6:0] dOpcode = dIR[41:35]; |
wire [6:0] dOpcode = dIR[31:25]; |
wire [6:0] dFunc = dIR[6:0]; |
|
always @(posedge clk) |
45,20 → 48,26
else begin |
if (advanceR) begin |
casex(dOpcode) |
`MISC: |
case(dFunc) |
`SYSCALL: xRt <= {dAXC,dIR[24:20]}; |
default: xRt <= 9'd0; |
endcase |
`R: |
case(dFunc) |
`MTSPR,`CMG,`CMGI,`EXEC: |
xRt <= 9'd0; |
`MYST: xRt <= {dAXC,dIR[19:15]}; |
default: xRt <= {dAXC,dIR[29:25]}; |
default: xRt <= {dAXC,dIR[19:15]}; |
endcase |
`SETLO: xRt <= {dAXC,dIR[36:32]}; |
`SETHI: xRt <= {dAXC,dIR[36:32]}; |
`RR,`FP: xRt <= {dAXC,dIR[24:20]}; |
`MYST,`MUX: xRt <= {dAXC,dIR[ 9: 5]}; |
`SETLO: xRt <= {dAXC,dIR[26:22]}; |
`SETMID: xRt <= {dAXC,dIR[26:22]}; |
`SETHI: xRt <= {dAXC,dIR[26:22]}; |
`RR,`FP: xRt <= {dAXC,dIR[14:10]}; |
`BTRI: xRt <= 9'd0; |
`BTRR: |
case(dIR[4:0]) |
`LOOP: xRt <= {dAXC,dIR[29:25]}; |
`LOOP: xRt <= {dAXC,dIR[19:15]}; |
default: xRt <= 9'd0; |
endcase |
`TRAPcc: xRt <= 9'd0; |
71,7 → 80,7
`SWX,`SHX,`SCX,`SBX,`SFX,`SFDX,`SPX,`SFPX,`SFDPX,`SSHX,`SSWX, |
`OUTWX,`OUTHX,`OUTCX,`OUTBX: |
xRt <= 9'd0; |
default: xRt <= {dAXC,dIR[24:20]}; |
default: xRt <= {dAXC,dIR[14:10]}; |
endcase |
`LSH,`LSW, |
`SW,`SH,`SC,`SB,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP, // but not SWC! |
80,47 → 89,8
`NOPI: xRt <= 9'd0; |
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI: |
xRt <= 9'd0; |
`SM: xRt <= 9'd0; |
`LM: |
casex(dIR[30:0]) |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: xRt <= {dAXC,5'd1}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: xRt <= {dAXC,5'd2}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: xRt <= {dAXC,5'd3}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: xRt <= {dAXC,5'd4}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: xRt <= {dAXC,5'd5}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: xRt <= {dAXC,5'd6}; |
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: xRt <= {dAXC,5'd7}; |
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: xRt <= {dAXC,5'd8}; |
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: xRt <= {dAXC,5'd9}; |
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: xRt <= {dAXC,5'd10}; |
31'bxxxxxxxxxxxxxxxxxxxx10000000000: xRt <= {dAXC,5'd11}; |
31'bxxxxxxxxxxxxxxxxxxx100000000000: xRt <= {dAXC,5'd12}; |
31'bxxxxxxxxxxxxxxxxxx1000000000000: xRt <= {dAXC,5'd13}; |
31'bxxxxxxxxxxxxxxxxx10000000000000: xRt <= {dAXC,5'd14}; |
31'bxxxxxxxxxxxxxxxx100000000000000: xRt <= {dAXC,5'd15}; |
31'bxxxxxxxxxxxxxxx1000000000000000: xRt <= {dAXC,5'd16}; |
31'bxxxxxxxxxxxxxx10000000000000000: xRt <= {dAXC,5'd17}; |
31'bxxxxxxxxxxxxx100000000000000000: xRt <= {dAXC,5'd18}; |
31'bxxxxxxxxxxxx1000000000000000000: xRt <= {dAXC,5'd19}; |
31'bxxxxxxxxxxx10000000000000000000: xRt <= {dAXC,5'd20}; |
31'bxxxxxxxxxx100000000000000000000: xRt <= {dAXC,5'd21}; |
31'bxxxxxxxxx1000000000000000000000: xRt <= {dAXC,5'd22}; |
31'bxxxxxxxx10000000000000000000000: xRt <= {dAXC,5'd23}; |
31'bxxxxxxx100000000000000000000000: xRt <= {dAXC,5'd24}; |
31'bxxxxxx1000000000000000000000000: xRt <= {dAXC,5'd25}; |
31'bxxxxx10000000000000000000000000: xRt <= {dAXC,5'd26}; |
31'bxxxx100000000000000000000000000: xRt <= {dAXC,5'd27}; |
31'bxxx1000000000000000000000000000: xRt <= {dAXC,5'd28}; |
31'bxx10000000000000000000000000000: xRt <= {dAXC,5'd29}; |
31'bx100000000000000000000000000000: xRt <= {dAXC,5'd30}; |
31'b1000000000000000000000000000000: xRt <= {dAXC,5'd31}; |
default: xRt <= 9'h000; |
endcase |
|
default: xRt <= {dAXC,dIR[29:25]}; |
default: xRt <= {dAXC,dIR[19:15]}; |
endcase |
if (dOpcode[6:4]==`IMM) |
xRt <= 9'd0; |
end |
else if (advanceX) |
xRt <= 9'd0; |