URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
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- from Rev 41 to Rev 42
- ↔ Reverse comparison
Rev 41 → Rev 42
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/02/05 16:44:38 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// Revision 1.7 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
121,7 → 126,7
`define ETH_IPGR1_DEF 32'h0000000C |
`define ETH_IPGR2_DEF 32'h00000012 |
`define ETH_PACKETLEN_DEF 32'h003C0600 |
`define ETH_COLLCONF_DEF 32'h000F0040 |
`define ETH_COLLCONF_DEF 32'h000F003f |
`define ETH_CTRLMODER_DEF 32'h00000000 |
`define ETH_MIIMODER_DEF 32'h00000064 |
`define ETH_MIICOMMAND_DEF 32'h00000000 |
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.3 2002/02/05 16:44:39 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
96,12 → 99,15
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, |
|
// Register |
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, |
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, r_RecSmall, |
|
WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven |
|
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ, |
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus |
|
); |
|
133,14 → 139,16
|
input Reset; // Reset signal |
|
// Status signals |
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode |
input LatchedCrcError; // CRC error |
input RxLateCollision; // Late collision occured while receiving frame |
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall) |
input DribbleNibble; // Extra nibble received |
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL |
input [15:0] RxLength; // Length of the incoming frame |
input LoadRxStatus; // Rx status was loaded |
|
|
// DMA |
// input [1:0] WB_ACK_I; // DMA acknowledge input |
// output [1:0] WB_REQ_O; // DMA request output |
// output [1:0] WB_ND_O; // DMA force new descriptor output |
// output WB_RD_O; // DMA restart descriptor output |
|
// Tx |
input MTxClk; // Transmit clock (from PHY) |
input TxUsedData; // Transmit packet used data |
173,6 → 181,7
input [7:0] r_TxBDNum; // Receive buffer descriptor number |
input r_DmaEn; // DMA enable |
input TX_BD_NUM_Wr; // RxBDNumber written |
input r_RecSmall; // Receive small frames igor !!! tega uporabi |
|
// Interrupts |
output TxB_IRQ; |
195,7 → 204,7
reg [15:0] TxLength; |
reg [15:0] TxStatus; |
|
reg [15:0] RxStatus; |
reg [14:13] RxStatusOld; |
|
reg TxStartFrm_wb; |
reg TxRetry_wb; |
240,6 → 249,7
reg ShiftWillEnd; |
|
reg WriteRxDataToFifo; |
reg [15:0] LatchedRxLength; |
|
reg ShiftEnded; |
|
269,14 → 279,14
wire [7:0] TempTxBDAddress; |
wire [7:0] TempRxBDAddress; |
|
reg [15:0] RxLength; |
wire [15:0] NewRxStatus; |
|
wire SetGotData; |
wire GotDataEvaluate; |
|
reg temp_ack; |
|
wire [5:0] RxStatusIn; |
reg [5:0] RxStatusInLatched; |
|
`ifdef ETH_REGISTERED_OUTPUTS |
reg temp_ack2; |
reg [31:0] registered_ram_do; |
356,8 → 366,6
end |
|
|
reg [3:0] debug; |
|
// Enabling access to the RAM for three devices. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
368,7 → 376,6
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp 8'h0; |
ram_di <=#Tp 32'h0; |
debug <=#Tp 4'h0; |
end |
else |
begin |
381,7 → 388,6
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp RxBDAddress + RxPointerRead; |
ram_di <=#Tp RxBDDataIn; |
debug <=#Tp 4'h1; |
end |
5'b100_01 : |
begin |
390,7 → 396,6
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled |
ram_addr <=#Tp TxBDAddress + TxPointerRead; |
ram_di <=#Tp TxBDDataIn; |
debug <=#Tp 4'h2; |
end |
5'b010_x0 : |
begin |
401,7 → 406,6
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs & WB_WE_I; |
BDRead <=#Tp BDCs & ~WB_WE_I; |
debug <=#Tp 4'h3; |
end |
5'b010_x1 : |
begin |
410,7 → 414,6
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled |
ram_addr <=#Tp TxBDAddress + TxPointerRead; |
ram_di <=#Tp TxBDDataIn; |
debug <=#Tp 4'h4; |
end |
5'b001_xx : |
begin |
421,12 → 424,10
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs & WB_WE_I; |
BDRead <=#Tp BDCs & ~WB_WE_I; |
debug <=#Tp 4'h5; |
end |
5'b100_00 : |
begin |
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit |
debug <=#Tp 4'h6; |
end |
5'b000_00 : |
begin |
437,7 → 438,6
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs & WB_WE_I; |
BDRead <=#Tp BDCs & ~WB_WE_I; |
debug <=#Tp 4'h7; |
end |
default : |
begin |
448,7 → 448,6
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs & WB_WE_I; |
BDRead <=#Tp BDCs & ~WB_WE_I; |
debug <=#Tp 4'h8; |
end |
endcase |
end |
962,7 → 961,7
// bit 4 od rx je carrier sense lost |
// bit [3:0] od rx je retry count |
|
assign WrapRxStatusBit = RxStatus[13]; |
assign WrapRxStatusBit = RxStatusOld[13]; |
|
|
// Temporary Tx and Rx buffer descriptor address |
995,10 → 994,7
RxBDAddress <=#Tp TempRxBDAddress; |
end |
|
assign NewRxStatus[15:0] = 16'hdead; |
|
|
assign RxBDDataIn = {RxLength, NewRxStatus}; // tu dopolni, da se bo vpisoval status |
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched}; // tu dopolni, da se bo vpisoval status |
assign TxBDDataIn = {32'h004380ef}; // tu dopolni, da se bo vpisoval status |
|
|
1313,10 → 1309,10
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatus <=#Tp 16'h0; |
RxStatusOld <=#Tp 2'h0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxStatus <=#Tp ram_do[15:0]; |
RxStatusOld <=#Tp ram_do[14:13]; |
end |
|
|
1384,6 → 1380,31
// Reception status is written back to the buffer descriptor after the end of frame is detected. |
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q; |
|
reg RxStatusWriteLatched; |
reg RxStatusWrite_rck; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatusWriteLatched <=#Tp 1'b0; |
else |
if(RxStatusWrite) |
RxStatusWriteLatched <=#Tp 1'b1; |
else |
if(RxStatusWrite_rck) |
RxStatusWriteLatched <=#Tp 1'b0; |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxStatusWrite_rck <=#Tp 1'b0; |
else |
RxStatusWrite_rck <=#Tp RxStatusWriteLatched; |
end |
|
|
reg RxEnableWindow; |
|
// Indicating that last byte is being reveived |
1484,20 → 1505,7
endcase |
end |
|
// Assembling data that will be written to the rx_fifo |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxLength <=#Tp 16'h0; |
else |
if(RxStartFrm) |
RxLength <=#Tp 16'h1; |
else |
if(RxValid & (RxStartFrm | RxEnableWindow)) |
RxLength <=#Tp RxLength + 1'b1; |
end |
|
|
reg WriteRxDataToFifoSync1; |
reg WriteRxDataToFifoSync2; |
|
1664,5 → 1672,44
assign Busy_IRQ = 1'b0; |
|
|
|
reg LoadStatusBlocked; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LoadStatusBlocked <=#Tp 1'b0; |
else |
if(LoadRxStatus) |
LoadStatusBlocked <=#Tp 1'b1; |
else |
if(RxStatusWrite_rck) |
LoadStatusBlocked <=#Tp 1'b0; |
end |
|
// LatchedRxLength[15:0] |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxLength[15:0] <=#Tp 16'h0; |
else |
if(LoadRxStatus & ~LoadStatusBlocked) |
LatchedRxLength[15:0] <=#Tp RxLength[15:0]; |
end |
|
|
|
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxStatusInLatched <=#Tp 'h0; |
else |
if(LoadRxStatus & ~LoadStatusBlocked) |
RxStatusInLatched <=#Tp RxStatusIn; |
end |
|
|
|
endmodule |
|
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.10 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
116,13 → 119,17
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, |
|
// Register |
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, |
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, r_RecSmall, |
|
WillSendControlFrame, TxCtrlEndFrm, |
|
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ, |
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus |
|
|
); |
|
|
147,6 → 154,16
output [1:0] WB_ND_O; // DMA force new descriptor output |
output WB_RD_O; // DMA restart descriptor output |
|
// Status |
input InvalidSymbol; |
input LatchedCrcError; |
input RxLateCollision; |
input ShortFrame; |
input DribbleNibble; |
input ReceivedPacketTooBig; |
input [15:0] RxLength; |
input LoadRxStatus; |
|
// Tx |
input MTxClk; // Transmit clock (from PHY) |
input TxUsedData; // Transmit packet used data |
178,6 → 195,7
input [7:0] r_TxBDNum; // Receive buffer descriptor number |
input r_DmaEn; // DMA enable |
input TX_BD_NUM_Wr; // RxBDNumber written |
input r_RecSmall; // Receive small frames |
|
// Interrupts |
output TxB_IRQ; |
364,7 → 382,6
wire [7:0] TempTxBDAddress; |
wire [7:0] TempRxBDAddress; |
|
wire [15:0] RxLength; |
wire [15:0] NewRxStatus; |
|
wire SetGotData; |
835,13 → 852,11
end |
|
|
assign RxLength[15:0] = 16'h1399; |
assign NewRxStatus[15:0] = {1'b0, WbWriteError, RxStatus[13:0]}; |
|
|
//assign BDDataIn = TxStatusWrite ? {TxLength[15:0], StatusIzTxEthMACModula} : {RxLength, NewRxStatus}; |
assign BDDataIn = TxStatusWrite ? {TxStatus[31:9], 9'h0} |
: {RxLength, NewRxStatus}; |
: {16'h1399, NewRxStatus}; |
|
assign BDStatusWrite = TxStatusWrite | RxStatusWrite; |
|
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.10 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.9 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
219,6 → 222,7
wire TxAbort; |
wire TxUnderRun; |
wire TxDone; |
wire [5:0] CollValid; |
|
|
|
241,6 → 245,7
wire RegCs; // Connected to registers |
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o |
wire r_DmaEn; // DMA enable |
wire r_RecSmall; // Receive small frames |
wire r_Rst; // Reset |
wire r_LoopBck; // Loopback |
wire r_TxEn; // Tx Enable |
255,7 → 260,11
wire [15:0] r_MaxFL; // Maximum frame length |
|
wire [15:0] r_MinFL; // Minimum frame length |
wire ShortFrame; |
wire DribbleNibble; // Extra nibble received |
wire ReceivedPacketTooBig; // Received packet is too big |
wire [47:0] r_MAC; // MAC address |
wire LoadRxStatus; // Rx status was loaded |
|
wire [7:0] r_TxBDNum; // Receive buffer descriptor number |
wire [6:0] r_IPGT; // |
301,7 → 310,7
( |
.DataIn(wb_dat_i), .Address(wb_adr_i[7:2]), .Rw(wb_we_i), |
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i), |
.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(), |
.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(r_RecSmall), |
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn), |
.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD), |
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck), |
339,6 → 348,9
wire ReceiveEnd; |
wire ReceivedPacketGood; |
wire ReceivedLengthOK; |
wire InvalidSymbol; |
wire LatchedCrcError; |
wire RxLateCollision; |
|
// Connecting MACControl |
eth_maccontrol maccontrol1 |
562,20 → 574,23
|
// Register |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum), |
.r_DmaEn(r_DmaEn), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), |
.r_DmaEn(r_DmaEn), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RecSmall(r_RecSmall), |
|
//RX |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid), |
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), |
.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ), |
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ) |
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), |
|
`ifdef WISHBONE_DMA |
`else |
, |
.RxAbort(RxAbort) |
.RxAbort(RxAbort), |
`endif |
|
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt), |
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus) |
|
); |
|
|
583,13 → 598,18
// Connecting MacStatus module |
eth_macstatus macstatus1 |
( |
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), .TransmitEnd(), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK), |
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb), |
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble), |
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt), |
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame), |
.ReceivedPauseFrm(ReceivedPauseFrm) |
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK), |
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb), |
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble), |
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt), |
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame), |
.ReceivedPauseFrm(ReceivedPauseFrm),.InvalidSymbol(InvalidSymbol), |
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i), |
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall), |
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame), |
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn), |
.LoadRxStatus(LoadRxStatus) |
); |
|
|
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
70,9 → 73,12
|
|
module eth_macstatus( |
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, TransmitEnd, ReceivedPacketGood, RxCrcError, |
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError, |
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting, |
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm |
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm, |
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision, |
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn, |
LoadRxStatus |
); |
|
|
96,22 → 102,35
input RxByteCntGreat2; |
input RxByteCntMaxFrame; |
input ReceivedPauseFrm; |
input [3:0] MRxD; |
input Collision; |
input [5:0] CollValid; |
input r_RecSmall; |
input [15:0] r_MinFL; |
input [15:0] r_MaxFL; |
input r_HugEn; |
|
output ReceivedLengthOK; |
output ReceiveEnd; |
output ReceivedPacketGood; |
output TransmitEnd; |
output InvalidSymbol; |
output LatchedCrcError; |
output RxLateCollision; |
output ShortFrame; |
output DribbleNibble; |
output ReceivedPacketTooBig; |
output LoadRxStatus; |
|
reg ReceiveEnd; |
|
reg LatchedCrcError; |
reg LatchedMRxErr; |
reg PreloadRxStatus; |
reg [15:0] LatchedRxByteCnt; |
reg LoadRxStatus; |
reg InvalidSymbol; |
|
wire TakeSample; |
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps |
|
|
// Crc error |
always @ (posedge MRxClk or posedge Reset) |
begin |
118,13 → 137,11
if(Reset) |
LatchedCrcError <=#Tp 1'b0; |
else |
begin |
if(RxStateSFD) |
LatchedCrcError <=#Tp 1'b0; |
else |
if(RxStateData[0]) |
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0; |
end |
if(RxStateSFD) |
LatchedCrcError <=#Tp 1'b0; |
else |
if(RxStateData[0]) |
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0; |
end |
|
|
147,51 → 164,129
|
|
// ReceivedLengthOK |
assign ReceivedLengthOK = LatchedRxByteCnt[15:0] > 63 & LatchedRxByteCnt[15:0] < 1519; |
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519; |
|
|
|
// LatchedRxByteCnt[15:0] |
|
|
// Time to take a sample |
assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 | |
RxStateData[0] & MRxDV & RxByteCntMaxFrame; |
|
|
// LoadRxStatus |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxByteCnt[15:0] <=#Tp 16'h0; |
LoadRxStatus <=#Tp 1'b0; |
else |
begin |
if(RxStateSFD) |
LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0]; |
else |
if(RxStateData[0]) |
LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0]; |
end |
LoadRxStatus <=#Tp TakeSample; |
end |
|
|
|
// Time to take a sample |
assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 | |
RxStateData[0] & MRxDV & RxByteCntMaxFrame; |
// ReceiveEnd |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceiveEnd <=#Tp 1'b0; |
else |
ReceiveEnd <=#Tp LoadRxStatus; |
end |
|
|
// PreloadRxStatus |
// Invalid Symbol received during 100Mbps mode |
assign SetInvalidSymbol = MRxDV & MRxErr & ~LatchedMRxErr & MRxD[3:0] == 4'he; |
|
|
// InvalidSymbol |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
PreloadRxStatus <=#Tp 1'b0; |
InvalidSymbol <=#Tp 1'b0; |
else |
PreloadRxStatus <=#Tp TakeSample; |
if(LoadRxStatus & ~SetInvalidSymbol) |
InvalidSymbol <=#Tp 1'b0; |
else |
if(SetInvalidSymbol) |
InvalidSymbol <=#Tp 1'b1; |
end |
|
|
// Late Collision |
|
// ReceiveEnd |
reg RxLateCollision; |
reg RxColWindow; |
// Collision Window |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceiveEnd <=#Tp 1'b0; |
RxLateCollision <=#Tp 1'b0; |
else |
ReceiveEnd <=#Tp PreloadRxStatus; |
if(LoadRxStatus) |
RxLateCollision <=#Tp 1'b0; |
else |
if(Collision & (~RxColWindow | r_RecSmall)) |
RxLateCollision <=#Tp 1'b1; |
end |
|
// Collision Window |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxColWindow <=#Tp 1'b1; |
else |
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1]) |
RxColWindow <=#Tp 1'b0; |
else |
if(RxStateIdle) |
RxColWindow <=#Tp 1'b1; |
end |
|
|
// ShortFrame |
reg ShortFrame; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShortFrame <=#Tp 1'b0; |
else |
if(LoadRxStatus) |
ShortFrame <=#Tp 1'b0; |
else |
if(TakeSample) |
ShortFrame <=#Tp r_RecSmall & RxByteCnt[15:0] < r_MinFL[15:0]; |
end |
|
|
// DribbleNibble |
reg DribbleNibble; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DribbleNibble <=#Tp 1'b0; |
else |
if(RxStateSFD) |
DribbleNibble <=#Tp 1'b0; |
else |
if(~MRxDV & RxStateData[1]) |
DribbleNibble <=#Tp 1'b1; |
end |
|
|
reg ReceivedPacketTooBig; |
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceivedPacketTooBig <=#Tp 1'b0; |
else |
if(LoadRxStatus) |
ReceivedPacketTooBig <=#Tp 1'b0; |
else |
if(TakeSample) |
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; |
end |
|
endmodule |