OpenCores

/tags/rel_1/doc/vga_core.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

tags/rel_1/doc/vga_core.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_1/doc/src/vga_core_enh.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_1/doc/src/vga_core_enh.doc =================================================================== --- tags/rel_1/doc/src/vga_core_enh.doc (nonexistent) +++ tags/rel_1/doc/src/vga_core_enh.doc (revision 42)

tags/rel_1/doc/src/vga_core_enh.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_1/rtl/verilog/vga_vtim.v =================================================================== --- tags/rel_1/rtl/verilog/vga_vtim.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_vtim.v (revision 42) @@ -0,0 +1,166 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core; Timing Generator //// +//// Video Timing Generator //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_vtim.v,v 1.6 2002-04-20 10:02:39 rherveille Exp $ +// +// $Date: 2002-04-20 10:02:39 $ +// $Revision: 1.6 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/01/28 03:47:16 rherveille +// Changed counter-library. +// Changed vga-core. +// Added 32bpp mode. +// + +`include "timescale.v" + +module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done); + // inputs & outputs + input clk; // master clock + input ena; // count enable + input rst; // synchronous active high reset + + input [ 7:0] Tsync; // sync duration + input [ 7:0] Tgdel; // gate delay + input [15:0] Tgate; // gate length + input [15:0] Tlen; // line time / frame time + + output Sync; // synchronization pulse + output Gate; // gate + output Done; // done with line/frame + reg Sync; + reg Gate; + + + // + // variable declarations + // + + wire Dsync, Dgdel, Dgate, Dlen; + reg go, drst; + + // + // module body + // + + // generate go signal + always@(posedge clk) + if (rst) + begin + go <= #1 1'b0; + drst <= #1 1'b1; + end + else // if (ena) + begin + go <= #1 Dlen | (!rst & drst); + drst <= #1 rst; + end + + // hookup sync counter + ro_cnt #(8, 1'b0, 8) + sync_cnt( + .clk(clk), + .rst(rst), + .nReset(1'b1), + .cnt_en(ena), + .go(go), + .d(Tsync), + .q(), + .done(Dsync) + ); + + // hookup gate delay counter + ro_cnt #(8, 1'b0, 8) + gdel_cnt( + .clk(clk), + .rst(rst), + .nReset(1'b1), + .cnt_en(ena), + .go(Dsync), + .d(Tgdel), + .q(), + .done(Dgdel) + ); + + // hookup gate counter + ro_cnt #(16, 1'b0, 16) + gate_cnt( + .clk(clk), + .rst(rst), + .nReset(1'b1), + .cnt_en(ena), + .go(Dgdel), + .d(Tgate), + .q(), + .done(Dgate) + ); + + // hookup length counter + ro_cnt #(16, 1'b0, 16) + len_cnt( + .clk(clk), + .rst(rst), + .nReset(1'b1), + .cnt_en(ena), + .go(go), + .d(Tlen), + .q(), + .done(Dlen) + ); + + // generate output signals + always@(posedge clk) + if (rst) + Sync <= #1 1'b0; + else + Sync <= #1 (go | Sync) & !Dsync; + + always@(posedge clk) + if (rst) + Gate <= #1 1'b0; + else + Gate <= #1 (Dgdel | Gate) & !Dgate; + + assign Done = Dlen; +endmodule Index: tags/rel_1/rtl/verilog/vga_wb_master.v =================================================================== --- tags/rel_1/rtl/verilog/vga_wb_master.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_wb_master.v (revision 42) @@ -0,0 +1,648 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Wishbone master interface //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_wb_master.v,v 1.11 2002-04-20 10:02:39 rherveille Exp $ +// +// $Date: 2002-04-20 10:02:39 $ +// $Revision: 1.11 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.10 2002/03/28 04:59:25 rherveille +// Fixed two small bugs that only showed up when the hardware cursors were disabled +// +// Revision 1.9 2002/03/04 16:05:52 rherveille +// Added hardware cursor support to wishbone master. +// Added provision to turn-off 3D cursors. +// Fixed some minor bugs. +// +// Revision 1.8 2002/03/04 11:01:59 rherveille +// Added 64x64pixels 4bpp hardware cursor support. +// +// Revision 1.7 2002/02/16 10:40:00 rherveille +// Some minor bug-fixes. +// Changed vga_ssel into vga_curproc (cursor processor). +// +// Revision 1.6 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +`include "timescale.v" +`include "vga_defines.v" + +module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint, + ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw, + cursor0_en, cursor0_res, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_o, cc0_dat_i, + cursor1_en, cursor1_res, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_o, cc1_dat_i, + VBAa, VBAb, Thgate, Tvgate, + stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full, + clut_req, clut_ack, clut_adr, clut_q); + + // inputs & outputs + + // wishbone signals + input clk_i; // master clock input + input rst_i; // synchronous active high reset + input nrst_i; // asynchronous low reset + output cyc_o; // cycle output + reg cyc_o; + output stb_o; // strobe ouput + reg stb_o; + output cab_o; // consecutive address burst output + reg cab_o; + output we_o; // write enable output + reg we_o; + output [31:0] adr_o; // address output + output [ 3:0] sel_o; // byte select outputs (only 32bits accesses are supported) + reg [3:0] sel_o; + input ack_i; // wishbone cycle acknowledge + input err_i; // wishbone cycle error + input [31:0] dat_i; // wishbone data in + + output sint; // non recoverable error, interrupt host + + // control register settings + input ctrl_ven; // video enable bit + input [1:0] ctrl_cd; // color depth + input ctrl_pc; // 8bpp pseudo color/bw + input [1:0] ctrl_vbl; // burst length + input ctrl_vbsw; // enable video bank switching + input ctrl_cbsw; // enable clut bank switching + + input cursor0_en; // enable hardware cursor0 + input cursor0_res; // cursor0 resolution + input [31: 0] cursor0_xy; // (x,y) address hardware cursor0 + input [31:11] cursor0_ba; // cursor0 video memory base address + input cursor0_ld; // reload cursor0 from video memory + output [ 3: 0] cc0_adr_o; // cursor0 color registers address output + input [15: 0] cc0_dat_i; // cursor0 color registers data input + input cursor1_en; // enable hardware cursor1 + input cursor1_res; // cursor1 resolution + input [31: 0] cursor1_xy; // (x,y) address hardware cursor1 + input [31:11] cursor1_ba; // cursor1 video memory base address + input cursor1_ld; // reload cursor1 from video memory + output [ 3: 0] cc1_adr_o; // cursor1 color registers address output + input [15: 0] cc1_dat_i; // cursor1 color registers data input + + // video memory addresses + input [31: 2] VBAa; // video memory base address A + input [31: 2] VBAb; // video memory base address B + + input [15:0] Thgate; // horizontal visible area (in pixels) + input [15:0] Tvgate; // vertical visible area (in horizontal lines) + + output stat_avmp; // active video memory page + output stat_acmp; // active CLUT memory page + reg stat_acmp; + output vmem_switch; // video memory bank-switch request: memory page switched (when enabled) + output clut_switch; // clut memory bank-switch request: clut page switched (when enabled) + + // to/from line-fifo + output line_fifo_wreq; + output [23:0] line_fifo_d; + input line_fifo_full; + + // to/from color lookup-table + output clut_req; // clut access request + input clut_ack; // clut access acknowledge + output [ 8:0] clut_adr; // clut access address + input [23:0] clut_q; // clut access data in + + // + // variable declarations + // + + reg vmem_acc; // video memory access + wire nvmem_req, vmem_ack; // NOT video memory access request // video memory access acknowledge + + wire ImDone; // Done reading image from video mem + reg dImDone; // delayed ImDone + wire ImDoneStrb; // image done (strobe signal) + reg dImDoneStrb; // delayed ImDoneStrb + + wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull; + wire [31:0] data_fifo_q; + wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d; + wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq; + wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq; + wire ImDoneFifoQ; + reg dImDoneFifoQ, ddImDoneFifoQ; + + reg sclr; // synchronous clear + + wire [7:0] clut_offs; // color lookup table offset + + // + // hardware cursors + reg [31:11] cursor_ba; // cursor pattern base address + reg [ 8: 0] cursor_adr; // cursor pattern offset + wire cursor0_we, cursor1_we; // cursor buffers write_request + reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1 + reg cur_acc; // cursor processors request memory access + reg cur_acc_sel; // which cursor to reload + wire cur_ack; // cursor processor memory access acknowledge + wire cur_done; // done reading cursor pattern + + + // + // module body + // + + // generate synchronous clear + always@(posedge clk_i) + sclr <= #1 ~ctrl_ven; + + // + // WISHBONE block + // + reg [ 2:0] burst_cnt; // video memory burst access counter + wire burst_done; // completed burst access to video mem + reg sel_VBA; // select video memory base address + reg [31:2] vmemA; // video memory address + + // wishbone access controller, video memory access request has highest priority (try to keep fifo full) + always@(posedge clk_i) + if (sclr) + vmem_acc <= #1 1'b0; // video memory access request + else + vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc; + + always@(posedge clk_i) + if (sclr) + cur_acc <= #1 1'b0; // cursor processor memory access request + else + cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done; + + + assign vmem_ack = ack_i & vmem_acc; + assign cur_ack = ack_i & cur_acc; + assign sint = err_i; // Non recoverable error, interrupt host system + + + // select active memory page + assign vmem_switch = ImDoneStrb; + + always@(posedge clk_i) + if (sclr) + sel_VBA <= #1 1'b0; + else if (ctrl_vbsw) + sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled) + + assign stat_avmp = sel_VBA; // assign output + + // selecting active clut page / cursor data + // delay image done same amount as video-memory data + vga_fifo #(4, 1) clut_sw_fifo ( + .clk(clk_i), + .aclr(1'b1), + .sclr(sclr), + .d(ImDone), + .wreq(vmem_ack), + .q(ImDoneFifoQ), + .rreq(data_fifo_rreq), + .empty(), + .hfull(), + .full() + ); + + // + // clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay + always@(posedge clk_i) + if (sclr) + dImDoneFifoQ <= #1 1'b0; + else if (data_fifo_rreq) + dImDoneFifoQ <= #1 ImDoneFifoQ; + + always@(posedge clk_i) + if (sclr) + ddImDoneFifoQ <= #1 1'b0; + else + ddImDoneFifoQ <= #1 dImDoneFifoQ; + + assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ; + + always@(posedge clk_i) + if (sclr) + stat_acmp <= #1 1'b0; + else if (ctrl_cbsw) + stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled) + + // + // generate clut-address + assign clut_adr = {stat_acmp, clut_offs}; + + // + // generate burst counter + wire [3:0] burst_cnt_val; + assign burst_cnt_val = {1'b0, burst_cnt} -4'h1; + assign burst_done = burst_cnt_val[3]; + + always@(posedge clk_i) + if ( (burst_done & vmem_ack) | !vmem_acc) + case (ctrl_vbl) // synopsis full_case parallel_case + 2'b00: burst_cnt <= #1 3'b000; // burst length 1 + 2'b01: burst_cnt <= #1 3'b001; // burst length 2 + 2'b10: burst_cnt <= #1 3'b011; // burst length 4 + 2'b11: burst_cnt <= #1 3'b111; // burst length 8 + endcase + else if(vmem_ack) + burst_cnt <= #1 burst_cnt_val[2:0]; + + // + // generate image counters + // + + // hgate counter + reg [15:0] hgate_cnt; + reg [16:0] hgate_cnt_val; + reg [1:0] hgate_div_cnt; + reg [2:0] hgate_div_val; + + wire hdone = hgate_cnt_val[16] & vmem_ack; // ???? + + always@(hgate_cnt or hgate_div_cnt or ctrl_cd) + begin + hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1; + + if (ctrl_cd != 2'b10) + hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1; + else if ( hgate_div_val[2] ) + hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1; + else + hgate_cnt_val = {1'b0, hgate_cnt}; + end + + always@(posedge clk_i) + if (sclr) + begin + case(ctrl_cd) // synopsys full_case parallel_case + 2'b00: // 8bpp + hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle + 2'b01: //16bpp + hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle + 2'b10: //24bpp + hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle + 2'b11: //32bpp + hgate_cnt <= #1 Thgate; // 1 pixel per cycle + endcase + + hgate_div_cnt <= 2'b10; + end + else if (vmem_ack) + if (hdone) + begin + case(ctrl_cd) // synopsys full_case parallel_case + 2'b00: // 8bpp + hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle + 2'b01: //16bpp + hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle + 2'b10: //24bpp + hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle + 2'b11: //32bpp + hgate_cnt <= #1 Thgate; // 1 pixel per cycle + endcase + hgate_div_cnt <= #1 2'b10; + end + else //if (vmem_ack) + begin + hgate_cnt <= #1 hgate_cnt_val[15:0]; + + if ( hgate_div_val[2] ) + hgate_div_cnt <= #1 2'b10; + else + hgate_div_cnt <= #1 hgate_div_val[1:0]; + end + + // vgate counter + reg [15:0] vgate_cnt; + wire vdone = ~|vgate_cnt[15:1] & vgate_cnt[0]; + + always@(posedge clk_i) + if (sclr || ImDoneStrb) + vgate_cnt <= #1 Tvgate; + else if (hdone) + vgate_cnt <= #1 vgate_cnt -16'h1; + + assign ImDone = hdone & vdone; + + assign ImDoneStrb = ImDone & !dImDone; + + always@(posedge clk_i) + begin + dImDone <= #1 ImDone; + dImDoneStrb <= #1 ImDoneStrb; + end + + // + // generate addresses + // + + // select video memory base address + always@(posedge clk_i) + if (dImDoneStrb | sclr) + if (!sel_VBA) + vmemA <= #1 VBAa; + else + vmemA <= #1 VBAb; + else if (vmem_ack) + vmemA <= #1 vmemA +30'h1; + + + //////////////////////////////////// + // hardware cursor signals section + // + always@(posedge clk_i) + if (ImDone) + cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority + + always@(posedge clk_i) + if (sclr) + begin + ld_cursor0 <= #1 1'b0; + ld_cursor1 <= #1 1'b0; + end + else + begin + ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel)); + ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel)); + end + + // select cursor base address + always@(posedge clk_i) + if (!cur_acc) + cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba; + + // generate pattern offset + wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1; + assign cur_done = next_cursor_adr[9]; + + always@(posedge clk_i) + if (!cur_acc) + cursor_adr <= #1 9'h0; + else if (cur_ack) + cursor_adr <= #1 next_cursor_adr; + + // generate cursor buffers write enable signals + assign cursor1_we = cur_ack & !cur_acc_sel; + assign cursor0_we = cur_ack & cur_acc_sel; + + + ////////////////////////////// + // generate wishbone signals + // + assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00}; + wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone || + cur_acc & !cur_done; + + always@(posedge clk_i or negedge nrst_i) + if (!nrst_i) + begin + cyc_o <= #1 1'b0; + stb_o <= #1 1'b0; + sel_o <= #1 4'b1111; + cab_o <= #1 1'b0; + we_o <= #1 1'b0; + end + else + if (rst_i) + begin + cyc_o <= #1 1'b0; + stb_o <= #1 1'b0; + sel_o <= #1 4'b1111; + cab_o <= #1 1'b0; + we_o <= #1 1'b0; + end + else + begin + cyc_o <= #1 wb_cycle; + stb_o <= #1 wb_cycle; + sel_o <= #1 4'b1111; // only 32bit accesses are supported + cab_o <= #1 wb_cycle; + we_o <= #1 1'b0; // read only + end + + // + // video-data buffer (temporary store data read from video memory) + vga_fifo #(4, 32) data_fifo ( + .clk(clk_i), + .aclr(1'b1), + .sclr(sclr), + .d(dat_i), + .wreq(vmem_ack), + .q(data_fifo_q), + .rreq(data_fifo_rreq), + .empty(data_fifo_empty), + .hfull(data_fifo_hfull), + .full() + ); + + assign nvmem_req = data_fifo_hfull; + + // + // hookup color processor + vga_colproc color_proc ( + .clk(clk_i), + .srst(sclr), + .vdat_buffer_di(data_fifo_q), + .ColorDepth(ctrl_cd), + .PseudoColor(ctrl_pc), + .vdat_buffer_empty(data_fifo_empty), + .vdat_buffer_rreq(data_fifo_rreq), + .rgb_fifo_full(rgb_fifo_full), + .rgb_fifo_wreq(color_proc_wreq), + .r(color_proc_q[23:16]), + .g(color_proc_q[15:8]), + .b(color_proc_q[7:0]), + .clut_req(clut_req), + .clut_ack(clut_ack), + .clut_offs(clut_offs), + .clut_q(clut_q) + ); + + // + // hookup data-source-selector && hardware cursor module +`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled) + wire cursor1_ld_strb; + reg scursor1_en; + reg scursor1_res; + reg [31:0] scursor1_xy; + + assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ; + + always@(posedge clk_i) + if (sclr) + scursor1_en <= #1 1'b0; + else if (cursor1_ld_strb) + scursor1_en <= #1 cursor1_en; + + always@(posedge clk_i) + if (cursor1_ld_strb) + scursor1_xy <= #1 cursor1_xy; + + always@(posedge clk_i) + if (cursor1_ld_strb) + scursor1_res <= #1 cursor1_res; + + vga_curproc hw_cursor1 ( + .clk(clk_i), + .rst_i(sclr), + .Thgate(Thgate), + .Tvgate(Tvgate), + .idat(color_proc_q), + .idat_wreq(color_proc_wreq), + .cursor_xy(scursor1_xy), + .cursor_res(scursor1_res), + .cursor_en(scursor1_en), + .cursor_wadr(cursor_adr), + .cursor_we(cursor1_we), + .cursor_wdat(dat_i), + .cc_adr_o(cc1_adr_o), + .cc_dat_i(cc1_dat_i), + .rgb_fifo_wreq(ssel1_wreq), + .rgb(ssel1_q) + ); + +`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled) + reg sddImDoneFifoQ, sdImDoneFifoQ; + + always@(posedge clk_i) + if (ssel1_wreq) + begin + sdImDoneFifoQ <= #1 dImDoneFifoQ; + sddImDoneFifoQ <= #1 sdImDoneFifoQ; + end +`endif + +`else // Hardware Cursor1 disabled, generate pass-through signals + assign ssel1_wreq = color_proc_wreq; + assign ssel1_q = color_proc_q; + + assign cc1_adr_o = 4'h0; + +`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled) + wire sddImDoneFifoQ, sdImDoneFifoQ; + + assign sdImDoneFifoQ = dImDoneFifoQ; + assign sddImDoneFifoQ = ddImDoneFifoQ; +`endif + +`endif + + +`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled) + wire cursor0_ld_strb; + reg scursor0_en; + reg scursor0_res; + reg [31:0] scursor0_xy; + + assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ; + + always@(posedge clk_i) + if (sclr) + scursor0_en <= #1 1'b0; + else if (cursor0_ld_strb) + scursor0_en <= #1 cursor0_en; + + always@(posedge clk_i) + if (cursor0_ld_strb) + scursor0_xy <= #1 cursor0_xy; + + always@(posedge clk_i) + if (cursor0_ld_strb) + scursor0_res <= #1 cursor0_res; + + vga_curproc hw_cursor0 ( + .clk(clk_i), + .rst_i(sclr), + .Thgate(Thgate), + .Tvgate(Tvgate), + .idat(ssel1_q), + .idat_wreq(ssel1_wreq), + .cursor_xy(scursor0_xy), + .cursor_en(scursor0_en), + .cursor_res(scursor0_res), + .cursor_wadr(cursor_adr), + .cursor_we(cursor0_we), + .cursor_wdat(dat_i), + .cc_adr_o(cc0_adr_o), + .cc_dat_i(cc0_dat_i), + .rgb_fifo_wreq(rgb_fifo_wreq), + .rgb(rgb_fifo_d) + ); +`else // Hardware Cursor0 disabled, generate pass-through signals + assign rgb_fifo_wreq = ssel1_wreq; + assign rgb_fifo_d = ssel1_q; + + assign cc0_adr_o = 4'h0; +`endif + + // + // hookup RGB buffer (temporary station between WISHBONE-clock-domain + // and pixel-clock-domain) + // The cursor_processor pipelines introduce a delay between the color + // processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate + // for this we double the rgb_fifo. + vga_fifo #(4, 24) rgb_fifo ( + .clk(clk_i), + .aclr(1'b1), + .sclr(sclr), + .d(rgb_fifo_d), + .wreq(rgb_fifo_wreq), + .q(line_fifo_d), + .rreq(rgb_fifo_rreq), + .empty(rgb_fifo_empty), + .hfull(rgb_fifo_full), + .full() + ); + + assign rgb_fifo_rreq = !line_fifo_full && !rgb_fifo_empty; + assign line_fifo_wreq = rgb_fifo_rreq; + +endmodule + + + + + Index: tags/rel_1/rtl/verilog/vga_wb_slave.v =================================================================== --- tags/rel_1/rtl/verilog/vga_wb_slave.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_wb_slave.v (revision 42) @@ -0,0 +1,443 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Wishbone slave interface //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_wb_slave.v,v 1.11 2002-04-20 10:02:39 rherveille Exp $ +// +// $Date: 2002-04-20 10:02:39 $ +// $Revision: 1.11 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.10 2002/03/28 04:59:25 rherveille +// Fixed two small bugs that only showed up when the hardware cursors were disabled +// +// Revision 1.9 2002/03/04 16:05:52 rherveille +// Added hardware cursor support to wishbone master. +// Added provision to turn-off 3D cursors. +// Fixed some minor bugs. +// +// Revision 1.8 2002/03/04 11:01:59 rherveille +// Added 64x64pixels 4bpp hardware cursor support. +// +// Revision 1.7 2002/02/25 06:13:44 rherveille +// Fixed dat_o incomplete sensitivity list. +// +// Revision 1.6 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + + +`include "timescale.v" +`include "vga_defines.v" + +module vga_wb_slave(clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, err_o, inta_o, + bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp, + cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o, + cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o, + vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in, + Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q); + + // + // inputs & outputs + // + + // wishbone slave interface + input clk_i; + input rst_i; + input arst_i; + input [11:2] adr_i; + input [31:0] dat_i; + output [31:0] dat_o; + reg [31:0] dat_o; + input [ 3:0] sel_i; + input we_i; + input stb_i; + input cyc_i; + output ack_o; + reg ack_o; + output err_o; + reg err_o; + output inta_o; + reg inta_o; + + // control register settings + output bl; // blanking level + output csl; // composite sync level + output vsl; // vsync level + output hsl; // hsync level + output pc; // pseudo color + output [1:0] cd; // color depth + output [1:0] vbl; // video memory burst length + output cbsw; // clut bank switch enable + output vbsw; // video memory bank switch enable + output ven; // video system enable + + // hardware cursor settings + output cursor0_res; // cursor0 resolution + output cursor0_en; // cursor0 enable + output [31: 0] cursor0_xy; // cursor0 location + output [31:11] cursor0_ba; // cursor0 base address + output cursor0_ld; // reload cursor0 from video memory + input [ 3: 0] cc0_adr_i; // cursor0 color register address + output [15: 0] cc0_dat_o; // cursor0 color register data + output cursor1_res; // cursor1 resolution + output cursor1_en; // cursor1 enable + output [31: 0] cursor1_xy; // cursor1 location + output [31:11] cursor1_ba; // cursor1 base address + output cursor1_ld; // reload cursor1 from video memory + input [ 3: 0] cc1_adr_i; // cursor1 color register address + output [15: 0] cc1_dat_o; // cursor1 color register data + + reg [31: 0] cursor0_xy; + reg [31:11] cursor0_ba; + reg cursor0_ld; + reg [31: 0] cursor1_xy; + reg [31:11] cursor1_ba; + reg cursor1_ld; + + // status register inputs + input avmp; // active video memory page + input acmp; // active clut memory page + input vbsint_in; // bank switch interrupt request + input cbsint_in; // clut switch interrupt request + input hint_in; // hsync interrupt request + input vint_in; // vsync interrupt request + input luint_in; // line fifo underrun interrupt request + input sint_in; // system error interrupt request + + // Horizontal Timing Register + output [ 7:0] Thsync; + output [ 7:0] Thgdel; + output [15:0] Thgate; + output [15:0] Thlen; + + // Vertical Timing Register + output [ 7:0] Tvsync; + output [ 7:0] Tvgdel; + output [15:0] Tvgate; + output [15:0] Tvlen; + + // video base addresses + output [31:2] VBARa; + reg [31:2] VBARa; + output [31:2] VBARb; + reg [31:2] VBARb; + + // color lookup table signals + output clut_acc; + input clut_ack; + input [23:0] clut_q; + + + // + // variable declarations + // + parameter REG_ADR_HIBIT = 7; + + wire [REG_ADR_HIBIT:0] REG_ADR = adr_i[REG_ADR_HIBIT : 2]; + wire CLUT_ADR = adr_i[11]; + + parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 6'b00_0000; + parameter [REG_ADR_HIBIT : 0] STAT_ADR = 6'b00_0001; + parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 6'b00_0010; + parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 6'b00_0011; + parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 6'b00_0100; + parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 6'b00_0101; + parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 6'b00_0110; + parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 6'b00_1100; + parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 6'b00_1101; + parameter [REG_ADR_HIBIT : 0] CCR0_ADR = 6'b01_0???; + parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 6'b01_1100; + parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 6'b01_1101; + parameter [REG_ADR_HIBIT : 0] CCR1_ADR = 6'b10_0???; + + + reg [31:0] ctrl, stat, htim, vtim, hvlen; + wire hint, vint, vbsint, cbsint, luint, sint; + wire hie, vie, vbsie, cbsie; + wire acc, acc32, reg_acc, reg_wacc; + wire cc0_acc, cc1_acc; + wire [31:0] ccr0_dat_o, ccr1_dat_o; + + + reg [31:0] reg_dato; // data output from registers + + // + // Module body + // + + assign acc = cyc_i & stb_i; + assign acc32 = (sel_i == 4'b1111); + assign clut_acc = CLUT_ADR & acc & acc32; + assign reg_acc = !CLUT_ADR & acc & acc32; + assign reg_wacc = reg_acc & we_i; + + assign cc0_acc = CCR0_ADR & acc & acc32; + assign cc1_acc = CCR1_ADR & acc & acc32; + + always@(posedge clk_i) + ack_o <= #1 ((reg_acc & acc32) | clut_ack) & !ack_o; + + always@(posedge clk_i) + err_o <= #1 acc & !acc32 & !err_o; + + + // generate registers + always@(posedge clk_i or negedge arst_i) + begin : gen_regs + if(!arst_i) + begin + htim <= #1 0; + vtim <= #1 0; + hvlen <= #1 0; + VBARa <= #1 0; + VBARb <= #1 0; + cursor0_xy <= #1 0; + cursor0_ba <= #1 0; + cursor1_xy <= #1 0; + cursor1_ba <= #1 0; + end + else if (rst_i) + begin + htim <= #1 0; + vtim <= #1 0; + hvlen <= #1 0; + VBARa <= #1 0; + VBARb <= #1 0; + cursor0_xy <= #1 0; + cursor0_ba <= #1 0; + cursor1_xy <= #1 0; + cursor1_ba <= #1 0; + end + else if (reg_wacc) + case (adr_i) // synopsis full_case parallel_case + HTIM_ADR : htim <= #1 dat_i; + VTIM_ADR : vtim <= #1 dat_i; + HVLEN_ADR : hvlen <= #1 dat_i; + VBARA_ADR : VBARa <= #1 dat_i[31: 2]; + VBARB_ADR : VBARb <= #1 dat_i[31: 2]; + C0XY_ADR : cursor0_xy <= #1 dat_i[31: 0]; + C0BAR_ADR : cursor0_ba <= #1 dat_i[31:11]; + C1XY_ADR : cursor1_xy <= #1 dat_i[31: 0]; + C1BAR_ADR : cursor1_ba <= #1 dat_i[31:11]; + endcase + end + + always@(posedge clk_i) + begin + cursor0_ld <= #1 reg_wacc && (adr_i == C0BAR_ADR); + cursor1_ld <= #1 reg_wacc && (adr_i == C1BAR_ADR); + end + + // generate control register + always@(posedge clk_i or negedge arst_i) + if (!arst_i) + ctrl <= #1 0; + else if (rst_i) + ctrl <= #1 0; + else if (reg_wacc & (REG_ADR == CTRL_ADR) ) + ctrl <= #1 dat_i; + else + begin + ctrl[6] <= #1 ctrl[6] & !cbsint_in; + ctrl[5] <= #1 ctrl[5] & !vbsint_in; + end + + + // generate status register + always@(posedge clk_i or negedge arst_i) + if (!arst_i) + stat <= #1 0; + else if (rst_i) + stat <= #1 0; + else + begin + `ifdef VGA_HWC1 + stat[21] <= #1 1'b1; + `else + stat[21] <= #1 1'b0; + `endif + `ifdef VGA_HWC0 + stat[20] <= #1 1'b1; + `else + stat[20] <= #1 1'b0; + `endif + + stat[17] <= #1 acmp; + stat[16] <= #1 avmp; + + if (reg_wacc & (REG_ADR == STAT_ADR) ) + begin + stat[7] <= #1 cbsint_in | (stat[7] & !dat_i[7]); + stat[6] <= #1 vbsint_in | (stat[6] & !dat_i[6]); + stat[5] <= #1 hint_in | (stat[5] & !dat_i[5]); + stat[4] <= #1 vint_in | (stat[4] & !dat_i[4]); + stat[1] <= #1 luint_in | (stat[3] & !dat_i[1]); + stat[0] <= #1 sint_in | (stat[0] & !dat_i[0]); + end + else + begin + stat[7] <= #1 stat[7] | cbsint_in; + stat[6] <= #1 stat[6] | vbsint_in; + stat[5] <= #1 stat[5] | hint_in; + stat[4] <= #1 stat[4] | vint_in; + stat[1] <= #1 stat[1] | luint_in; + stat[0] <= #1 stat[0] | sint_in; + end + end + + + // decode control register + assign cursor1_res = ctrl[25]; + assign cursor1_en = ctrl[24]; + assign cursor0_res = ctrl[23]; + assign cursor0_en = ctrl[20]; + assign bl = ctrl[15]; + assign csl = ctrl[14]; + assign vsl = ctrl[13]; + assign hsl = ctrl[12]; + assign pc = ctrl[11]; + assign cd = ctrl[10:9]; + assign vbl = ctrl[8:7]; + assign cbsw = ctrl[6]; + assign vbsw = ctrl[5]; + assign cbsie = ctrl[4]; + assign vbsie = ctrl[3]; + assign hie = ctrl[2]; + assign vie = ctrl[1]; + assign ven = ctrl[0]; + + // decode status register + assign cbsint = stat[7]; + assign vbsint = stat[6]; + assign hint = stat[5]; + assign vint = stat[4]; + assign luint = stat[1]; + assign sint = stat[0]; + + // decode Horizontal Timing Register + assign Thsync = htim[31:24]; + assign Thgdel = htim[23:16]; + assign Thgate = htim[15:0]; + assign Thlen = hvlen[31:16]; + + // decode Vertical Timing Register + assign Tvsync = vtim[31:24]; + assign Tvgdel = vtim[23:16]; + assign Tvgate = vtim[15:0]; + assign Tvlen = hvlen[15:0]; + + + `ifdef VGA_HWC0 + // hookup cursor0 color registers + vga_cur_cregs cregs0( + .clk_i(clk_i), + .rst_i(rst_i), + .arst_i(arst_i), + .hsel_i(cc0_acc), + .hadr_i(adr_i[4:2]), + .hwe_i(we_i), + .hdat_i(dat_i), + .hdat_o(ccr0_dat_o), // host access + .hack_o(), + .cadr_i(cc0_adr_i), + .cdat_o(cc0_dat_o) // cursor processor access + ); + `else + assign ccr0_dat_o = 32'h0; + assign cc0_dat_o = 32'h0; + `endif + + `ifdef VGA_HWC1 + // hookup cursor1 color registers + vga_cur_cregs cregs1( + .clk_i(clk_i), + .rst_i(rst_i), + .arst_i(arst_i), + .hsel_i(cc1_acc), + .hadr_i(adr_i[4:2]), + .hwe_i(we_i), + .hdat_i(dat_i), + .hdat_o(ccr1_dat_o), // host access + .hack_o(), + .cadr_i(cc1_adr_i), + .cdat_o(cc1_dat_o) // cursor processor access + ); + `else + assign ccr1_dat_o = 32'h0; + assign cc1_dat_o = 32'h0; + `endif + + + // assign output + always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or + cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba or ccr0_dat_o or ccr1_dat_o) + casez (REG_ADR) // synopsis full_case parallel_case + CTRL_ADR : reg_dato = ctrl; + STAT_ADR : reg_dato = stat; + HTIM_ADR : reg_dato = htim; + VTIM_ADR : reg_dato = vtim; + HVLEN_ADR : reg_dato = hvlen; + VBARA_ADR : reg_dato = {VBARa, 2'b0}; + VBARB_ADR : reg_dato = {VBARb, 2'b0}; + C0XY_ADR : reg_dato = cursor0_xy; + C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0}; + CCR0_ADR : reg_dato = ccr0_dat_o; + C1XY_ADR : reg_dato = cursor1_xy; + C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0}; + CCR1_ADR : reg_dato = ccr1_dat_o; + default : reg_dato = 32'h0000_0000; + endcase + + always@(posedge clk_i) + dat_o <= #1 reg_acc ? reg_dato : {8'h0, clut_q}; + + // generate interrupt request signal + always@(posedge clk_i) + inta_o <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint; +endmodule + + + Index: tags/rel_1/rtl/verilog/vga_pgen.v =================================================================== --- tags/rel_1/rtl/verilog/vga_pgen.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_pgen.v (revision 42) @@ -0,0 +1,151 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core; Pixel Generator //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_pgen.v,v 1.5 2002-04-05 06:24:35 rherveille Exp $ +// +// $Date: 2002-04-05 06:24:35 $ +// $Revision: 1.5 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2002/01/28 03:47:16 rherveille +// Changed counter-library. +// Changed vga-core. +// Added 32bpp mode. +// + +`include "timescale.v" + +module vga_pgen (mclk, pclk, ctrl_ven, ctrl_HSyncL, Thsync, Thgdel, Thgate, Thlen, + ctrl_VSyncL, Tvsync, Tvgdel, Tvgate, Tvlen, ctrl_CSyncL, ctrl_BlankL, + eoh, eov, gate, Hsync, Vsync, Csync, Blank); + + // inputs & outputs + + input mclk; // master clock + input pclk; // pixel clock + + input ctrl_ven; // Video enable signal + + // horiontal timing settings + input ctrl_HSyncL; // horizontal sync pulse polarization level (pos/neg) + input [ 7:0] Thsync; // horizontal sync pulse width (in pixels) + input [ 7:0] Thgdel; // horizontal gate delay (in pixels) + input [15:0] Thgate; // horizontal gate length (number of visible pixels per line) + input [15:0] Thlen; // horizontal length (number of pixels per line) + + // vertical timing settings + input ctrl_VSyncL; // vertical sync pulse polarization level (pos/neg) + input [ 7:0] Tvsync; // vertical sync pulse width (in lines) + input [ 7:0] Tvgdel; // vertical gate delay (in lines) + input [15:0] Tvgate; // vertical gate length (number of visible lines in frame) + input [15:0] Tvlen; // vertical length (number of lines in frame) + + // composite signals + input ctrl_CSyncL; // composite sync pulse polarization level + input ctrl_BlankL; // blank signal polarization level + + // status outputs + output eoh; // end of horizontal + reg eoh; + output eov; // end of vertical; + reg eov; + output gate; // vertical AND horizontal gate (logical AND function) + + // pixel control outputs + output Hsync; // horizontal sync pulse + output Vsync; // vertical sync pulse + output Csync; // composite sync: Hsync OR Vsync (logical OR function) + output Blank; // blanking signal + + + // + // variable declarations + // + reg nVen; // video enable signal (active low) + wire eol, eof; + + // + // module body + // + + // synchronize timing/control settings (from master-clock-domain to pixel-clock-domain) + always@(posedge pclk) + nVen <= #1 !ctrl_ven; + + // hookup video timing generator + vga_tgen vtgen(.clk(pclk), .rst(nVen), .HSyncL(ctrl_HSyncL), .Thsync(Thsync), .Thgdel(Thgdel), .Thgate(Thgate), .Thlen(Thlen), + .VSyncL(ctrl_VSyncL), .Tvsync(Tvsync), .Tvgdel(Tvgdel), .Tvgate(Tvgate), .Tvlen(Tvlen), .CSyncL(ctrl_CSyncL), .BlankL(ctrl_BlankL), + .eol(eol), .eof(eof), .gate(gate), .Hsync(Hsync), .Vsync(Vsync), .Csync(Csync), .Blank(Blank)); + + // + // from pixel-clock-domain to master-clock-domain + // + reg seol, seof; // synchronized end-of-line, end-of-frame + reg dseol, dseof; // delayed seol, seof + + always@(posedge mclk) + if (!ctrl_ven) + begin + seol <= #1 1'b0; + dseol <= #1 1'b0; + + seof <= #1 1'b0; + dseof <= #1 1'b0; + + eoh <= #1 1'b0; + eov <= #1 1'b0; + end + else + begin + seol <= #1 eol; + dseol <= #1 seol; + + seof <= #1 eof; + dseof <= #1 seof; + + eoh <= #1 seol & !dseol; + eov <= #1 seof & !dseof; + end + +endmodule + Index: tags/rel_1/rtl/verilog/vga_cur_cregs.v =================================================================== --- tags/rel_1/rtl/verilog/vga_cur_cregs.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_cur_cregs.v (revision 42) @@ -0,0 +1,128 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Hardware Cursor Color Registers //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_cur_cregs.v,v 1.2 2002-03-04 16:05:52 rherveille Exp $ +// +// $Date: 2002-03-04 16:05:52 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/03/04 11:01:59 rherveille +// Added 64x64pixels 4bpp hardware cursor support. +// +// + +`include "timescale.v" + +module vga_cur_cregs ( + clk_i, rst_i, arst_i, + hsel_i, hadr_i, hwe_i, hdat_i, hdat_o, hack_o, + cadr_i, cdat_o + ); + + // + // inputs & outputs + // + + // wishbone signals + input clk_i; // master clock input + input rst_i; // synchronous active high reset + input arst_i; // asynchronous active low reset + + // host interface + input hsel_i; // host select input + input [ 2:0] hadr_i; // host address input + input hwe_i; // host write enable input + input [31:0] hdat_i; // host data in + output [31:0] hdat_o; // host data out + output hack_o; // host acknowledge out + + reg [31:0] hdat_o; + reg hack_o; + + // cursor processor interface + input [ 3:0] cadr_i; // cursor address in + output [15:0] cdat_o; // cursor data out + + reg [15:0] cdat_o; + + + // + // variable declarations + // + reg [31:0] cregs [7:0]; // color registers + wire [31:0] temp_cdat; + + // + // module body + // + + + //////////////////////////// + // generate host interface + + // write section + always@(posedge clk_i) + if (hsel_i & hwe_i) + cregs[hadr_i] <= #1 hdat_i; + + // read section + always@(posedge clk_i) + hdat_o <= #1 cregs[hadr_i]; + + // acknowledge section + always@(posedge clk_i) + hack_o <= #1 hsel_i & !hack_o; + + + ////////////////////////////// + // generate cursor interface + + // read section + assign temp_cdat = cregs[cadr_i[3:1]]; + + always@(posedge clk_i) + cdat_o <= #1 cadr_i[0] ? temp_cdat[31:16] : temp_cdat[15:0]; + +endmodule + Index: tags/rel_1/rtl/verilog/vga_curproc.v =================================================================== --- tags/rel_1/rtl/verilog/vga_curproc.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_curproc.v (revision 42) @@ -0,0 +1,302 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Hardware Cursor Processor //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_curproc.v,v 1.3 2002-03-04 16:05:52 rherveille Exp $ +// +// $Date: 2002-03-04 16:05:52 $ +// $Revision: 1.3 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/03/04 11:01:59 rherveille +// Added 64x64pixels 4bpp hardware cursor support. +// +// Revision 1.1 2002/02/16 10:40:00 rherveille +// Some minor bug-fixes. +// Changed vga_ssel into vga_curproc (cursor processor). +// +// Revision 1.1 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +`include "timescale.v" + +module vga_curproc (clk, rst_i, Thgate, Tvgate, idat, idat_wreq, + cursor_xy, cursor_en, cursor_res, + cursor_wadr, cursor_wdat, cursor_we, + cc_adr_o, cc_dat_i, + rgb_fifo_wreq, rgb); + + // + // inputs & outputs + // + + // wishbone signals + input clk; // master clock input + input rst_i; // synchronous active high reset + + // image size + input [15:0] Thgate, Tvgate; // horizontal/vertical gate + // image data + input [23:0] idat; // image data input + input idat_wreq; // image data write request + + // cursor data + input [31:0] cursor_xy; // cursor (x,y) + input cursor_en; // cursor enable (on/off) + input cursor_res; // cursor resolution (32x32 or 64x64 pixels) + input [ 8:0] cursor_wadr; // cursor buffer write address + input [31:0] cursor_wdat; // cursor buffer write data + input cursor_we; // cursor buffer write enable + + // color registers interface + output [ 3:0] cc_adr_o; // cursor color registers address + reg [ 3:0] cc_adr_o; + input [15:0] cc_dat_i; // cursor color registers data + + // rgb-fifo connections + output rgb_fifo_wreq; // rgb-out write request + reg rgb_fifo_wreq; + output [23:0] rgb; // rgb data output + reg [23:0] rgb; + + // + // variable declarations + // + reg dcursor_en, ddcursor_en, dddcursor_en; + reg [15:0] xcnt, ycnt; + wire xdone, ydone; + wire [15:0] cursor_x, cursor_y; + wire cursor_isalpha; + reg [15:0] cdat, dcdat; + wire [ 7:0] cursor_r, cursor_g, cursor_b, cursor_alpha; + reg inbox_x, inbox_y; + wire inbox; + reg dinbox, ddinbox, dddinbox; + + reg [23:0] didat, ddidat, dddidat; + reg didat_wreq, ddidat_wreq; + wire [31:0] cbuf_q; + reg [11:0] cbuf_ra; + reg [ 2:0] dcbuf_ra; + wire [ 8:0] cbuf_a; + + reg store1, store2; + + // + // module body + // + + // + // generate x-y counters + always@(posedge clk) + if(rst_i || xdone) + xcnt <= #1 16'h0; + else if (idat_wreq) + xcnt <= #1 xcnt + 16'h1; + + assign xdone = (xcnt == Thgate) && idat_wreq; + + always@(posedge clk) + if(rst_i || ydone) + ycnt <= #1 16'h0; + else if (xdone) + ycnt <= #1 ycnt + 16'h1; + + assign ydone = (ycnt == Tvgate) && xdone; + + + // decode cursor (x,y) + assign cursor_x = cursor_xy[15: 0]; + assign cursor_y = cursor_xy[31:16]; + + // + // generate inbox signals + always@(posedge clk) + begin + inbox_x <= #1 (xcnt >= cursor_x) && (xcnt < (cursor_x + (cursor_res ? 16'h7f : 16'h1f) )); + inbox_y <= #1 (ycnt >= cursor_y) && (ycnt < (cursor_y + (cursor_res ? 16'h7f : 16'h1f) )); + end + + assign inbox = inbox_x && inbox_y; + + always@(posedge clk) + dinbox <= #1 inbox; + + always@(posedge clk) + if (didat_wreq) + ddinbox <= #1 dinbox; + + always@(posedge clk) + dddinbox <= #1 ddinbox; + + // + // generate cursor buffer address counter + always@(posedge clk) + if (!cursor_en || ydone) + cbuf_ra <= #1 12'h0; + else if (inbox && idat_wreq) + cbuf_ra <= #1 cbuf_ra +12'h1; + + always@(posedge clk) + dcbuf_ra <= #1 cbuf_ra[2:0]; + + assign cbuf_a = cursor_we ? cursor_wadr : cursor_res ? cbuf_ra[11:3] : cbuf_ra[9:1]; + + // hookup local cursor memory (generic synchronous single port memory) + // cursor memory should never be written to/read from at the same time + generic_spram #(9, 32) cbuf( + .clk(clk), + .rst(1'b0), // no reset + .ce(1'b1), // always enable memory + .we(cursor_we), + .oe(1'b1), // always output data + .addr(cbuf_a), + .di(cursor_wdat), + .do(cbuf_q) + ); + + // + // decode cursor data for 32x32x16bpp mode + always@(posedge clk) + if (didat_wreq) + cdat <= #1 dcbuf_ra[0] ? cbuf_q[31:16] : cbuf_q[15:0]; + + always@(posedge clk) + dcdat <= #1 cdat; + + // + // decode cursor data for 64x64x4bpp mode + + // generate cursor-color address + always@(posedge clk) + if (didat_wreq) + case (dcbuf_ra) + 3'b000: cc_adr_o <= cbuf_q[ 3: 0]; + 3'b001: cc_adr_o <= cbuf_q[ 7: 4]; + 3'b010: cc_adr_o <= cbuf_q[11: 8]; + 3'b011: cc_adr_o <= cbuf_q[15:12]; + 3'b100: cc_adr_o <= cbuf_q[19:16]; + 3'b101: cc_adr_o <= cbuf_q[23:20]; + 3'b110: cc_adr_o <= cbuf_q[27:24]; + 3'b111: cc_adr_o <= cbuf_q[31:28]; + endcase + + // + // generate cursor colors + assign cursor_isalpha = cursor_res ? cc_dat_i[15] : dcdat[15]; + assign cursor_alpha = cursor_res ? cc_dat_i[7:0] : dcdat[7:0]; + assign cursor_r = {cursor_res ? cc_dat_i[14:10] : dcdat[14:10], 3'h0}; + assign cursor_g = {cursor_res ? cc_dat_i[ 9: 5] : dcdat[ 9: 5], 3'h0}; + assign cursor_b = {cursor_res ? cc_dat_i[ 4: 0] : dcdat[ 4: 0], 3'h0}; + + // + // delay image data + always@(posedge clk) + didat <= #1 idat; + + always@(posedge clk) + if (didat_wreq) + ddidat <= #1 didat; + + always@(posedge clk) + dddidat <= #1 ddidat; + + always@(posedge clk) + begin + didat_wreq <= #1 idat_wreq; + ddidat_wreq <= #1 didat_wreq; + end + + // + // generate selection unit + always@(posedge clk) + dcursor_en <= #1 cursor_en; + + always@(posedge clk) + if (didat_wreq) + ddcursor_en <= #1 dcursor_en; + + always@(posedge clk) + dddcursor_en <= #1 ddcursor_en; + + // Alpha blending: + // rgb = (rgb1 * alhpa1) + (rgb2 * alpha2) + // We generate an alpha mixer (alpha1 + alpha2 = 1) + // rgb = (alpha1)(rgb1) + (1-alpha1)(rgb2) + // We always mix to black (rgb2 = 0) + // rgb = (alpha1)(rgb1) + always@(posedge clk) + if (ddidat_wreq) + if (!dddcursor_en || !dddinbox) + rgb <= #1 dddidat; + else if (cursor_isalpha) + `ifdef VGA_HWC_3D + rgb <= #1 dddidat * cursor_alpha; + `else + rgb <= #1 dddidat; + `endif + else + rgb <= #1 {cursor_r, cursor_g, cursor_b}; + + // + // generate write request signal + always@(posedge clk) + if (rst_i) + begin + store1 <= #1 1'b0; + store2 <= #1 1'b0; + end + else + begin + store1 <= #1 didat_wreq | store1; + store2 <= #1 (didat_wreq & store1) | store2; + end + + // skip 2 idat_wreq signal, to keep in pace with rgb_fifo_full signal + always@(posedge clk) + rgb_fifo_wreq <= #1 ddidat_wreq & store2; + +endmodule Index: tags/rel_1/rtl/verilog/vga_enh_top.v =================================================================== --- tags/rel_1/rtl/verilog/vga_enh_top.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_enh_top.v (revision 42) @@ -0,0 +1,392 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant Enhanced VGA/LCD Core //// +//// Top Level //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001,2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_enh_top.v,v 1.2 2002-03-04 11:01:59 rherveille Exp $ +// +// $Date: 2002-03-04 11:01:59 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +`include "timescale.v" +`include "vga_defines.v" + +module vga_enh_top (wb_clk_i, wb_rst_i, rst_i, wb_inta_o, + wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o, + wbm_adr_o, wbm_dat_i, wbm_cab_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i, + clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o); + + // + // parameters + // + parameter ARST_LVL = 1'b0; + parameter LINE_FIFO_AWIDTH = 7; + + // + // inputs & outputs + // + + // syscon interface + input wb_clk_i; // wishbone clock input + input wb_rst_i; // synchronous active high reset + input rst_i; // asynchronous reset + output wb_inta_o; // interrupt request output + + // slave signals + input [11:0] wbs_adr_i; // addressbus input (only 32bit databus accesses supported) + input [31:0] wbs_dat_i; // Slave databus output + output [31:0] wbs_dat_o; // Slave databus input + input [ 3:0] wbs_sel_i; // byte select inputs + input wbs_we_i; // write enabel input + input wbs_stb_i; // strobe/select input + input wbs_cyc_i; // valid bus cycle input + output wbs_ack_o; // bus cycle acknowledge output + output wbs_err_o; // bus cycle error output + + // master signals + output [31:0] wbm_adr_o; // addressbus output + input [31:0] wbm_dat_i; // Master databus input + output [ 3:0] wbm_sel_o; // byte select outputs + output wbm_we_o; // write enable output + output wbm_stb_o; // strobe output + output wbm_cyc_o; // valid bus cycle output + output wbm_cab_o; // continuos address burst output + input wbm_ack_i; // bus cycle acknowledge input + input wbm_err_i; // bus cycle error input + + // VGA signals + input clk_p_i; // pixel clock + output hsync_pad_o; // horizontal sync + reg hsync_pad_o; + output vsync_pad_o; // vertical sync + reg vsync_pad_o; + output csync_pad_o; // composite sync + reg csync_pad_o; + output blank_pad_o; // blanking signal + reg blank_pad_o; + output [ 7:0] r_pad_o, g_pad_o, b_pad_o; // RGB color signals + + // + // variable declarations + // + + // programable asynchronous reset + wire arst = rst_i ^ ARST_LVL; + + // from wb_slave + wire ctrl_bl, ctrl_csl, ctrl_vsl, ctrl_hsl, ctrl_pc, ctrl_cbsw, ctrl_vbsw, ctrl_ven; + wire [ 1: 0] ctrl_cd, ctrl_vbl; + wire [ 7: 0] Thsync, Thgdel, Tvsync, Tvgdel; + wire [15: 0] Thgate, Thlen, Tvgate, Tvlen; + wire [31: 2] VBARa, VBARb; + wire [31: 0] cursor0_xy, cursor1_xy; + wire cursor0_en, cursor1_en; + wire [31:11] cursor0_ba, cursor1_ba; + wire cursor0_ld, cursor1_ld; + wire cursor0_res, cursor1_res; + wire [15: 0] cc0_dat_o, cc1_dat_o; + + // to wb_slave + wire stat_avmp, stat_acmp, vmem_swint, clut_swint, hint, vint, sint; + reg luint; + wire [ 3: 0] cc0_adr_i, cc1_adr_i; + + // from pixel generator + wire cgate; // composite gate signal + wire ihsync, ivsync, icsync, iblank; // intermediate horizontal/vertical/composite sync, intermediate blank + + // line fifo connections + wire line_fifo_dpm_wreq; + wire [23:0] line_fifo_dpm_d, line_fifo_dpm_q; + + // clut connections + wire ext_clut_req, ext_clut_ack; + wire [23:0] ext_clut_q; + wire cp_clut_req, cp_clut_ack; + wire [ 8:0] cp_clut_adr; + wire [23:0] cp_clut_q; + + // + // Module body + // + + // hookup wishbone slave + vga_wb_slave u1 ( + // wishbone interface + .clk_i(wb_clk_i), + .rst_i(wb_rst_i), + .arst_i(arst), + .adr_i(wbs_adr_i[11:2]), + .dat_i(wbs_dat_i), + .dat_o(wbs_dat_o), + .sel_i(wbs_sel_i), + .we_i(wbs_we_i), + .stb_i(wbs_stb_i), + .cyc_i(wbs_cyc_i), + .ack_o(wbs_ack_o), + .err_o(wbs_err_o), + .inta_o(wb_inta_o), + + // internal connections + .bl(ctrl_bl), // blank polarization level + .csl(ctrl_csl), // csync polarization level + .vsl(ctrl_vsl), // vsync polarization level + .hsl(ctrl_hsl), // hsync polarization level + .pc(ctrl_pc), // pseudo-color mode (only for 8bpp) + .cd(ctrl_cd), // color depth + .vbl(ctrl_vbl), // video memory burst length + .cbsw(ctrl_cbsw), // color lookup table bank switch enable + .vbsw(ctrl_vbsw), // video bank switch enable + .ven(ctrl_ven), // video enable + .acmp(stat_acmp), // active color lookup table page + .avmp(stat_avmp), // active video memory page + .cursor0_res(cursor0_res), // cursor0 resolution + .cursor0_en(cursor0_en), // cursor0 enable + .cursor0_xy(cursor0_xy), // cursor0 (x,y) + .cursor0_ba(cursor0_ba), // curso0 video memory base address + .cursor0_ld(cursor0_ld), // reload curso0 from video memory + .cc0_adr_i(cc0_adr_i), // cursor0 color registers address + .cc0_dat_o(cc0_dat_o), // cursor0 color registers data + .cursor1_res(cursor1_res), // cursor1 resolution + .cursor1_en(cursor1_en), // cursor1 enable + .cursor1_xy(cursor1_xy), // cursor1 (x,y) + .cursor1_ba(cursor1_ba), // cursor1 video memory base address + .cursor1_ld(cursor1_ld), // reload cursor1 from video memory + .cc1_adr_i(cc1_adr_i), // cursor1 color registers address + .cc1_dat_o(cc1_dat_o), // cursor1 color registers data + .vbsint_in(vmem_swint), // video memory bank switch interrupt + .cbsint_in(clut_swint), // clut memory bank switch interrupt + .hint_in(hint), // horizontal interrupt + .vint_in(vint), // vertical interrupt + .luint_in(luint), // line fifo underrun interrupt + .sint_in(sint), // system-error interrupt + .Thsync(Thsync), + .Thgdel(Thgdel), + .Thgate(Thgate), + .Thlen(Thlen), + .Tvsync(Tvsync), + .Tvgdel(Tvgdel), + .Tvgate(Tvgate), + .Tvlen(Tvlen), + .VBARa(VBARa), + .VBARb(VBARb), + .clut_acc(ext_clut_req), + .clut_ack(ext_clut_ack), + .clut_q(ext_clut_q) + ); + + // hookup wishbone master + vga_wb_master u2 ( + // wishbone interface + .clk_i(wb_clk_i), + .rst_i(wb_rst_i), + .nrst_i(arst), + .cyc_o(wbm_cyc_o), + .stb_o(wbm_stb_o), + .cab_o(wbm_cab_o), + .we_o(wbm_we_o), + .adr_o(wbm_adr_o), + .sel_o(wbm_sel_o), + .ack_i(wbm_ack_i), + .err_i(wbm_err_i), + .dat_i(wbm_dat_i), + + // internal connections + .sint(sint), + .ctrl_ven(ctrl_ven), + .ctrl_cd(ctrl_cd), + .ctrl_pc(ctrl_pc), + .ctrl_vbl(ctrl_vbl), + .ctrl_cbsw(ctrl_cbsw), + .ctrl_vbsw(ctrl_vbsw), + .cursor0_en(cursor0_en), // cursor0 enable + .cursor0_res(cursor0_res), // cursor0 resolution + .cursor0_xy(cursor0_xy), // cursor0 (x,y) + .cursor0_ba(cursor0_ba), // curso0 video memory base address + .cursor0_ld(cursor0_ld), // reload curso0 from video memory + .cc0_adr_o(cc0_adr_i), // cursor0 color registers address + .cc0_dat_i(cc0_dat_o), // cursor0 color registers data + .cursor1_en(cursor1_en), // cursor1 enable + .cursor1_res(cursor1_res), // cursor1 resolution + .cursor1_xy(cursor1_xy), // cursor1 (x,y) + .cursor1_ba(cursor1_ba), // cursor1 video memory base address + .cursor1_ld(cursor1_ld), // reload cursor1 from video memory + .cc1_adr_o(cc1_adr_i), // cursor1 color registers address + .cc1_dat_i(cc1_dat_o), // cursor1 color registers data + .VBAa(VBARa), + .VBAb(VBARb), + .Thgate(Thgate), + .Tvgate(Tvgate), + .stat_acmp(stat_acmp), + .stat_avmp(stat_avmp), + .vmem_switch(vmem_swint), + .clut_switch(clut_swint), + + // line fifo memory signals + .line_fifo_wreq(line_fifo_dpm_wreq), + .line_fifo_d(line_fifo_dpm_d), + .line_fifo_full(line_fifo_full_wr), + + // clut memory signals + .clut_req(cp_clut_req), + .clut_ack(cp_clut_ack), + .clut_adr(cp_clut_adr), + .clut_q(cp_clut_q) + ); + + // hookup CLUT + vga_csm_pb #(24, 9) clut_mem( + .clk_i(wb_clk_i), + + // color processor access + .req0_i(cp_clut_req), + .ack0_o(cp_clut_ack), + .adr0_i(cp_clut_adr), + .dat0_i(24'h0), + .dat0_o(cp_clut_q), + .we0_i(1'b0), // no writes + + // external access + .req1_i(ext_clut_req), + .ack1_o(ext_clut_ack), + .adr1_i(wbs_adr_i[10:2]), + .dat1_i(wbs_dat_i[23:0]), + .dat1_o(ext_clut_q), + .we1_i(wbs_we_i) + ); + + // hookup pixel and video timing generator + vga_pgen u3 ( + .mclk(wb_clk_i), + .pclk(clk_p_i), + .ctrl_ven(ctrl_ven), + .ctrl_HSyncL(ctrl_hsl), + .Thsync(Thsync), + .Thgdel(Thgdel), + .Thgate(Thgate), + .Thlen(Thlen), + .ctrl_VSyncL(ctrl_vsl), + .Tvsync(Tvsync), + .Tvgdel(Tvgdel), + .Tvgate(Tvgate), + .Tvlen(Tvlen), + .ctrl_CSyncL(ctrl_csl), + .ctrl_BlankL(ctrl_bl), + .eoh(hint), + .eov(vint), + .gate(cgate), + .Hsync(ihsync), + .Vsync(ivsync), + .Csync(icsync), + .Blank(iblank) + ); + + + // delay video control signals 1 clock cycle (dual clock fifo synchronizes output) + always@(posedge clk_p_i) + begin + hsync_pad_o <= #1 ihsync; + vsync_pad_o <= #1 ivsync; + csync_pad_o <= #1 icsync; + blank_pad_o <= #1 iblank; + end + + // hookup line-fifo + vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) u4 ( + .rclk(clk_p_i), + .wclk(wb_clk_i), + .aclr(ctrl_ven), + .wreq(line_fifo_dpm_wreq), + .d(line_fifo_dpm_d), + .rreq(cgate), + .q(line_fifo_dpm_q), + .rd_empty(line_fifo_empty_rd), + .rd_full(), + .wr_empty(), + .wr_full(line_fifo_full_wr) + ); + + assign r_pad_o = line_fifo_dpm_q[23:16]; + assign g_pad_o = line_fifo_dpm_q[15: 8]; + assign b_pad_o = line_fifo_dpm_q[ 7: 0]; + + // generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt) + reg luint_pclk, sluint; + + always@(posedge clk_p_i) + luint_pclk <= #1 cgate & line_fifo_empty_rd; + + always@(posedge wb_clk_i or negedge arst) + if (!arst) + begin + sluint <= #1 1'b0; + luint <= #1 1'b0; + end + else if (wb_rst_i) + begin + sluint <= #1 1'b0; + luint <= #1 1'b0; + end + else if (!ctrl_ven) + begin + sluint <= #1 1'b0; + luint <= #1 1'b0; + end + else + begin + sluint <= #1 luint_pclk; // resample at wb_clk_i clock + luint <= #1 sluint; // sample again, reduce metastability risk + end + +endmodule + + + + + Index: tags/rel_1/rtl/verilog/vga_colproc.v =================================================================== --- tags/rel_1/rtl/verilog/vga_colproc.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_colproc.v (revision 42) @@ -0,0 +1,499 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core //// +//// Enhanced Color Processor //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_colproc.v,v 1.7 2002-03-04 11:01:59 rherveille Exp $ +// +// $Date: 2002-03-04 11:01:59 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.6 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +`include "timescale.v" + +module vga_colproc(clk, srst, vdat_buffer_di, ColorDepth, PseudoColor, + vdat_buffer_empty, vdat_buffer_rreq, rgb_fifo_full, + rgb_fifo_wreq, r, g, b, + clut_req, clut_ack, clut_offs, clut_q); + + // + // inputs & outputs + // + input clk; // master clock + input srst; // synchronous reset + + input [31:0] vdat_buffer_di; // video memory data input + + input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp) + input PseudoColor; // pseudo color enabled (only for 8bpp color depth) + + input vdat_buffer_empty; + output vdat_buffer_rreq; // pixel buffer read request + reg vdat_buffer_rreq; + + input rgb_fifo_full; + output rgb_fifo_wreq; + reg rgb_fifo_wreq; + output [7:0] r, g, b; // pixel color information + reg [7:0] r, g, b; + + output clut_req; // clut request + reg clut_req; + input clut_ack; // clut acknowledge + output [ 7:0] clut_offs; // clut offset + reg [7:0] clut_offs; + input [23:0] clut_q; // clut data in + + // + // variable declarations + // + reg [31:0] DataBuffer; + + reg [7:0] Ra, Ga, Ba; + reg [1:0] colcnt; + reg RGBbuf_wreq; + + // + // Module body + // + + // store word from pixelbuffer / wishbone input + always@(posedge clk) + if (vdat_buffer_rreq) + DataBuffer <= #1 vdat_buffer_di; + + // + // generate statemachine + // + // extract color information from data buffer + parameter idle = 7'b000_0000, + fill_buf = 7'b000_0001, + bw_8bpp = 7'b000_0010, + col_8bpp = 7'b000_0100, + col_16bpp_a = 7'b000_1000, + col_16bpp_b = 7'b001_0000, + col_24bpp = 7'b010_0000, + col_32bpp = 7'b100_0000; + + reg [6:0] c_state; // synopsys enum_state + reg [6:0] nxt_state; // synopsys enum_state + + // next state decoder + always@(c_state or vdat_buffer_empty or ColorDepth or PseudoColor or rgb_fifo_full or colcnt or clut_ack) + begin : nxt_state_decoder + // initial value + nxt_state = c_state; + + case (c_state) // synopsis full_case parallel_case + // idle state + idle: + if (!vdat_buffer_empty && !rgb_fifo_full) + nxt_state = fill_buf; + + // fill data buffer + fill_buf: + case (ColorDepth) // synopsis full_case parallel_case + 2'b00: + if (PseudoColor) + nxt_state = col_8bpp; + else + nxt_state = bw_8bpp; + + 2'b01: + nxt_state = col_16bpp_a; + + 2'b10: + nxt_state = col_24bpp; + + 2'b11: + nxt_state = col_32bpp; + + endcase + + // + // 8 bits per pixel + // + bw_8bpp: + if (!rgb_fifo_full && !(|colcnt) ) + if (!vdat_buffer_empty) + nxt_state = fill_buf; + else + nxt_state = idle; + + col_8bpp: + // Do NOT check for rgb_fifo_full here. + // In 8bpp pseudo-color mode the color-processor must always finish + // the current 4pixel-block(i.e. it runs until colcnt = '11'). + // This is because of the late clut-response which shuffles all + // signals the state-machine depends on. + // Because of this we can not do an early video_memory_data fetch, + // i.e. we can not jump to the fill_buf state. Instead we always + // jump to idle and check for rgb_fifo_full there. + // + // The addition of the cursor-processors forces us to increase the + // rgb-fifo size. The increased rgb-fifo also handles the above + // described problem. Thus erradicating the above comment. + // We add the early video_memory_data fetch again. + if (!(|colcnt)) + if (!vdat_buffer_empty && !rgb_fifo_full) + nxt_state = fill_buf; + else + nxt_state = idle; + + // + // 16 bits per pixel + // + col_16bpp_a: + if (!rgb_fifo_full) + nxt_state = col_16bpp_b; + + col_16bpp_b: + if (!rgb_fifo_full) + if (!vdat_buffer_empty) + nxt_state = fill_buf; + else + nxt_state = idle; + + // + // 24 bits per pixel + // + col_24bpp: + if (!rgb_fifo_full) + if (colcnt == 2'h1) // (colcnt == 1) + nxt_state = col_24bpp; // stay in current state + else if (!vdat_buffer_empty) + nxt_state = fill_buf; + else + nxt_state = idle; + + // + // 32 bits per pixel + // + col_32bpp: + if (!rgb_fifo_full) + if (!vdat_buffer_empty) + nxt_state = fill_buf; + else + nxt_state = idle; + endcase + end // next state decoder + + // generate state registers + always@(posedge clk) + if (srst) + c_state <= #1 idle; + else + c_state <= #1 nxt_state; + + + reg iclut_req; + reg ivdat_buf_rreq; + reg [7:0] iR, iG, iB, iRa, iGa, iBa; + + // output decoder + always@(c_state or vdat_buffer_empty or colcnt or DataBuffer or rgb_fifo_full or clut_ack or clut_q or Ba or Ga or Ra) + begin : output_decoder + + // initial values + ivdat_buf_rreq = 1'b0; + RGBbuf_wreq = 1'b0; + iclut_req = 1'b0; + + iR = 'h0; + iG = 'h0; + iB = 'h0; + iRa = 'h0; + iGa = 'h0; + iBa = 'h0; + + case (c_state) // synopsis full_case parallel_case + idle: + begin + if (!rgb_fifo_full) + if (!vdat_buffer_empty) + ivdat_buf_rreq = 1'b1; + + // when entering from 8bpp_pseudo_color_mode + RGBbuf_wreq = clut_ack; + + iR = clut_q[23:16]; + iG = clut_q[15: 8]; + iB = clut_q[ 7: 0]; + end + + fill_buf: + begin + // when entering from 8bpp_pseudo_color_mode + RGBbuf_wreq = clut_ack; + + iR = clut_q[23:16]; + iG = clut_q[15: 8]; + iB = clut_q[ 7: 0]; + end + + // + // 8 bits per pixel + // + bw_8bpp: + begin + if (!rgb_fifo_full) + begin + RGBbuf_wreq = 1'b1; + + if ( (!vdat_buffer_empty) && !(|colcnt) ) + ivdat_buf_rreq = 1'b1; + end + + case (colcnt) // synopsis full_case parallel_case + 2'b11: + begin + iR = DataBuffer[31:24]; + iG = DataBuffer[31:24]; + iB = DataBuffer[31:24]; + end + + 2'b10: + begin + iR = DataBuffer[23:16]; + iG = DataBuffer[23:16]; + iB = DataBuffer[23:16]; + end + + 2'b01: + begin + iR = DataBuffer[15:8]; + iG = DataBuffer[15:8]; + iB = DataBuffer[15:8]; + end + + default: + begin + iR = DataBuffer[7:0]; + iG = DataBuffer[7:0]; + iB = DataBuffer[7:0]; + end + endcase + end + + col_8bpp: + begin + // Do NOT check for rgb_fifo_full here. + // In 8bpp pseudo-color mode the color-processor must always finish + // the current 4pixel-block(i.e. it runs until colcnt = '11'). + // This is because of the late clut-response which shuffles all + // signals the state-machine depends on. + // Because of this we can not do an early video_memory_data fetch, + // i.e. we can not jump to the fill_buf state. Instead we always + // jump to idle and check for rgb_fifo_full there. + // + // The addition of the cursor-processors forces us to increase the + // rgb-fifo size. The increased rgb-fifo also handles the above + // described problem. Thus erradicating the above comment. + // We add the early video_memory_data fetch again. + if (!(|colcnt)) + if (!vdat_buffer_empty && !rgb_fifo_full) + ivdat_buf_rreq = 1'b1; + + RGBbuf_wreq = clut_ack; + + iR = clut_q[23:16]; + iG = clut_q[15: 8]; + iB = clut_q[ 7: 0]; + + iclut_req = !rgb_fifo_full || (colcnt[1] ^ colcnt[0]); + end + + // + // 16 bits per pixel + // + col_16bpp_a: + begin + if (!rgb_fifo_full) + RGBbuf_wreq = 1'b1; + + iR[7:3] = DataBuffer[31:27]; + iG[7:2] = DataBuffer[26:21]; + iB[7:3] = DataBuffer[20:16]; + end + + col_16bpp_b: + begin + if (!rgb_fifo_full) + begin + RGBbuf_wreq = 1'b1; + + if (!vdat_buffer_empty) + ivdat_buf_rreq = 1'b1; + end + + iR[7:3] = DataBuffer[15:11]; + iG[7:2] = DataBuffer[10: 5]; + iB[7:3] = DataBuffer[ 4: 0]; + end + + // + // 24 bits per pixel + // + col_24bpp: + begin + if (!rgb_fifo_full) + begin + RGBbuf_wreq = 1'b1; + + if ( (colcnt != 2'h1) && !vdat_buffer_empty) + ivdat_buf_rreq = 1'b1; + end + + + case (colcnt) // synopsis full_case parallel_case + 2'b11: + begin + iR = DataBuffer[31:24]; + iG = DataBuffer[23:16]; + iB = DataBuffer[15: 8]; + iRa = DataBuffer[ 7: 0]; + end + + 2'b10: + begin + iR = Ra; + iG = DataBuffer[31:24]; + iB = DataBuffer[23:16]; + iRa = DataBuffer[15: 8]; + iGa = DataBuffer[ 7: 0]; + end + + 2'b01: + begin + iR = Ra; + iG = Ga; + iB = DataBuffer[31:24]; + iRa = DataBuffer[23:16]; + iGa = DataBuffer[15: 8]; + iBa = DataBuffer[ 7: 0]; + end + + default: + begin + iR = Ra; + iG = Ga; + iB = Ba; + end + endcase + end + + // + // 32 bits per pixel + // + col_32bpp: + begin + if (!rgb_fifo_full) + begin + RGBbuf_wreq = 1'b1; + + if (!vdat_buffer_empty) + ivdat_buf_rreq = 1'b1; + end + + iR[7:0] = DataBuffer[23:16]; + iG[7:0] = DataBuffer[15:8]; + iB[7:0] = DataBuffer[7:0]; + end + + endcase + end // output decoder + + // generate output registers + always@(posedge clk) + begin + r <= #1 iR; + g <= #1 iG; + b <= #1 iB; + + if (RGBbuf_wreq) + begin + Ra <= #1 iRa; + Ba <= #1 iBa; + Ga <= #1 iGa; + end + + if (srst) + begin + vdat_buffer_rreq <= #1 1'b0; + rgb_fifo_wreq <= #1 1'b0; + clut_req <= #1 1'b0; + end + else + begin + vdat_buffer_rreq <= #1 ivdat_buf_rreq; + rgb_fifo_wreq <= #1 RGBbuf_wreq; + clut_req <= #1 iclut_req; + end + end + + // assign clut offset + always@(colcnt or DataBuffer) + case (colcnt) // synopsis full_case parallel_case + 2'b11: clut_offs = DataBuffer[31:24]; + 2'b10: clut_offs = DataBuffer[23:16]; + 2'b01: clut_offs = DataBuffer[15: 8]; + 2'b00: clut_offs = DataBuffer[ 7: 0]; + endcase + + + // + // color counter + // + always@(posedge clk) + if(srst) + colcnt <= #1 2'b11; + else if (RGBbuf_wreq) + colcnt <= #1 colcnt -2'h1; +endmodule + + Index: tags/rel_1/rtl/verilog/vga_fifo.v =================================================================== --- tags/rel_1/rtl/verilog/vga_fifo.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_fifo.v (revision 42) @@ -0,0 +1,140 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core; Universal Fifo //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_fifo.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $ +// +// $Date: 2002-02-07 05:42:10 $ +// $Revision: 1.6 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + +`include "timescale.v" + +module vga_fifo (clk, aclr, sclr, d, wreq, q, rreq, empty, hfull, full); + + // + // parameters + // + + parameter AWIDTH = 7; // 128 entries + parameter DWIDTH = 32; // 32bits data + + // + // inputs & outputs + // + + input clk; // clock input + input aclr; // active low asynchronous clear + input sclr; // active high synchronous clear + + input [DWIDTH -1:0] d; // data input + input wreq; // write request + + output [DWIDTH -1:0] q; // data output +// reg [DWIDTH -1:0] q; + input rreq; // read request + + output empty; // fifo is empty + output hfull; // fifo is half full + output full; // fifo is full + + + // + // variable declarations + // + parameter DEPTH = 1 << AWIDTH; + + reg [DWIDTH -1:0] mem [DEPTH -1:0]; + + reg [AWIDTH -1:0] rptr, wptr; + reg [AWIDTH :0] fifo_cnt; + + // + // Module body + // + + // read pointer + always@(posedge clk or negedge aclr) + if (!aclr) + rptr <= #1 0; + else if (sclr) + rptr <= #1 0; + else if (rreq) + rptr <= #1 rptr + 1; + + // write pointer + always@(posedge clk or negedge aclr) + if (!aclr) + wptr <= #1 0; + else if (sclr) + wptr <= #1 0; + else if (wreq) + wptr <= #1 wptr + 1; + + // memory array operations + always@(posedge clk) + if (wreq) + mem[wptr] <= #1 d; + + assign q = mem[rptr]; + + // number of words in fifo + always@(posedge clk or negedge aclr) + if (!aclr) + fifo_cnt <= #1 0; + else if (sclr) + fifo_cnt <= #1 0; + else + begin + if (wreq & !rreq) + fifo_cnt <= #1 fifo_cnt + 1; + else if (rreq & !wreq) + fifo_cnt <= #1 fifo_cnt - 1; + end + + // status flags + assign empty = !(|fifo_cnt); + assign hfull = fifo_cnt[AWIDTH -1] | fifo_cnt[AWIDTH]; + assign full = fifo_cnt[AWIDTH]; +endmodule + Index: tags/rel_1/rtl/verilog/vga_csm_pb.v =================================================================== --- tags/rel_1/rtl/verilog/vga_csm_pb.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_csm_pb.v (revision 42) @@ -0,0 +1,143 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core; CycleShared Memory //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_csm_pb.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $ +// +// $Date: 2002-02-07 05:42:10 $ +// $Revision: 1.6 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + +`include "timescale.v" + +module vga_csm_pb (clk_i, req0_i, ack0_o, adr0_i, dat0_i, dat0_o, we0_i, req1_i, ack1_o, adr1_i, dat1_i, dat1_o, we1_i); + + // + // parameters + // + parameter DWIDTH = 32; // databus width + parameter AWIDTH = 8; // address bus width + + // + // inputs & outputs + // + + input clk_i; // clock input + + // wishbone slave0 connections + input [ AWIDTH -1:0] adr0_i; // address input + input [ DWIDTH -1:0] dat0_i; // data input + output [ DWIDTH -1:0] dat0_o; // data output + input we0_i; // write enable input + input req0_i; // access request input + output ack0_o; // access acknowledge output + + // wishbone slave1 connections + input [ AWIDTH -1:0] adr1_i; // address input + input [ DWIDTH -1:0] dat1_i; // data input + output [ DWIDTH -1:0] dat1_o; // data output + input we1_i; // write enable input + input req1_i; // access request input + output ack1_o; // access acknowledge output + + // + // variable declarations + // + + // multiplexor select signal + wire acc0, acc1; + reg dacc0, dacc1; + wire sel0, sel1; + reg ack0, ack1; + + // memory data output + wire [DWIDTH -1:0] mem_q; + + + // + // module body + // + + // generate multiplexor select signal + assign acc0 = req0_i; + assign acc1 = req1_i && !sel0; + + always@(posedge clk_i) + begin + dacc0 <= #1 acc0 & !ack0_o; + dacc1 <= #1 acc1 & !ack1_o; + end + + assign sel0 = acc0 && !dacc0; + assign sel1 = acc1 && !dacc1; + + always@(posedge clk_i) + begin + ack0 <= #1 sel0 && !ack0_o; + ack1 <= #1 sel1 && !ack1_o; + end + + wire [AWIDTH -1:0] mem_adr = sel0 ? adr0_i : adr1_i; + wire [DWIDTH -1:0] mem_d = sel0 ? dat0_i : dat1_i; + wire mem_we = sel0 ? req0_i && we0_i : req1_i && we1_i; + + // hookup generic synchronous single port memory + generic_spram #(AWIDTH, DWIDTH) clut_mem( + .clk(clk_i), + .rst(1'b0), // no reset + .ce(1'b1), // always enable memory + .we(mem_we), + .oe(1'b1), // always output data + .addr(mem_adr), + .di(mem_d), + .do(mem_q) + ); + + // assign DAT_O outputs + assign dat0_o = mem_q; + assign dat1_o = mem_q; + + // generate ack outputs + assign ack0_o = ( (sel0 && we0_i) || ack0 ); + assign ack1_o = ( (sel1 && we1_i) || ack1 ); +endmodule Index: tags/rel_1/rtl/verilog/vga_defines.v =================================================================== --- tags/rel_1/rtl/verilog/vga_defines.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_defines.v (revision 42) @@ -0,0 +1,62 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Defines file //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_defines.v,v 1.4 2002-02-07 05:42:10 rherveille Exp $ +// +// $Date: 2002-02-07 05:42:10 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + + +// +// define memory vendor +// + +`define VENDOR_FPGA + +// +// enable / disable hardware cursors +// +//`define VGA_HWC0 +//`define VGA_HWC1 \ No newline at end of file Index: tags/rel_1/rtl/verilog/ud_cnt.v =================================================================== --- tags/rel_1/rtl/verilog/ud_cnt.v (nonexistent) +++ tags/rel_1/rtl/verilog/ud_cnt.v (revision 42) @@ -0,0 +1,100 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Generic Up/Down counter //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ud_cnt.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $ +// +// $Date: 2002-01-28 03:47:16 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + + +///////////////////////////// +// general purpose counter // +///////////////////////////// + +`include "timescale.v" + +module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco); + // parameter declaration + parameter SIZE = 8; + parameter RESD = {SIZE{1'b0}}; // data after reset + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + input cnt_en; // count enable + input ud; // up/not down + input nld; // synchronous active low load + input [SIZE-1:0] d; // load counter value + output [SIZE-1:0] q; // current counter value + input rci; // carry input + output rco; // carry output + + // variable declarations + reg [SIZE-1:0] Qi; // intermediate value + wire [SIZE:0] val; // carry+result + + // + // Module body + // + + assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci); + + always@(posedge clk or negedge nReset) + begin + if (~nReset) + Qi <= #1 RESD; + else if (rst) + Qi <= #1 RESD; + else if (~nld) + Qi <= #1 d; + else if (cnt_en) + Qi <= #1 val[SIZE-1:0]; + end + + // assign outputs + assign q = Qi; + assign rco = val[SIZE]; +endmodule + + Index: tags/rel_1/rtl/verilog/ro_cnt.v =================================================================== --- tags/rel_1/rtl/verilog/ro_cnt.v (nonexistent) +++ tags/rel_1/rtl/verilog/ro_cnt.v (revision 42) @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Run-Once counter //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ro_cnt.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $ +// +// $Date: 2002-01-28 03:47:16 $ +// $Revision: 1.5 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + + +/////////////////////////// +// run-once down-counter // +/////////////////////////// + +// counts D+1 cycles before generating 'DONE' + +`include "timescale.v" + +module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q); + + // parameter declaration + parameter SIZE = 8; + + parameter UD = 1'b0; // default count down + parameter ID = {SIZE{1'b0}}; // initial data after reset + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + input cnt_en; // count enable + input go; // load counter and start sequence + output done; // done counting + input [SIZE-1:0] d; // load counter value + output [SIZE-1:0] q; // current counter value + + // variable declarations + reg rci; + wire nld, rco; + + // + // module body + // + + always@(posedge clk or negedge nReset) + if (~nReset) + rci <= #1 1'b0; + else if (rst) + rci <= #1 1'b0; + else //if (cnt_en) + rci <= #1 go | (rci & !rco); + + assign nld = !go; + + // hookup counter + ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en), + .ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco)); + + + // assign outputs + + assign done = rco; + +endmodule + + + Index: tags/rel_1/rtl/verilog/vga_fifo_dc.v =================================================================== --- tags/rel_1/rtl/verilog/vga_fifo_dc.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_fifo_dc.v (revision 42) @@ -0,0 +1,166 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core; Dual Clocked Fifo //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_fifo_dc.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $ +// +// $Date: 2002-01-28 03:47:16 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + + +`include "timescale.v" + +module vga_fifo_dc (rclk, wclk, aclr, wreq, d, rreq, q, rd_empty, rd_full, wr_empty, wr_full); + + // parameters + parameter AWIDTH = 7; //128 entries + parameter DWIDTH = 16; //16bit databus + + // inputs & outputs + input rclk; // read clock + input wclk; // write clock + input aclr; // active low asynchronous clear + input wreq; // write request + input [DWIDTH -1:0] d; // data input + input rreq; // read request + output [DWIDTH -1:0] q; // data output + + output rd_empty; // FIFO is empty, synchronous to read clock + reg rd_empty; + output rd_full; // FIFO is full, synchronous to read clock + reg rd_full; + output wr_empty; // FIFO is empty, synchronous to write clock + reg wr_empty; + output wr_full; // FIFO is full, synchronous to write clock + reg wr_full; + + // variable declarations + reg [AWIDTH -1:0] rptr, wptr; + wire ifull, iempty; + reg rempty, rfull, wempty, wfull; + + // + // module body + // + + + // + // Pointers + // + // read pointer + always@(posedge rclk or negedge aclr) + if (~aclr) + rptr <= #1 0; + else if (rreq) + rptr <= #1 rptr + 1; + + // write pointer + always@(posedge wclk or negedge aclr) + if (~aclr) + wptr <= #1 0; + else if (wreq) + wptr <= #1 wptr +1; + + // + // status flags + // + wire [AWIDTH -1:0] tmp; + wire [AWIDTH -1:0] tmp2; + assign tmp = wptr - rptr; + assign iempty = (rptr == wptr) ? 1'b1 : 1'b0; + + assign tmp2 = (1 << AWIDTH) -3; + assign ifull = ( tmp >= tmp2 ) ? 1'b1 : 1'b0; + + // rdclk flags + always@(posedge rclk or negedge aclr) + if (~aclr) + begin + rempty <= #1 1'b1; + rfull <= #1 1'b0; + rd_empty <= #1 1'b1; + rd_full <= #1 1'b0; + end + else + begin + rempty <= #1 iempty; + rfull <= #1 ifull; + rd_empty <= #1 rempty; + rd_full <= #1 rfull; + end + + // wrclk flags + always@(posedge wclk or negedge aclr) + if (~aclr) + begin + wempty <= #1 1'b1; + wfull <= #1 1'b0; + wr_empty <= #1 1'b1; + wr_full <= #1 1'b0; + end + else + begin + wempty <= #1 iempty; + wfull <= #1 ifull; + wr_empty <= #1 wempty; + wr_full <= #1 wfull; + end + + // hookup generic dual ported memory + generic_dpram #(AWIDTH, DWIDTH) fifo_dc_mem( + .rclk(rclk), + .rrst(1'b0), + .rce(1'b1), + .oe(1'b1), + .raddr(rptr), + .do(q), + .wclk(wclk), + .wrst(1'b0), + .wce(1'b1), + .we(wreq), + .waddr(wptr), + .di(d) + ); + +endmodule Index: tags/rel_1/rtl/verilog/vga_tgen.v =================================================================== --- tags/rel_1/rtl/verilog/vga_tgen.v (nonexistent) +++ tags/rel_1/rtl/verilog/vga_tgen.v (revision 42) @@ -0,0 +1,130 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant VGA/LCD Core; Timing Generator //// +//// Horizontal and Vertical Timing Generator //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_tgen.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $ +// +// $Date: 2002-01-28 03:47:16 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + +`include "timescale.v" + +module vga_tgen(clk, rst, HSyncL, Thsync, Thgdel, Thgate, Thlen, VSyncL, Tvsync, Tvgdel, Tvgate, Tvlen, CSyncL, BlankL, + eol, eof, gate, Hsync, Vsync, Csync, Blank); + // inputs & outputs + input clk; + input rst; + // horizontal timing settings inputs + input HSyncL; // horizontal sync pulse polarization level (pos/neg) + input [ 7:0] Thsync; // horizontal sync pule width (in pixels) + input [ 7:0] Thgdel; // horizontal gate delay + input [15:0] Thgate; // horizontal gate (number of visible pixels per line) + input [15:0] Thlen; // horizontal length (number of pixels per line) + // vertical timing settings inputs + input VSyncL; // vertical sync pulse polarization level (pos/neg) + input [ 7:0] Tvsync; // vertical sync pule width (in pixels) + input [ 7:0] Tvgdel; // vertical gate delay + input [15:0] Tvgate; // vertical gate (number of visible pixels per line) + input [15:0] Tvlen; // vertical length (number of pixels per line) + + input CSyncL; // composite sync level (pos/neg) + input BlankL; // blanking level + + // outputs + output eol; // end of line + output eof; // end of frame + output gate; // vertical AND horizontal gate (logical AND function) + + output Hsync; // horizontal sync pulse + output Vsync; // vertical sync pulse + output Csync; // composite sync + output Blank; // blank signal + + // + // variable declarations + // + wire Hgate, Vgate; + wire Hdone; + wire iHsync, iVsync; + + // + // module body + // + + // hookup horizontal timing generator + vga_vtim hor_gen( + .clk(clk), + .ena(1'b1), + .rst(rst), + .Tsync(Thsync), + .Tgdel(Thgdel), + .Tgate(Thgate), + .Tlen(Thlen), + .Sync(iHsync), + .Gate(Hgate), + .Done(Hdone)); + + + // hookup vertical timing generator + vga_vtim ver_gen( + .clk(clk), + .ena(Hdone), + .rst(rst), + .Tsync(Tvsync), + .Tgdel(Tvgdel), + .Tgate(Tvgate), + .Tlen(Tvlen), + .Sync(iVsync), + .Gate(Vgate), + .Done(eof)); + + // assign outputs + assign eol = Hdone; + assign gate = Hgate & Vgate; + + assign Hsync = iHsync ^ HSyncL; + assign Vsync = iVsync ^ VSyncL; + assign Csync = (iHsync | iVsync) ^ CSyncL; + assign Blank = !(gate ^ BlankL); +endmodule Index: tags/rel_1/rtl/verilog/generic_spram.v =================================================================== --- tags/rel_1/rtl/verilog/generic_spram.v (nonexistent) +++ tags/rel_1/rtl/verilog/generic_spram.v (revision 42) @@ -0,0 +1,405 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// +//// //// +//// Description //// +//// This block is a wrapper with common single-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides a behavioral model of generic //// +//// single-port synchronous RAM. //// +//// It also contains a synthesizeable model for FPGAs. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Single-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage Single-Port Sync RAM //// +//// - Virtual Silicon Single-Port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Generic FPGA (VENDOR_FPGA) //// +//// Tested RAMs: Altera, Xilinx //// +//// Synthesis tools: LeonardoSpectrum, Synplicity //// +//// - Xilinx (VENDOR_XILINX) //// +//// - Altera (VENDOR_ALTERA) //// +//// //// +//// To Do: //// +//// - fix avant! two-port ram //// +//// - add additional RAMs //// +//// //// +//// Author(s): //// +//// - Richard Herveille, richard@asics.ws //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +`include "timescale.v" + +//`define VENDOR_XILINX +//`define VENDOR_ALTERA +//`define VENDOR_FPGA + +module generic_spram( + // Generic synchronous single-port RAM interface + clk, rst, ce, we, oe, addr, di, do +); + + // + // Default address and data buses width + // + parameter aw = 6; //number of address-bits + parameter dw = 8; //number of data-bits + + // + // Generic synchronous single-port RAM interface + // + input clk; // Clock, rising edge + input rst; // Reset, active high + input ce; // Chip enable input, active high + input we; // Write enable input, active high + input oe; // Output enable input, active high + input [aw-1:0] addr; // address bus inputs + input [dw-1:0] di; // input data bus + output [dw-1:0] do; // output data bus + + // + // Module body + // + +`ifdef VENDOR_FPGA + // + // Instantiation synthesizeable FPGA memory + // + // This code has been tested using LeonardoSpectrum and Synplicity. + // The code correctly instantiates Altera EABs and Xilinx BlockRAMs. + // + reg [dw-1 :0] mem [(1< '0'); -- initial data after reset + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); + end component ud_cnt; + + -- run-once down-counter + component ro_cnt is + generic(SIZE : natural := 8); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + D : in unsigned(SIZE -1 downto 0); -- load counter value + Q : out unsigned(SIZE -1 downto 0); -- current counter value + + ID : in unsigned(SIZE -1 downto 0) := (others => '0') -- initial data after reset + ); + end component ro_cnt; +end package count; + +-- +-- general purpose counter +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ud_cnt is + generic( + SIZE : natural := 8 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + D : in unsigned(SIZE -1 downto 0); -- load counter value + Q : out unsigned(SIZE -1 downto 0); -- current counter value + + resD : in unsigned(SIZE -1 downto 0) := (others => '0'); -- initial data after reset + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); +end entity ud_cnt; + +architecture structural of ud_cnt is + signal Qi : unsigned(SIZE -1 downto 0); + signal val : unsigned(SIZE downto 0); +begin + val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); + + regs: process(clk, nReset, resD) + begin + if (nReset = '0') then + Qi <= resD; + elsif (clk'event and clk = '1') then + if (rst = '1') then + Qi <= resD; + else + if (nld = '0') then + Qi <= D; + elsif (cnt_en = '1') then + Qi <= val(SIZE -1 downto 0); + end if; + end if; + end if; + end process regs; + + -- assign outputs + Q <= Qi; + rco <= val(SIZE); +end architecture structural; + + +-- +-- run-once down-counter, counts D+1 cycles before generating 'DONE' +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ro_cnt is + generic(SIZE : natural := 8); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + D : in unsigned(SIZE -1 downto 0); -- load counter value + Q : out unsigned(SIZE -1 downto 0); -- current counter value + + ID : in unsigned(SIZE -1 downto 0) := (others => '0') -- initial data after reset + ); +end entity ro_cnt; + +architecture structural of ro_cnt is + component ud_cnt is + generic( + SIZE : natural := 8 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + D : in unsigned(SIZE -1 downto 0); -- load counter value + Q : out unsigned(SIZE -1 downto 0); -- current counter value + + resD : in unsigned(SIZE -1 downto 0) := (others => '0'); -- initial data after reset + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); + end component ud_cnt; + + signal rci, rco, nld : std_logic; +begin + gen_ctrl: process(clk, nReset) + begin + if (nReset = '0') then + rci <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + rci <= '0'; + elsif (cnt_en = '1' ) then + rci <= (go or rci) and not rco; + end if; + end if; + end process; + + nld <= not go; + + -- hookup counter + cnt : ud_cnt + generic map (SIZE => SIZE) + port map (clk => clk, nReset => nReset, rst => rst, cnt_en => cnt_en, nld => nld, D => D, Q => Q, + resD => ID, rci => rci, rco => rco); + + done <= rco; +end architecture structural; + Index: tags/rel_1/rtl/vhdl/vtim.vhd =================================================================== --- tags/rel_1/rtl/vhdl/vtim.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/vtim.vhd (revision 42) @@ -0,0 +1,107 @@ +-- +-- File vtim.vhd, Video Timing Generator +-- Project: VGA +-- Author : Richard Herveille +-- rev.: 0.1 April 13th, 2001 +-- rev.: 0.2 June 23nd, 2001. Removed unused "rst_strb" signal. +-- rev.: 0.3 June 29th, 2001. Changed 'gen_go' process to use clock-enable signal. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +library count; +use count.count.all; + +entity vtim is + port( + clk : in std_logic; -- master clock + ena : in std_logic; -- count enable + rst : in std_logic; -- synchronous active high reset + + Tsync : in unsigned(7 downto 0); -- sync duration + Tgdel : in unsigned(7 downto 0); -- gate delay + Tgate : in unsigned(15 downto 0); -- gate length + Tlen : in unsigned(15 downto 0); -- line time / frame time + + Sync : out std_logic; -- synchronization pulse + Gate : out std_logic; -- gate + Done : out std_logic -- done with line/frame + ); +end entity vtim; + +architecture structural of vtim is + signal Dsync, Dgdel, Dgate, Dlen : std_logic; + signal go, drst : std_logic; +begin + -- generate go signal + gen_go: process(clk) + begin + if (clk'event and clk = '1') then + if (rst = '1') then + go <= '0'; + drst <= '1'; + elsif (ena = '1') then + go <= Dlen or (not rst and drst); + drst <= rst; + end if; + end if; + end process gen_go; +-- go <= Dlen or (not rst and drst); does not work => horizontal Dlen counter does not reload + + -- hookup sync counter + sync_cnt : ro_cnt generic map (SIZE => 8) + port map (clk => clk, rst => rst, cnt_en => ena, go => go, D => Tsync, iD => Tsync, done => Dsync); + + -- hookup gate delay counter + gdel_cnt : ro_cnt generic map (SIZE => 8) + port map (clk => clk, rst => rst, cnt_en => ena, go => Dsync, D => Tgdel, iD => Tgdel, done => Dgdel); + + -- hookup gate counter + gate_cnt : ro_cnt generic map (SIZE => 16) + port map (clk => clk, rst => rst, cnt_en => ena, go => Dgdel, D => Tgate, iD => Tgate, done => Dgate); + + -- hookup gate counter + len_cnt : ro_cnt generic map (SIZE => 16) + port map (clk => clk, rst => rst, cnt_en => ena, go => go, D => Tlen, iD => Tlen, done => Dlen); + + -- generate output signals + gen_sync: block + signal iSync : std_logic; + begin + process(clk) + begin + if (clk'event and clk = '1') then + if (rst = '1') then + iSync <= '0'; + else + iSync <= (go or iSync) and not Dsync; + end if; + end if; + end process; + Sync <= iSync; + end block gen_sync; + + gen_gate: block + signal iGate : std_logic; + begin + process(clk) + begin + if (clk'event and clk = '1') then + if (rst = '1') then + iGate <= '0'; + else + iGate <= (Dgdel or iGate) and not Dgate; + end if; + end if; + end process; + + Gate <= iGate; + end block gen_gate; + + Done <= Dlen; +end architecture structural; + + + Index: tags/rel_1/rtl/vhdl/dpm.vhd =================================================================== --- tags/rel_1/rtl/vhdl/dpm.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/dpm.vhd (revision 42) @@ -0,0 +1,94 @@ +-- +-- File dpm.vhd (dual ported memory) +-- Author : Richard Herveille +-- rev. 0.1 May 17th, 2001 : Initial release +-- +-- fifo_dc uses this entity to implement the dual ported RAM of the fifo. +-- Change this file to implement target specific RAM blocks. +-- +-- rev. 0.2 June 29th, 2001. Changed "std_logic_vector(23 downto 0)" into "std_logic_vector(DWIDTH -1 downto 0)" for 'dout'. +-- Removed rreq input. Removed obsolete "dout" signal +-- The design now correctly maps to Altera-EABs and Xilinx-BlockRAMs + +-- +-- dual ported memory, wrapper for target specific RAM blocks +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity dual_ported_memory is + generic( + AWIDTH : natural := 8; + DWIDTH : natural := 24 + ); + port( + rclk : in std_logic; -- read clock input + wclk : in std_logic; -- write clock input + + D : in std_logic_vector(DWIDTH -1 downto 0); -- Data input + waddr : in unsigned(AWIDTH -1 downto 0); -- write clock address input + wreq : in std_logic; -- write request + + Q : out std_logic_vector(DWIDTH -1 downto 0); -- Data output + raddr : in unsigned(AWIDTH -1 downto 0) -- read clock address input + ); +end entity dual_ported_memory; + +architecture structural of dual_ported_memory is + -- example target specific RAM block, 256entries x 24bit + component VSR256X24M2 is + port( + RCK : in std_logic; -- read clock + REN : in std_logic; -- read enable, active low + RADR : in std_logic_vector(7 downto 0); -- read address + + WCK : in std_logic; -- write clock + WEN : in std_logic; -- write enable, active low + WADR : in std_logic_vector(7 downto 0); -- write address + + DI : in std_logic_vector(23 downto 0); -- data input, (synchronous to write clock) + DOUT : out std_logic_vector(23 downto 0) -- data output (asynchronous) + ); + end component VSR256X24M2; +-- signal nrreq, nwreq : std_logic; + + -- generate memory for generic description + type mem_type is array (2**AWIDTH -1 downto 0) of std_logic_vector(DWIDTH -1 downto 0); + signal mem : mem_type; + +begin + -- + -- Change the next section(s) for target specific RAM blocks. + -- The functionality as described below must be maintained! Some target specific RAM blocks have an asychronous output. + -- Insert registers at the output if necessary + -- + -- generic dual ported memory description + -- + write_mem: process(wclk) + begin + if (wclk'event and wclk = '1') then + if (wreq = '1') then + mem(conv_integer(waddr)) <= D; -- store D in memory array + end if; + end if; + end process write_mem; + + read_mem: process(rclk) + begin + if (rclk'event and rclk = '1') then + Q <= mem(conv_integer(raddr)); + end if; + end process read_mem; + + -- + -- target specific example + -- +-- nrreq <= not rreq; +-- nwreq <= not wreq; +-- u1: VSR256X24M2 port map(RCK => rclk, REN => nrreq, RADR => std_logic_vector(raddr), +-- WCK => wclk, WEN => nwreq, WADR => std_logic_vector(waddr), +-- DI => D, DOUT => Q); + +end architecture structural; Index: tags/rel_1/rtl/vhdl/vga_and_clut_tstbench.vhd =================================================================== --- tags/rel_1/rtl/vhdl/vga_and_clut_tstbench.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/vga_and_clut_tstbench.vhd (revision 42) @@ -0,0 +1,415 @@ +-- +-- file: vga_and_clut_tstbench.vhd +-- project: VGA/LCD controller + Color Lookup Table +-- author: Richard Herveille +-- +-- Testbench for VGA controller + CLUT combination +-- +-- rev 1.0 July 4th, 2001. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity tst_bench is +end entity tst_bench; + +architecture test of tst_bench is + -- + -- component declarations + -- + + component vga_and_clut is + port( + CLK_I : in std_logic; -- wishbone clock input + RST_I : in std_logic; -- synchronous active high reset + NRESET : in std_logic := '1'; -- asynchronous active low reset + INTA_O : out std_logic; -- interrupt request output + + -- slave signals + ADR_I : in unsigned(10 downto 2); -- addressbus input (only 32bit databus accesses supported) + SDAT_I : in std_logic_vector(31 downto 0); -- Slave databus output + SDAT_O : out std_logic_vector(31 downto 0); -- Slave databus input + SEL_I : in std_logic_vector(3 downto 0); -- byte select inputs + WE_I : in std_logic; -- write enabel input + VGA_STB_I : in std_logic; -- vga strobe/select input + CLUT_STB_I : in std_logic; -- color-lookup-table strobe/select input + CYC_I : in std_logic; -- valid bus cycle input + ACK_O : out std_logic; -- bus cycle acknowledge output + ERR_O : out std_logic; -- bus cycle error output + + -- master signals + ADR_O : out unsigned(31 downto 2); -- addressbus output + MDAT_I : in std_logic_vector(31 downto 0); -- Master databus input + SEL_O : out std_logic_vector(3 downto 0); -- byte select outputs + WE_O : out std_logic; -- write enable output + STB_O : out std_logic; -- strobe output + CYC_O : out std_logic; -- valid bus cycle output + CAB_O : out std_logic; -- continuos address burst output + ACK_I : in std_logic; -- bus cycle acknowledge input + ERR_I : in std_logic; -- bus cycle error input + + -- VGA signals + PCLK : in std_logic; -- pixel clock + HSYNC : out std_logic; -- horizontal sync + VSYNC : out std_logic; -- vertical sync + CSYNC : out std_logic; -- composite sync + BLANK : out std_logic; -- blanking signal + R,G,B : out std_logic_vector(7 downto 0) -- RGB color signals + ); + end component vga_and_clut; + + component wb_host is + generic( + RST_LVL : std_logic := '0' -- reset level + ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + + cyc_o : out std_logic; + stb_o : out std_logic; + we_o : out std_logic; + adr_o : out std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + dat_i : in std_logic_vector(31 downto 0); + sel_o : out std_logic_vector(3 downto 0); + ack_i : in std_logic; + err_i : in std_logic + ); + end component wb_host; + + component vid_mem is + generic( + ACK_DELAY : natural := 2 + ); + port( + clk_i : in std_logic; + adr_i : in unsigned (15 downto 0); + cyc_i : in std_logic; + stb_i : in std_logic; + dat_o : out std_logic_vector(31 downto 0); + ack_o : out std_logic + ); + end component vid_mem; + + -- + -- signal declarations + -- + + -- clock & reset + signal clk, vga_clk : std_logic := '0'; + signal rst : std_logic := '1'; + signal init : std_logic := '0'; + + -- wishbone host + signal h_cyc_o, h_stb_o, h_we_o : std_logic; + signal h_adr_o : unsigned(31 downto 0); + signal h_dat_o, h_dat_i : std_logic_vector(31 downto 0); + signal h_sel_o : std_logic_vector(3 downto 0); + signal h_ack_i, h_err_i : std_logic; + + -- vga master + signal vga_adr_o : unsigned(31 downto 2); + signal vga_dat_i : std_logic_vector(31 downto 0); + signal vga_stb_o, vga_cyc_o, vga_ack_i : std_logic; + signal vga_sel_o : std_logic_vector(3 downto 0); + signal vga_we_o, vga_err_i : std_logic; + + -- vga + signal r, g, b : std_logic_vector(7 downto 0); + signal hsync, vsync, csync, blank : std_logic; +begin + + -- generate clocks + clk_block: block + begin + process(clk) + begin + clk <= not clk after 2.5 ns; -- 200MHz wishbone clock + end process; + + process(vga_clk) + begin + vga_clk <= not vga_clk after 12.5 ns; -- 40MHz vga clock + end process; + end block clk_block; + + -- generate reset signal + gen_rst: process(init, rst) + begin + if (init = '0') then + rst <= '0' after 100 ns; + init <= '1'; + end if; + end process gen_rst; + + -- + -- hookup vga + clut core + -- + u1: vga_and_clut port map (CLK_I => clk, RST_I => RST, ADR_I => h_adr_o(10 downto 2), + SDAT_I => h_dat_o, SDAT_O => h_dat_i, SEL_I => h_sel_o, WE_I => h_we_o, VGA_STB_I => h_adr_o(31), + CLUT_STB_I => h_adr_o(30), CYC_I => h_cyc_o, ACK_O => h_ack_i, ERR_O => h_err_i, + ADR_O => vga_adr_o, MDAT_I => vga_dat_i, SEL_O => vga_sel_o, WE_O => vga_we_o, STB_O => vga_stb_o, + CYC_O => vga_cyc_o, ACK_I => vga_ack_i, ERR_I => vga_err_i, + PCLK => vga_clk, HSYNC => hsync, VSYNC => vsync, CSYNC => csync, BLANK => blank, R => r, G => g, B => b); + + -- + -- hookup wishbone host + -- + u2: wb_host + generic map (RST_LVL => '1') + port map (clk_i => clk, rst_i => rst, cyc_o => h_cyc_o, stb_o => h_stb_o, we_o => h_we_o, unsigned(adr_o) => h_adr_o, + dat_o => h_dat_o, dat_i => h_dat_i, sel_o => h_sel_o, ack_i => h_ack_i, err_i => h_err_i); + + u3: vid_mem + generic map (ACK_DELAY => 0) + port map (clk_i => clk, adr_i => vga_adr_o(17 downto 2), cyc_i => vga_cyc_o, + stb_i => vga_stb_o, dat_o => vga_dat_i, ack_o => vga_ack_i); +end architecture test; + +-- +------------------------------------ +-- Wishbone host behavioral model -- +------------------------------------ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +library std; +use std.standard.all; + +entity wb_host is + generic( + RST_LVL : std_logic := '1' -- reset level + ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + + cyc_o : out std_logic; + stb_o : out std_logic; + we_o : out std_logic; + adr_o : out std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + dat_i : in std_logic_vector(31 downto 0); + sel_o : out std_logic_vector(3 downto 0); + ack_i : in std_logic; + err_i : in std_logic + ); +end entity wb_host; + +architecture behavioral of wb_host is + -- type declarations + type vector_type is + record + adr : std_logic_vector(31 downto 0); -- wishbone address output + we : std_logic; -- wishbone write enable output + dat : std_logic_vector(31 downto 0); -- wishbone data output (write) or input compare value (read) + sel : std_logic_vector(3 downto 0); -- wishbone byte select output + stop : std_logic; -- last field, stop wishbone activities + end record; + + type vector_list is array(0 to 38) of vector_type; + + type states is (chk_stop, gen_cycle); + + -- signal declarations + signal state : states; + signal cnt : natural := 0; + signal cyc, stb : std_logic; + + shared variable vectors : vector_list := + ( + -- fill clut (adr(30) = '1') + (x"40000000",'1',x"00123456","1111",'0'), --0 + (x"40000004",'1',x"00789abc","1111",'0'), + (x"40000008",'1',x"00def010","1111",'0'), + (x"4000000C",'1',x"00010203","1111",'0'), + (x"40000010",'1',x"00040506","1111",'0'), + (x"40000014",'1',x"00070809","1111",'0'), + (x"40000018",'1',x"000a0b0c","1111",'0'), + (x"4000001C",'1',x"00102030","1111",'0'), + (x"40000020",'1',x"00405060","1111",'0'), + (x"40000024",'1',x"00708090","1111",'0'), + (x"40000028",'1',x"00a0b0c0","1111",'0'), + (x"4000002C",'1',x"00112233","1111",'0'), + (x"40000030",'1',x"00445566","1111",'0'), + (x"40000034",'1',x"00778899","1111",'0'), + (x"40000038",'1',x"00aabbcc","1111",'0'), + (x"4000003C",'1',x"00ddeeff","1111",'0'), + + -- verify data written + (x"40000000",'0',x"00123456","1111",'0'), --16 + (x"40000004",'0',x"00789abc","1111",'0'), + (x"40000008",'0',x"00def010","1111",'0'), + (x"4000000C",'0',x"00010203","1111",'0'), + (x"40000010",'0',x"00040506","1111",'0'), + (x"40000014",'0',x"00070809","1111",'0'), + (x"40000018",'0',x"000a0b0c","1111",'0'), + (x"4000001C",'0',x"00102030","1111",'0'), + (x"40000020",'0',x"00405060","1111",'0'), + (x"40000024",'0',x"00708090","1111",'0'), + (x"40000028",'0',x"00a0b0c0","1111",'0'), + (x"4000002C",'0',x"00112233","1111",'0'), + (x"40000030",'0',x"00445566","1111",'0'), + (x"40000034",'0',x"00778899","1111",'0'), + (x"40000038",'0',x"00aabbcc","1111",'0'), + (x"4000003C",'0',x"00ddeeff","1111",'0'), + + -- program vga controller + (x"80000008",'1',x"04090018","1111",'0'), --32 program horizontal timing register (25 visible pixels per line) + (x"8000000c",'1',x"05010003","1111",'0'), -- program vertical timing register (4 visible lines per frame) + (x"80000010",'1',x"00320016","1111",'0'), -- program horizontal/vertical length register (50x50 pixels) + (x"80000014",'1',x"10000000","1111",'0'), -- program video base address 0 register (sdram) + (x"8000001c",'1',x"10200000","1111",'0'), -- program color lookup table (sram) + (x"80000000",'1',x"00000901","1111",'0'), -- program control register (enable video system) + + -- end list + (x"00000000",'0',x"00000000","1111",'1') --38 stop testbench + ); + +begin + process(clk_i, cnt, ack_i, err_i) + variable nxt_state : states; + variable icnt : natural; + begin + + nxt_state := state; + icnt := cnt; + + case state is + when chk_stop => + cyc <= '0'; -- no valid bus-cycle + stb <= '0'; -- disable strobe output + if (vectors(cnt).stop = '0') then + nxt_state := gen_cycle; + cyc <= '1'; + stb <= '1'; + end if; + + when gen_cycle => + cyc <= '1'; + stb <= '1'; + if (ack_i = '1') or (err_i = '1') then + nxt_state := chk_stop; + cyc <= '0'; + stb <= '0'; + + icnt := cnt +1; + + -- + -- check assertion of ERR_I + -- + if (err_i = '1') then + if (clk_i'event and clk_i = '1') then -- display warning only at rising edge of clock +-- report ("ERR_I asserted at vectorno. ")& cnt +-- severity warning; + report ("ERR_I asserted at vectorno. ") severity error; + end if; + end if; + + -- + -- compare DAT_I with expected data during ACK_I assertion + -- + if (vectors(cnt).we = '0') then + if (vectors(cnt).dat /= dat_i) then + if (clk_i'event and clk_i = '1') then -- display warning only at rising edge of clock +-- report ("DAT_I not equal to compare value. Expected ")& vectors(cnt).dat_i & (" received ") & dat_i; +-- severity warning; + report ("DAT_I not equal to compare value") severity error; + end if; + end if; + end if; + + end if; + end case; + + + if (clk_i'event and clk_i = '1') then + if (rst_i = RST_LVL) then + state <= chk_stop; + cyc_o <= '0'; + stb_o <= '0'; + adr_o <= (others => 'X'); + dat_o <= (others => 'X'); + we_o <= 'X'; + sel_o <= (others => 'X'); + else + state <= nxt_state; + cyc_o <= cyc; + stb_o <= stb; + + if (cyc = '1') then + adr_o <= vectors(cnt).adr; + dat_o <= vectors(cnt).dat; + we_o <= vectors(cnt).we; + sel_o <= vectors(cnt).sel; + else + adr_o <= (others => 'X'); + dat_o <= (others => 'X'); + we_o <= 'X'; + sel_o <= (others => 'X'); + end if; + end if; + + cnt <= icnt; + end if; + end process; +end architecture behavioral; + +-- +------------------------ +-- video memory (ROM) -- +------------------------ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity vid_mem is + generic( + ACK_DELAY : natural := 2 + ); + port( + clk_i : in std_logic; + adr_i : in unsigned (15 downto 0); + cyc_i : in std_logic; + stb_i : in std_logic; + dat_o : out std_logic_vector(31 downto 0); + ack_o : out std_logic + ); +end entity vid_mem; + +architecture behavioral of vid_mem is + signal cnt : unsigned(2 downto 0) := conv_unsigned(ACK_DELAY, 3); + signal my_ack : std_logic; +begin + with adr_i(15 downto 0) select + dat_o <= x"01020304" when x"0000", + x"05060708" when x"0001", + x"090a0b0c" when x"0002", + x"0d0e0f00" when x"0003", + x"a5a5a5a5" when others; + + gen_ack: process(clk_i) + begin + if (clk_i'event and clk_i = '1') then + if (my_ack = '1') then + cnt <= conv_unsigned(ACK_DELAY, 3); + elsif ((cyc_i = '1') and (stb_i = '1')) then + cnt <= cnt -1; + end if; + end if; + end process gen_ack; + + my_ack <= '1' when ((cyc_i = '1') and (stb_i = '1') and (cnt = 0)) else '0'; + ack_o <= my_ack; +end architecture behavioral; + + + + + + Index: tags/rel_1/rtl/vhdl/colproc.vhd =================================================================== --- tags/rel_1/rtl/vhdl/colproc.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/colproc.vhd (revision 42) @@ -0,0 +1,320 @@ +-- +-- File colproc.vhd, Color Processor +-- Project: VGA +-- Author : Richard Herveille. Ideas and thoughts: Sherif Taher Eid +-- rev.: 0.1 May 1st, 2001 +-- rev.: 0.2 June 23rd, 2001. Removed unused "prev_state" references from statemachine. Removed unused "dWB_Di" signal. +-- rev.: 1.0 July 6th, 2001. Fixed a bug where the core did not repond correctly to a delayed clut_ack signal in 8bpp_pseudo_color mode. +-- rev.: 1.1 August 2nd, 2001. Changed 24bpp section in output-decoder. Smaller/faster synthesis results. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity colproc is + port( + clk : in std_logic; -- master clock + ctrl_Ven : in std_logic; -- Video Enable + + pixel_buffer_Di, -- Pixel Buffer data input + WB_Di : in std_logic_vector(31 downto 0); -- WISHBONE data input + + ColorDepth : in std_logic_vector(1 downto 0); -- color depth (8bpp, 16bpp, 24bpp) + PseudoColor : in std_logic; -- pseudo color enabled (only for 8bpp color depth) + + pixel_buffer_empty : in std_logic; + pixel_buffer_rreq : buffer std_logic; -- pixel buffer read request + + RGB_fifo_full : in std_logic; + RGB_fifo_wreq : out std_logic; + R,G,B : out std_logic_vector(7 downto 0); -- pixel color (to RGB fifo) + + clut_req : out std_logic; -- CLUT access request + clut_offs: out unsigned(7 downto 0); -- offset into color lookup table + clut_ack : in std_logic -- CLUT data acknowledge + ); +end entity colproc; + +architecture structural of colproc is + signal DataBuffer : std_logic_vector(31 downto 0); + signal colcnt : unsigned(1 downto 0); + signal RGBbuf_wreq : std_logic; +begin + -- store word from pixelbuffer / wishbone input + process(clk) + begin + if (clk'event and clk = '1') then + if (pixel_buffer_rreq = '1') then + DataBuffer <= pixel_buffer_Di; + end if; + end if; + end process; + + -- extract color information from data buffer + statemachine: block + type states is (idle, fill_buf, bw_8bpp, col_8bpp, col_16bpp_a, col_16bpp_b, col_24bpp); + signal c_state : states; + + signal Ra, Ga, Ba : std_logic_vector(7 downto 0); + begin + gen_nxt_state: process(clk, c_state, pixel_buffer_empty, ColorDepth, PseudoColor, RGB_fifo_full, colcnt, clut_ack) + variable nxt_state : states; + begin + + -- initial value + nxt_state := c_state; + + case c_state is + -- idle state + when idle => + if (pixel_buffer_empty = '0') then + nxt_state := fill_buf; + end if; + + when fill_buf => + case ColorDepth is + when "00" => + if (PseudoColor = '1') then + nxt_state := col_8bpp; + else + nxt_state := bw_8bpp; + end if; + + when "01" => + nxt_state := col_16bpp_a; + + when others => + nxt_state := col_24bpp; + + end case; + + -- + -- 8 bits per pixel + -- + when bw_8bpp => + if ((RGB_fifo_full = '0') and (colcnt = 0)) then + nxt_state := idle; + end if; + + when col_8bpp => + if ((RGB_fifo_full = '0') and (colcnt = 0)) then + if (clut_ack = '1') then + nxt_state := idle; + end if; + end if; + + -- + -- 16 bits per pixel + -- + when col_16bpp_a => + if (RGB_fifo_full = '0') then + nxt_state := col_16bpp_b; + end if; + + when col_16bpp_b => + if (RGB_fifo_full = '0') then + nxt_state := idle; + end if; + + -- + -- 24 bits per pixel + -- + when col_24bpp => + if (RGB_fifo_full = '0') then + if (colcnt = 1) then + nxt_state := col_24bpp; -- stay in current state + else + nxt_state := idle; + end if; + end if; + end case; + + if (clk'event and clk = '1') then + if (ctrl_Ven = '0') then + c_state <= idle; + else + c_state <= nxt_state; + end if; + end if; + end process gen_nxt_state; + + -- + -- output decoder + -- + gen_odec: process(clk, c_state, pixel_buffer_empty, colcnt, DataBuffer, RGB_fifo_full, clut_ack, WB_Di, Ba, Ga, Ra) + variable clut_acc : std_logic; + variable pixelbuf_rreq : std_logic; + variable iR, iG, iB, iRa, iGa, iBa : std_logic_vector(7 downto 0); + begin + -- initial values + pixelbuf_rreq := '0'; + RGBbuf_wreq <= '0'; + clut_acc := '0'; + + iR := (others => '0'); + iG := (others => '0'); + iB := (others => '0'); + iRa := (others => '0'); + iGa := (others => '0'); + iBa := (others => '0'); + + case c_state is + when idle => + if (pixel_buffer_empty = '0') then + pixelbuf_rreq := '1'; + end if; + + -- + -- 8 bits per pixel + -- + when bw_8bpp => + if (RGB_fifo_full = '0') then + RGBbuf_wreq <= '1'; + end if; + + case colcnt is + when "11" => + iR := DataBuffer(31 downto 24); + iG := iR; + iB := iR; + + when "10" => + iR := DataBuffer(23 downto 16); + iG := iR; + iB := iR; + + when "01" => + iR := DataBuffer(15 downto 8); + iG := iR; + iB := iR; + + when others => + iR := DataBuffer(7 downto 0); + iG := iR; + iB := iR; + end case; + + when col_8bpp => + if ((RGB_fifo_full = '0') and (clut_ack = '1')) then + RGBbuf_wreq <= '1'; + end if; + + iR := WB_Di(23 downto 16); + iG := WB_Di(15 downto 8); + iB := WB_Di( 7 downto 0); + + clut_acc := not RGB_fifo_full; + + if ((colcnt = 0) and (clut_ack = '1')) then + clut_acc := '0'; + end if; + + -- + -- 16 bits per pixel + -- + when col_16bpp_a => + if (RGB_fifo_full = '0') then + RGBbuf_wreq <= '1'; + end if; + iR(7 downto 3) := DataBuffer(31 downto 27); + iG(7 downto 2) := DataBuffer(26 downto 21); + iB(7 downto 3) := DataBuffer(20 downto 16); + + when col_16bpp_b => + if (RGB_fifo_full = '0') then + RGBbuf_wreq <= '1'; + end if; + iR(7 downto 3) := DataBuffer(15 downto 11); + iG(7 downto 2) := DataBuffer(10 downto 5); + iB(7 downto 3) := DataBuffer( 4 downto 0); + + -- + -- 24 bits per pixel + -- + when col_24bpp => + if (RGB_fifo_full = '0') then + RGBbuf_wreq <= '1'; + end if; + + case colcnt is + when "11" => + iR := DataBuffer(31 downto 24); + iG := DataBuffer(23 downto 16); + iB := DataBuffer(15 downto 8); + iRa := DataBuffer( 7 downto 0); + + when "10" => + iR := Ra; + iG := DataBuffer(31 downto 24); + iB := DataBuffer(23 downto 16); + iRa := DataBuffer(15 downto 8); + iGa := DataBuffer( 7 downto 0); + + when "01" => + iR := Ra; + iG := Ga; + iB := DataBuffer(31 downto 24); + iRa := DataBuffer(23 downto 16); + iGa := DataBuffer(15 downto 8); + iBa := DataBuffer( 7 downto 0); + + when others => + iR := Ra; + iG := Ga; + iB := Ba; + end case; + + when others => + null; + + end case; + + if (clk'event and clk = '1') then + R <= iR; + G <= iG; + B <= iB; + + if (RGBbuf_wreq = '1') then + Ra <= iRa; + Ba <= iBa; + Ga <= iGa; + end if; + + if (ctrl_Ven = '0') then + pixel_buffer_rreq <= '0'; + RGB_fifo_wreq <= '0'; + clut_req <= '0'; + else + pixel_buffer_rreq <= pixelbuf_rreq; + RGB_fifo_wreq <= RGBbuf_wreq; + clut_req <= clut_acc; + end if; + end if; + end process gen_odec; + + -- assign clut offset + with colcnt select + clut_offs <= unsigned(DataBuffer(31 downto 24)) when "11", + unsigned(DataBuffer(23 downto 16)) when "10", + unsigned(DataBuffer(15 downto 8)) when "01", + unsigned(DataBuffer( 7 downto 0)) when others; + + end block statemachine; + + + -- color counter + gen_colcnt: process(clk) + begin + if (clk'event and clk = '1') then + if (ctrl_Ven = '0') then + colcnt <= (others => '1'); + elsif (RGBbuf_wreq = '1') then + colcnt <= colcnt -1; + end if; + end if; + end process gen_colcnt; + +end architecture structural; + + + Index: tags/rel_1/rtl/vhdl/wb_slave.vhd =================================================================== --- tags/rel_1/rtl/vhdl/wb_slave.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/wb_slave.vhd (revision 42) @@ -0,0 +1,185 @@ +-- +-- file: wb_slave.vhd +-- project: VGA/LCD controller +-- author: Richard Herveille +-- rev 1.0 May 10th, 2001 +-- rev 1.1 June 3rd, 2001. Changed WISHBONE ADR_I. Addresses are defined as byte-oriented, instead of databus independent. +-- rev 1.2 July 15th, 2001. Added CLUT bank switching. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity wb_slave is + port ( + CLK_I : in std_logic; + RST_I : in std_logic; + NRESET : in std_logic; + ADR_I : in unsigned(4 downto 2); + DAT_I : in std_logic_vector(31 downto 0); + DAT_O : out std_logic_vector(31 downto 0); + SEL_I : in std_logic_vector(3 downto 0); + WE_I : in std_logic; + STB_I : in std_logic; + CYC_I : in std_logic; + ACK_O : out std_logic; + ERR_O : out std_logic; + INTA_O : out std_logic; + + -- control register settings + BL : out std_logic; -- blanking level + CSL : out std_logic; -- composite sync level + VSL : out std_logic; -- vsync level + HSL : out std_logic; -- hsync level + PC : out std_logic; -- pseudo color + CD : out std_logic_vector(1 downto 0); -- color depth + VBL : out std_logic_vector(1 downto 0); -- burst length + CBSW : out std_logic; -- clut bank switching enable + VBSW : out std_logic; -- video page bank switching enable + Ven : out std_logic; -- video system enable + + -- status register inputs + AVMP, -- active video memory page + ACMP : in std_logic; -- active clut page + bsint_in, + hint_in, + vint_in, + luint_in, + sint_in : in std_logic; -- interrupt request signals + + -- Horizontal Timing Register + Thsync : out unsigned(7 downto 0); + Thgdel : out unsigned(7 downto 0); + Thgate : out unsigned(15 downto 0); + Thlen : out unsigned(15 downto 0); + + -- Vertical Timing Register + Tvsync : out unsigned(7 downto 0); + Tvgdel : out unsigned(7 downto 0); + Tvgate : out unsigned(15 downto 0); + Tvlen : out unsigned(15 downto 0); + + VBARa, + VBARb : buffer unsigned(31 downto 2); + CBAR : buffer unsigned(31 downto 11) +); +end entity wb_slave; + +architecture structural of wb_slave is + signal ctrl, stat, htim, vtim, hvlen : std_logic_vector(31 downto 0); + signal HINT, VINT, BSINT, LUINT, SINT : std_logic; + signal HIE, VIE, BSIE : std_logic; + signal acc, acc32, reg_acc : std_logic; +begin + acc <= CYC_I and STB_I; + acc32 <= SEL_I(3) and SEL_I(2) and SEL_I(1) and SEL_I(0); + reg_acc <= acc and acc32 and WE_I; + ACK_O <= acc and acc32; + ERR_O <= acc and not acc32; + + gen_regs: process(CLK_I, nRESET) + begin + if (nReset = '0') then + ctrl <= (others => '0'); + htim <= (others => '0'); + vtim <= (others => '0'); + hvlen <= (others => '0'); + VBARa <= (others => '0'); + VBARb <= (others => '0'); + CBAR <= (others => '0'); + elsif(CLK_I'event and CLK_I = '1') then + if (RST_I = '1') then + ctrl <= (others => '0'); + htim <= (others => '0'); + vtim <= (others => '0'); + hvlen <= (others => '0'); + VBARa <= (others => '0'); + VBARb <= (others => '0'); + CBAR <= (others => '0'); + elsif (reg_acc = '1') then + case ADR_I is + when "000" => ctrl <= DAT_I; + when "001" => null; -- status register (see gen_stat process) + when "010" => htim <= DAT_I; + when "011" => vtim <= DAT_I; + when "100" => hvlen <= DAT_I; + when "101" => VBARa <= unsigned(DAT_I(31 downto 2)); + when "110" => VBARb <= unsigned(DAT_I(31 downto 2)); + when "111" => CBAR <= unsigned(DAT_I(31 downto 11)); + + when others => null; -- should never happen + end case; + end if; + end if; + end process gen_regs; + + -- generate status register + gen_stat: process(CLK_I, nRESET) + begin + if (nReset = '0') then + stat <= (others => '0'); + elsif(CLK_I'event and CLK_I = '1') then + if (RST_I = '1') then + stat <= (others => '0'); + else + stat(17) <= ACMP; + stat(16) <= AVMP; + stat( 6) <= bsint_in or (stat(6) and not (reg_acc and WE_I and DAT_I(6)) ); + stat( 5) <= hint_in or (stat(5) and not (reg_acc and WE_I and DAT_I(5)) ); + stat( 4) <= vint_in or (stat(4) and not (reg_acc and WE_I and DAT_I(4)) ); + stat( 1) <= luint_in or (stat(1) and not (reg_acc and WE_I and DAT_I(1)) ); + stat( 0) <= sint_in or (stat(0) and not (reg_acc and WE_I and DAT_I(0)) ); + end if; + end if; + end process gen_stat; + + -- decode control register + BL <= ctrl(15); + CSL <= ctrl(14); + VSL <= ctrl(13); + HSL <= ctrl(12); + PC <= ctrl(11); + CD <= ctrl(10 downto 9); + VBL <= ctrl(8 downto 7); + CBSW <= ctrl(5); + VBSW <= ctrl(4); + BSIE <= ctrl(3); + HIE <= ctrl(2); + VIE <= ctrl(1); + Ven <= ctrl(0); + + -- decode status register + BSINT <= stat(6); + HINT <= stat(5); + VINT <= stat(4); + LUINT <= stat(1); + SINT <= stat(0); + + -- decode Horizontal Timing Register + Thsync <= unsigned(htim(31 downto 24)); + Thgdel <= unsigned(htim(23 downto 16)); + Thgate <= unsigned(htim(15 downto 0)); + Thlen <= unsigned(hvlen(31 downto 16)); + + -- decode Vertical Timing Register + Tvsync <= unsigned(vtim(31 downto 24)); + Tvgdel <= unsigned(vtim(23 downto 16)); + Tvgate <= unsigned(vtim(15 downto 0)); + Tvlen <= unsigned(hvlen(15 downto 0)); + + + -- assign output + with ADR_I select + DAT_O <= ctrl when "000", + stat when "001", + htim when "010", + vtim when "011", + hvlen when "100", + std_logic_vector(VBARa & "00") when "101", + std_logic_vector(VBARb & "00") when "110", + std_logic_vector(CBAR & ACMP & "0000000000") when others; + + -- generate interrupt request signal + INTA_O <= (HINT and HIE) or (VINT and VIE) or (BSINT and BSIE) or LUINT or SINT; +end architecture structural; + Index: tags/rel_1/rtl/vhdl/csm_pb.vhd =================================================================== --- tags/rel_1/rtl/vhdl/csm_pb.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/csm_pb.vhd (revision 42) @@ -0,0 +1,179 @@ +-- +-- Wishbone compliant cycle shared memory, priority based selection +-- author: Richard Herveille +-- +-- rev.: 1.0 july 12th, 2001. Initial release +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity csm_pb is + generic( + DWIDTH : natural := 32; -- databus width + AWIDTH : natural := 8 -- addressbus width + ); + port( + -- SYSCON signals + CLK_I : in std_logic; -- wishbone clock input + RST_I : in std_logic; -- synchronous active high reset + nRESET : in std_logic; -- asynchronous active low reset + + -- wishbone slave0 connections + ADR0_I : in unsigned(AWIDTH -1 downto 0); -- address input + DAT0_I : in std_logic_vector(DWIDTH -1 downto 0); -- data input + DAT0_O : out std_logic_vector(DWIDTH -1 downto 0); -- data output + SEL0_I : in std_logic_vector( (DWIDTH/8) -1 downto 0); -- byte select input + WE0_I : in std_logic; -- write enable input + STB0_I : in std_logic; -- strobe input + CYC0_I : in std_logic; -- valid bus cycle input + ACK0_O : out std_logic; -- acknowledge output + ERR0_O : out std_logic; -- error output + + -- wishbone slave1 connections + ADR1_I : in unsigned(AWIDTH -1 downto 0); -- address input + DAT1_I : in std_logic_vector(DWIDTH -1 downto 0); -- data input + DAT1_O : out std_logic_vector(DWIDTH -1 downto 0); -- data output + SEL1_I : in std_logic_vector( (DWIDTH/8) -1 downto 0); -- byte select input + WE1_I : in std_logic; -- write enable input + STB1_I : in std_logic; -- strobe input + CYC1_I : in std_logic; -- valid bus cycle input + ACK1_O : out std_logic; -- acknowledge output + ERR1_O : out std_logic -- error output + ); +end entity csm_pb; + +architecture structural of csm_pb is + -- function declarations + function "and"(L: std_logic_vector; R : std_logic) return std_logic_vector is + variable tmp : std_logic_vector(L'range); + begin + for n in L'range loop + tmp(n) := L(n) and R; + end loop; + return tmp; + end function "and"; + + function "and"(L: std_logic; R : std_logic_vector) return std_logic_vector is + begin + return (R and L); + end function "and"; + + -- define memory array + type mem_array is array(2**AWIDTH -1 downto 0) of std_logic_vector(DWIDTH -1 downto 0); + signal mem : mem_array; + + -- multiplexor select signal + signal wb0_acc, dwb0_acc : std_logic; + signal wb1_acc, dwb1_acc : std_logic; + signal sel_wb0 : std_logic; + signal sel_wb1 : std_logic; + signal ack0_pipe, ack1_pipe : std_logic_vector(3 downto 0); + + -- multiplexed memory busses / signals + signal mem_adr, mem_radr : unsigned(AWIDTH -1 downto 0); + signal mem_dati, mem_dato : std_logic_vector(DWIDTH -1 downto 0); + signal mem_we : std_logic; + + -- acknowledge generation + signal wb0_ack, wb1_ack : std_logic; + + -- error signal generation + signal err0, err1 : std_logic_vector( (DWIDTH/8) -1 downto 0); + +begin + -- generate multiplexor select signal + wb0_acc <= CYC0_I and STB0_I; + wb1_acc <= CYC1_I and STB1_I and not sel_wb0; + + process(CLK_I) + begin + if (CLK_I'event and CLK_I = '1') then + dwb0_acc <= wb0_acc and not wb0_ack; + dwb1_acc <= wb1_acc and not wb1_ack; + end if; + end process; + + sel_wb0 <= wb0_acc and not dwb0_acc; + sel_wb1 <= wb1_acc and not dwb1_acc; + + gen_ack_pipe: process(CLK_I, nRESET) + begin + if (nRESET = '0') then + ack0_pipe <= (others => '0'); + ack1_pipe <= (others => '0'); + elsif (CLK_I'event and CLK_I = '1') then + if (RST_I = '1') then + ack0_pipe <= (others => '0'); + ack1_pipe <= (others => '0'); + else + ack0_pipe <= (ack0_pipe(2 downto 0) & sel_wb0) and not wb0_ack; + ack1_pipe <= (ack1_pipe(2 downto 0) & sel_wb1) and not wb1_ack; + end if; + end if; + end process gen_ack_pipe; + + -- multiplex memory bus +-- gen_muxs: process(CLK_I) +-- begin +-- if (CLK_I'event and CLK_I = '1') then +-- if (sel_wb0 = '1') then +-- mem_adr <= adr0_i; +-- mem_dati <= dat0_i; +-- mem_we <= we0_i and cyc0_i and stb0_i and not wb0_ack; +-- else +-- mem_adr <= adr1_i; +-- mem_dati <= dat1_i; +-- mem_we <= we1_i and cyc1_i and stb1_i and not wb1_ack; +-- end if; +-- end if; +-- end process gen_muxs; + + mem_adr <= adr0_i when (sel_wb0 = '1') else adr1_i; + mem_dati <= dat0_i when (sel_wb0 = '1') else dat1_i; + mem_we <= (we0_i and cyc0_i and stb0_i) when (sel_wb0 = '1') else (we1_i and cyc1_i and stb1_i); + + -- memory access + gen_mem: process(CLK_I) + begin + if (CLK_I'event and CLK_I = '1') then + -- write operation + if (mem_we = '1') then + mem(conv_integer(mem_adr)) <= mem_dati; + end if; + + -- read operation + mem_radr <= mem_adr; -- FLEX RAMs require address to be registered with inclock for read operation. + mem_dato <= mem(conv_integer(mem_radr)); + end if; + end process gen_mem; + + -- assign DAT_O outputs + DAT1_O <= mem_dato; + DAT0_O <= mem_dato; + + -- assign ACK_O outputs +-- gen_ack: process(CLK_I) +-- begin +-- if (CLK_I'event and CLK_I = '1') then + wb0_ack <= ( (sel_wb0 and WE0_I) or (ack0_pipe(1)) );-- and not wb0_ack; + wb1_ack <= ( (sel_wb1 and WE1_I) or (ack1_pipe(1)) );-- and not wb1_ack; +-- end if; +-- end process gen_ack; + -- ACK outputs + ACK0_O <= wb0_ack; + ACK1_O <= wb1_ack; + + -- ERR outputs + err0 <= (others => '1'); + ERR0_O <= '1' when ( (SEL0_I /= err0) and (CYC0_I = '1') and (STB0_I = '1') ) else '0'; + + err1 <= (others => '1'); + ERR1_O <= '1' when ( (SEL1_I /= err1) and (CYC1_I = '1') and (STB1_I = '1') ) else '0'; +end architecture; + + + + Index: tags/rel_1/rtl/vhdl/fifo.vhd =================================================================== --- tags/rel_1/rtl/vhdl/fifo.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/fifo.vhd (revision 42) @@ -0,0 +1,150 @@ +-- +-- File fifo.vhd (universal FIFO) +-- Author : Richard Herveille +-- rev.: 0.1 May 04th, 2001 +-- rev.: 0.2 June 16th, 2001. Changed "function bitcount" until it compiled under Xilinx Webpack +-- rev.: 0.3 June 23nd, 2001. Removed unused "dummy" variable from function bitcount. +-- rev.: 1.0 June 29th, 2001. Synchronized Q output. Design now correctly maps to Xilinx-BlockRAMs +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity FIFO is + generic( + DEPTH : natural := 128; + WIDTH : natural := 32 + ); + port( + clk : in std_logic; -- clock input + aclr : in std_logic := '1'; -- active low asynchronous clear + sclr : in std_logic := '0'; -- active high synchronous clear + + D : in std_logic_vector(WIDTH -1 downto 0); -- Data input + wreq : in std_logic; -- write request + + Q : out std_logic_vector(WIDTH -1 downto 0); -- Data output + rreq : in std_logic; -- read request + + empty, -- FIFO is empty + hfull, -- FIFO is half full + full : out std_logic -- FIFO is full + ); +end entity FIFO; + +architecture structural of FIFO is + -- bitcount, return no.of bits required for 'n' + function bitcount(n : in natural) return natural is + variable tmp : unsigned(32 downto 1); + variable cnt : natural; + begin + tmp := conv_unsigned(n, 32); + +-- "while..loop" is not supported by xilinx webpack yet +-- cnt := 32; +-- while ( (tmp(cnt) = '0') and (cnt > 0) ) loop +-- cnt := cnt -1; +-- end loop; + + -- replaced "while..loop" with "loop..exit" for xilinx web-pack +-- "loop" is not supported by xilinx webpack yet +-- cnt := 32; +-- loop +-- exit when ( (tmp(cnt) /= '0') or (cnt = 0) ); +-- cnt := cnt -1; +-- end loop; + + -- same construction as above, now using for..loop +-- "exit" statement not supported by xilinx webpack yet (what IS supported ?????) +-- for cnt in 32 downto 1 loop +-- exit when ( (tmp(cnt) /= '0') or (cnt = 0) ); +-- end loop; + + -- yet another try + cnt := 32; + for dummy in 32 downto 1 loop + if (tmp(cnt) = '0') then + cnt := cnt -1; + end if; + end loop; + + return cnt; + end function bitcount; + + constant ADEPTH : natural := bitcount(DEPTH -1); -- 256 entries: range 255 downto 0 + + type mem_type is array (DEPTH -1 downto 0) of std_logic_vector(WIDTH -1 downto 0); + signal mem : mem_type; -- VHDL '87 syntax + + signal rptr, wptr : unsigned(ADEPTH -1 downto 0); + signal fifo_cnt : unsigned(ADEPTH downto 0); +begin + -- read pointer + gen_rd_ptr: process(clk, aclr) + begin + if (aclr = '0') then + rptr <= (others => '0'); + elsif (clk'event and clk = '1') then + if (sclr = '1') then + rptr <= (others => '0'); + elsif (rreq = '1') then + rptr <= rptr +1; + end if; + end if; + end process gen_rd_ptr; + + -- write pointer + gen_wr_ptr: process(clk, aclr) + begin + if (aclr = '0') then + wptr <= (others => '0'); + elsif (clk'event and clk = '1') then + if (sclr = '1') then + wptr <= (others => '0'); + elsif (wreq = '1') then + wptr <= wptr +1; + end if; + end if; + end process gen_wr_ptr; + + -- memory array operations + gen_mem: process(clk) + begin + if (clk'event and clk = '1') then + if (wreq = '1') then + mem(conv_integer(wptr)) <= D; -- store D in memory array + end if; + Q <= mem(conv_integer(rptr)); -- assign output + end if; + end process gen_mem; + + -- number of words in fifo + gen_fifo_cnt: process(clk, aclr, fifo_cnt, wreq, rreq) + variable count : unsigned(ADEPTH downto 0); + begin + count := fifo_cnt; + + if (wreq = '1') then + count := count +1; + end if; + if (rreq = '1') then + count := count -1; + end if; + + if (aclr = '0') then + fifo_cnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if (sclr = '1') then + fifo_cnt <= (others => '0'); + else + fifo_cnt <= count; + end if; + end if; + end process gen_fifo_cnt; + + -- status flags + empty <= '1' when (fifo_cnt = 0) else '0'; + hfull <= fifo_cnt(ADEPTH -1); + full <= fifo_cnt(ADEPTH); +end architecture structural; Index: tags/rel_1/rtl/vhdl/wb_master.vhd =================================================================== --- tags/rel_1/rtl/vhdl/wb_master.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/wb_master.vhd (revision 42) @@ -0,0 +1,387 @@ +-- +-- File wb_master.vhd, WISHBONE MASTER interface (video-memory/clut memory) +-- Project: VGA +-- Author : Richard Herveille +-- rev.: 1.0 May 1st, 2001 +-- rev.: 1.1 June 3rd, 2001. Changed address related sections. +-- rev.: 1.2 June 23nd, 2001. Removed unused "sel_vba", "vmem_offs" and "bl" signals. +-- rev.: 1.3 July 6th, 2001. Major bug fixes; core did not respond correctly to delayed ACK_I generation. +-- rev.: 1.4 July 15th, 2001. Added CLUT bank switching. +-- Removed multiplier, replaced it by counters +-- Fixed timing bug. +-- rev.: 1.5 July 17th, 2001. Fixed a weird condition where to core got stuck during a video memory access, caused by +-- the image_done timers. +-- rev.: 1.6 July 31th, 2001. Fixed a bug where the video/clut banks would switch with a 1 frame delay. +-- Fixed a bug where the data in the RGB-buffer could be overwritten. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +library count; +use count.count.all; + +entity wb_master is + port( + -- WISHBONE signals + CLK_I : in std_logic; -- master clock input + RST_I : in std_logic; -- synchronous active high reset + nRESET : in std_logic; -- asynchronous active low reset + CYC_O : out std_logic; -- cycle output + STB_O : out std_logic; -- strobe output + CAB_O : out std_logic; -- Consecutive Address Burst output + WE_O : out std_logic; -- write enable output + ADR_O : out unsigned(31 downto 2); -- address output + SEL_O : out std_logic_vector(3 downto 0); -- Byte Select outputs (only 32bit accesses are supported) + ACK_I : in std_logic; -- WISHBONE cycle acknowledge signal + ERR_I : in std_logic; -- oops, bus-error + DAT_I : in std_logic_vector(31 downto 0); -- WISHBONE data in + + SINT : out std_logic; -- Non recoverable error, interrupt host + + -- control register settings + ctrl_Ven : in std_logic; -- video enable bit + ctrl_cd : in std_logic_vector(1 downto 0); -- color depth + ctrl_pc : in std_logic; -- 8bpp pseudo color/bw + ctrl_vbl : in std_logic_vector(1 downto 0); -- burst length + ctrl_vbsw : in std_logic; -- enable video bank switching + ctrl_cbsw : in std_logic; -- enable clut bank switching + + -- video memory addresses + VBAa, -- Video Memory Base Address-A + VBAb : in unsigned(31 downto 2); -- Video Memory Base Address-B + CBA : in unsigned(31 downto 11); -- CLUT Base Address Register + + Thgate : in unsigned(15 downto 0); -- horizontal visible area (in pixels) + Tvgate : in unsigned(15 downto 0); -- vertical visible area (in horizontal lines) + + stat_AVMP : out std_logic; -- active video memory page + stat_ACMP : out std_logic; -- active color lookup table + bs_req : out std_logic; -- bank-switch request: memory page switched (when enabled). bs_req is always generated + + -- to/from line fifo + line_fifo_wreq : out std_logic; + line_fifo_d : out std_logic_vector(23 downto 0); + line_fifo_full : in std_logic + ); +end entity wb_master; + +architecture structural of wb_master is + -- + -- component declarations + -- + -- FIFO + component FIFO is + generic( + DEPTH : natural := 128; + WIDTH : natural := 32 + ); + port( + clk : in std_logic; -- clock input + aclr : in std_logic := '1'; -- active low asynchronous clear + sclr : in std_logic := '0'; -- active high synchronous clear + + D : in std_logic_vector(WIDTH -1 downto 0); -- Data input + wreq : in std_logic; -- write request + + Q : out std_logic_vector(WIDTH -1 downto 0); -- Data output + rreq : in std_logic; -- read request + + empty, -- FIFO is empty + hfull, -- FIFO is half full + full : out std_logic -- FIFO is full + ); + end component FIFO; + + -- color processor (convert data from pixel buffer to RGB) + component colproc is + port( + clk : in std_logic; -- master clock + ctrl_Ven : in std_logic; -- Video Enable + + pixel_buffer_Di, -- Pixel Buffer data input + WB_Di : in std_logic_vector(31 downto 0); -- WISHBONE data input + + ColorDepth : in std_logic_vector(1 downto 0); -- color depth (8bpp, 16bpp, 24bpp) + PseudoColor : in std_logic; -- pseudo color enabled (only for 8bpp color depth) + + pixel_buffer_empty : in std_logic; + pixel_buffer_rreq : buffer std_logic; -- pixel buffer read request + + RGB_fifo_full : in std_logic; + RGB_fifo_wreq : out std_logic; + R,G,B : out std_logic_vector(7 downto 0); -- pixel color (to RGB fifo) + + clut_req : out std_logic; -- CLUT access request + clut_offs: out unsigned(7 downto 0); -- offset into color lookup table + clut_ack : in std_logic -- CLUT data acknowledge + ); + end component colproc; + + signal nVen : std_logic; -- NOT ctrl_Ven (video enable) + signal vmem_acc, clut_acc : std_logic; -- video memory access // clut access + signal clut_req, clut_ack : std_logic; -- clut access request // clut access acknowledge + signal clut_offs : unsigned(7 downto 0); -- clut memory offset + signal nvmem_req, vmem_ack : std_logic; -- NOT video memory access request // video memory access acknowledge + signal ImDoneStrb, dImDoneStrb : std_logic; -- image done (strobe signal) + signal pixelbuf_rreq, pixelbuf_empty, pixelbuf_empty_flush, pixelbuf_flush, pixelbuf_hfull : std_logic; + signal pixelbuf_q : std_logic_vector(31 downto 0); + signal RGBbuf_rreq, RGBbuf_wreq, RGBbuf_empty, RGBbuf_full, fill_RGBfifo, RGB_fifo_full : std_logic; + signal RGBbuf_d : std_logic_vector(23 downto 0); +begin + + + -- + -- WISHBONE block + -- + WB_block: block + signal burst_cnt : unsigned(2 downto 0); -- video memory burst access counter + signal ImDone, dImDone, burst_done : std_logic; -- Done reading image from video mem // delayed ImDone // completed burst access to video mem + signal sel_VBA, sel_CBA : std_logic; -- select video memory base address // select clut base address + signal vmemA, clutA : unsigned(31 downto 2); -- video memory address // clut address + signal hgate_cnt, vgate_cnt : unsigned(15 downto 0); -- horizontal / vertical pixel counters + signal hdone, vdone : std_logic; -- horizontal count done / vertical count done + begin + -- + -- wishbone access controller, video memory access request has highest priority (try to keep fifo full) + -- + access_ctrl: process(CLK_I) + begin + if(CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + vmem_acc <= '0'; + clut_acc <= '0'; + else + clut_acc <= clut_req and ( (nvmem_req and not vmem_acc) or clut_acc); + vmem_acc <= (not nvmem_req or (vmem_acc and not (burst_done and vmem_ack) )) and not clut_acc; + end if; + end if; + end process access_ctrl; + + vmem_ack <= ACK_I and vmem_acc; + clut_ack <= ACK_I and clut_acc; + + SINT <= (vmem_acc or clut_acc) and ERR_I; -- Non recoverable error, interrupt host system + + -- select active memory page + gen_sel_VBA: process(CLK_I) + begin + if(CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + sel_VBA <= '0'; + elsif (ctrl_vbsw = '1') then + sel_VBA <= sel_VBA xor ImDoneStrb; -- select next video memory bank when finished reading current bank (and bank switch enabled) + end if; + end if; + end process gen_sel_VBA; + stat_AVMP <= sel_VBA; -- assign output + + gen_sel_CBA: process(CLK_I) + begin + if(CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + sel_CBA <= '0'; + elsif (ctrl_cbsw = '1') then + sel_CBA <= sel_CBA xor ImDoneStrb; -- select next clut when finished reading current video bank + end if; + end if; + end process gen_sel_CBA; + stat_ACMP <= sel_CBA; -- assign output + + -- assign bank_switch_request (status register) output + bs_req <= ImDoneStrb and ctrl_Ven; -- bank switch request + + -- generate burst counter + gen_burst_cnt: process(CLK_I, ctrl_vbl, burst_cnt) + variable bl : unsigned(2 downto 0); + variable val : unsigned(3 downto 0); + begin + case ctrl_vbl is + when "00" => bl := "000"; -- burst length 1 + when "01" => bl := "001"; -- burst length 2 + when "10" => bl := "011"; -- burst length 4 + when others => bl := "111"; -- burst length 8 + end case; + + val := ('0' & burst_cnt) -1; + + if (CLK_I'event and CLK_I = '1') then + if ( ((burst_done = '1') and (vmem_ack = '1')) or (vmem_acc = '0')) then + burst_cnt <= bl; + elsif (vmem_ack = '1') then + burst_cnt <= val(2 downto 0); + end if; + end if; + + burst_done <= val(3); + end process gen_burst_cnt; + + -- + -- generate image counters + -- + + -- hgate counter + hgate_count: process(CLK_I, hgate_cnt) + variable val : unsigned(16 downto 0); + begin + val := ('0' & hgate_cnt) -1; + + if (CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + hgate_cnt <= Thgate; + elsif (RGBbuf_wreq = '1') then + if (hdone = '1') then + hgate_cnt <= Thgate; + else + hgate_cnt <= val(15 downto 0); + end if; + end if; + end if; + + hdone <= val(16); + end process hgate_count; + + vgate_count: process(CLK_I, vgate_cnt) + variable val : unsigned(16 downto 0); + begin + val := ('0' & vgate_cnt) -1; + + if (CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + vgate_cnt <= Tvgate; + elsif ((hdone = '1') and (RGBbuf_wreq = '1')) then + if (ImDone = '1') then + vgate_cnt <= Tvgate; + else + vgate_cnt <= val(15 downto 0); + end if; + end if; + end if; + + vdone <= val(16); + end process vgate_count; + + ImDone <= hdone and vdone; + ImDoneStrb <= ImDone and not dImDone; + + gen_pix_done: process(CLK_I) + begin + if (CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + dImDone <= '0'; + else + dImDone <= ImDone; + end if; + + dImDoneStrb <= ImDoneStrb; + end if; + end process gen_pix_done; + + -- + -- generate addresses + -- + addr: process(CLK_I, sel_VBA, VBAa, VBAb) + begin + -- select video memory base address + if (CLK_I'event and CLK_I = '1') then + -- calculate video memory address + if ((dImDoneStrb = '1') or (ctrl_Ven = '0')) then + if (sel_VBA = '0') then + vmemA <= VBAa; + else + vmemA <= VBAb; + end if; + elsif (vmem_ack = '1') then + vmemA <= vmemA + 1; + end if; + end if; + end process addr; + + -- calculate CLUT address + clutA <= (CBA & sel_CBA & clut_offs); + + -- generate wishbone signals + gen_wb_sigs: process(CLK_I, nRESET, vmemA, clutA, vmem_acc) + begin + + -- assign wishbone address + if (vmem_acc = '1') then + ADR_O <= vmemA; + else + ADR_O <= clutA; + end if; + + if (nRESET = '0') then + CYC_O <= '0'; + STB_O <= '0'; + SEL_O <= "1111"; + CAB_O <= '0'; + WE_O <= '0'; + elsif (CLK_I'event and CLK_I = '1') then + if (RST_I = '1') then + CYC_O <= '0'; + STB_O <= '0'; + SEL_O <= "1111"; + CAB_O <= '0'; + WE_O <= '0'; + else + CYC_O <= (clut_acc and clut_req and not ACK_I) or (vmem_acc and not (burst_done and vmem_ack and nvmem_req) ); + STB_O <= (clut_acc and clut_req and not ACK_I) or (vmem_acc and not (burst_done and vmem_ack and nvmem_req) ); -- same as CYC_O; only 1 register+logic needed + SEL_O <= "1111"; -- only 32bit accesses are supported + CAB_O <= vmem_acc and not (burst_done and vmem_ack and nvmem_req); + WE_O <= '0'; -- read only + end if; + end if; + end process gen_wb_sigs; + end block WB_block; + + + nVen <= not ctrl_Ven; + pixelbuf_flush <= nVen or ImDoneStrb; + + -- pixel buffer (temporary store data read from video memory) + pixel_buf: FIFO generic map (DEPTH => 16, WIDTH => 32) + port map(clk => CLK_I, sclr => pixelbuf_flush, D => DAT_I, wreq => vmem_ack, Q => pixelbuf_q, rreq => pixelbuf_rreq, + empty => pixelbuf_empty, hfull => pixelbuf_hfull); + + nvmem_req <= not (not pixelbuf_hfull and not ImDoneStrb); + + -- hookup color processor + gen_fill_RGBfifo: process(CLK_I) + begin + if (CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + fill_RGBfifo <= '0'; + else + fill_RGBfifo <= (RGBbuf_empty or fill_RGBfifo) and not RGBbuf_full; + end if; + end if; + end process gen_fill_RGBfifo; + RGB_fifo_full <= not (fill_RGBfifo and not RGBbuf_full); -- not fill_RGBfifo or RGBbuf_full + + pixelbuf_empty_flush <= pixelbuf_empty or pixelbuf_flush; + color_proc: colproc port map (clk => CLK_I, ctrl_Ven => ctrl_Ven, pixel_buffer_di => pixelbuf_q, WB_Di => DAT_I, ColorDepth => ctrl_CD, + PseudoColor => ctrl_PC, pixel_buffer_empty => pixelbuf_empty_flush, pixel_buffer_rreq => pixelbuf_rreq, + RGB_fifo_full => RGB_fifo_full, RGB_fifo_wreq => RGBbuf_wreq, R => RGBbuf_d(23 downto 16), G => RGBbuf_d(15 downto 8), + B => RGBbuf_d(7 downto 0), clut_req => clut_req, clut_offs => clut_offs, clut_ack => clut_ack); + + -- hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain) + RGB_buf: FIFO generic map (DEPTH => 8, WIDTH => 24) + port map (clk => CLK_I, sclr => nVen, D => RGBbuf_d, wreq => RGBbuf_wreq, Q => line_fifo_d, rreq => RGBbuf_rreq, + empty => RGBbuf_empty, hfull => RGBbuf_full); + + -- hookup line fifo + gen_lfifo_wreq: process(CLK_I) + begin + if (CLK_I'event and CLK_I = '1') then + if (ctrl_Ven = '0') then + RGBbuf_rreq <= '0'; + else + RGBbuf_rreq <= not line_fifo_full and not RGBbuf_empty and not RGBbuf_rreq; + end if; + end if; + end process gen_lfifo_wreq; + line_fifo_wreq <= RGBbuf_rreq; + +end architecture structural; Index: tags/rel_1/rtl/vhdl/vga_and_clut.vhd =================================================================== --- tags/rel_1/rtl/vhdl/vga_and_clut.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/vga_and_clut.vhd (revision 42) @@ -0,0 +1,227 @@ +-- +-- file: vga_and_clut.vhd +-- project: VGA/LCD controller + Color Lookup Table +-- author: Richard Herveille +-- +-- rev. 1.0 July 4th, 2001. +-- rev. 1.1 July 15th, 2001. Changed cycle_shared_memory to csm_pb. The core does not require a CLKx2 clock anymore. +-- Added CLUT bank switching + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity vga_and_clut is + port( + CLK_I : in std_logic; -- wishbone clock input + RST_I : in std_logic; -- synchronous active high reset + NRESET : in std_logic; -- asynchronous active low reset + INTA_O : out std_logic; -- interrupt request output + + -- slave signals + ADR_I : in unsigned(10 downto 2); -- addressbus input (only 32bit databus accesses supported) + SDAT_I : in std_logic_vector(31 downto 0); -- Slave databus output + SDAT_O : out std_logic_vector(31 downto 0); -- Slave databus input + SEL_I : in std_logic_vector(3 downto 0); -- byte select inputs + WE_I : in std_logic; -- write enabel input + VGA_STB_I : in std_logic; -- vga strobe/select input + CLUT_STB_I : in std_logic; -- color-lookup-table strobe/select input + CYC_I : in std_logic; -- valid bus cycle input + ACK_O : out std_logic; -- bus cycle acknowledge output + ERR_O : out std_logic; -- bus cycle error output + + -- master signals + ADR_O : out unsigned(31 downto 2); -- addressbus output + MDAT_I : in std_logic_vector(31 downto 0); -- Master databus input + SEL_O : out std_logic_vector(3 downto 0); -- byte select outputs + WE_O : out std_logic; -- write enable output + STB_O : out std_logic; -- strobe output + CYC_O : out std_logic; -- valid bus cycle output + CAB_O : out std_logic; -- continuos address burst output + ACK_I : in std_logic; -- bus cycle acknowledge input + ERR_I : in std_logic; -- bus cycle error input + + -- VGA signals + PCLK : in std_logic; -- pixel clock + HSYNC : out std_logic; -- horizontal sync + VSYNC : out std_logic; -- vertical sync + CSYNC : out std_logic; -- composite sync + BLANK : out std_logic; -- blanking signal + R,G,B : out std_logic_vector(7 downto 0) -- RGB color signals + ); +end entity vga_and_clut; + +architecture structural of vga_and_clut is + -- + -- component declarations + -- + component VGA is + port ( + CLK_I : in std_logic; + RST_I : in std_logic; + NRESET : in std_logic; + INTA_O : out std_logic; + + -- slave signals + ADR_I : in unsigned(4 downto 2); -- only 32bit databus accesses supported + SDAT_I : in std_logic_vector(31 downto 0); + SDAT_O : out std_logic_vector(31 downto 0); + SEL_I : in std_logic_vector(3 downto 0); + WE_I : in std_logic; + STB_I : in std_logic; + CYC_I : in std_logic; + ACK_O : out std_logic; + ERR_O : out std_logic; + + -- master signals + ADR_O : out unsigned(31 downto 2); + MDAT_I : in std_logic_vector(31 downto 0); + SEL_O : out std_logic_vector(3 downto 0); + WE_O : out std_logic; + STB_O : out std_logic; + CYC_O : out std_logic; + CAB_O : out std_logic; + ACK_I : in std_logic; + ERR_I : in std_logic; + + -- VGA signals + PCLK : in std_logic; -- pixel clock + HSYNC : out std_logic; -- horizontal sync + VSYNC : out std_logic; -- vertical sync + CSYNC : out std_logic; -- composite sync + BLANK : out std_logic; -- blanking signal + R,G,B : out std_logic_vector(7 downto 0) -- RGB color signals + ); + end component vga; + + component csm_pb is + generic( + DWIDTH : natural := 32; -- databus width + AWIDTH : natural := 8 -- addressbus width + ); + port( + -- SYSCON signals + CLK_I : in std_logic; -- wishbone clock input + RST_I : in std_logic; -- synchronous active high reset + nRESET : in std_logic; -- asynchronous active low reset + + -- wishbone slave0 connections + ADR0_I : in unsigned(AWIDTH -1 downto 0); -- address input + DAT0_I : in std_logic_vector(DWIDTH -1 downto 0); -- data input + DAT0_O : out std_logic_vector(DWIDTH -1 downto 0); -- data output + SEL0_I : in std_logic_vector( (DWIDTH/8) -1 downto 0); -- byte select input + WE0_I : in std_logic; -- write enable input + STB0_I : in std_logic; -- strobe input + CYC0_I : in std_logic; -- valid bus cycle input + ACK0_O : out std_logic; -- acknowledge output + ERR0_O : out std_logic; -- error output + + -- wishbone slave1 connections + ADR1_I : in unsigned(AWIDTH -1 downto 0); -- address input + DAT1_I : in std_logic_vector(DWIDTH -1 downto 0); -- data input + DAT1_O : out std_logic_vector(DWIDTH -1 downto 0); -- data output + SEL1_I : in std_logic_vector( (DWIDTH/8) -1 downto 0); -- byte select input + WE1_I : in std_logic; -- write enable input + STB1_I : in std_logic; -- strobe input + CYC1_I : in std_logic; -- valid bus cycle input + ACK1_O : out std_logic; -- acknowledge output + ERR1_O : out std_logic -- error output + ); + end component csm_pb; + + -- + -- Signal declarations + -- + signal CBA : unsigned(31 downto 11); -- color lookup table base address + + signal vga_clut_acc : std_logic; -- vga access to color lookup table + + signal empty_data : std_logic_vector(23 downto 0); -- all zeros + + signal vga_ack_o, vga_ack_i, vga_err_o, vga_err_i : std_logic; + signal vga_adr_o : unsigned(31 downto 2); + signal vga_dat_i, vga_dat_o : std_logic_vector(31 downto 0); -- vga master data input, vga slave data output + signal vga_sel_o : std_logic_vector(3 downto 0); + signal vga_we_o, vga_stb_o, vga_cyc_o : std_logic; + + signal vga_clut_stb : std_logic; + + signal mem0_dat_o, mem1_dat_o : std_logic_vector(23 downto 0); + signal mem0_ack_o, mem0_err_o : std_logic; + signal mem1_ack_o, mem1_err_o : std_logic; +begin + -- + -- capture VGA CBAR access + -- + process(CLK_I, nReset) + begin + if (nReset = '0') then + CBA <= (others => '0'); + elsif (CLK_I'event and CLK_I = '1') then + if (RST_I = '1') then + CBA <= (others => '0'); + elsif ( (SEL_I = "1111") and (CYC_I = '1') and (VGA_STB_I = '1') and (WE_I = '1') and (std_logic_vector(ADR_I(4 downto 2)) = "111") ) then + CBA <= unsigned(SDAT_I(31 downto 11)); + end if; + end if; + end process; + + -- generate vga_clut_acc. Because CYC_O and STB_O are generated one clock cycle after ADR_O, + -- vga_clut_acc may be synchronous. + process(CLK_I) + begin + if (CLK_I'event and CLK_I = '1') then + if (vga_adr_o(31 downto 11) = CBA) then + vga_clut_acc <= '1'; + else + vga_clut_acc <= '0'; + end if; + end if; + end process; + + -- + -- hookup vga controller + -- + u1: VGA port map (CLK_I => CLK_I, RST_I => RST_I, NRESET => nReset, INTA_O => INTA_O, + ADR_I => ADR_I(4 downto 2), SDAT_I => SDAT_I, SDAT_O => vga_dat_o, SEL_I => SEL_I, WE_I => WE_I, + STB_I => VGA_STB_I, CYC_I => CYC_I, ACK_O => vga_ack_o, ERR_O => vga_err_o, + ADR_O => vga_adr_o, MDAT_I => vga_dat_i, SEL_O => vga_sel_o, WE_O => vga_we_o, STB_O => vga_stb_o, + CYC_O => vga_cyc_o, CAB_O => CAB_O, ACK_I => vga_ack_i, ERR_I => vga_err_i, + PCLK => PCLK, HSYNC => HSYNC, VSYNC => VSYNC, CSYNC => CSYNC, BLANK => BLANK, R => R, G => G, B => B); + + -- + -- hookup cycle shared memory + -- + vga_clut_stb <= vga_stb_o when (vga_clut_acc = '1') else '0'; + + empty_data <= (others => '0'); + u2: csm_pb + generic map (DWIDTH => 24, AWIDTH => 9) + port map (CLK_I => CLK_I, RST_I => RST_I, nRESET => nReset, + ADR0_I => vga_adr_o(10 downto 2), DAT0_I => empty_data, DAT0_O => mem0_dat_o, SEL0_I => vga_sel_o(2 downto 0), + WE0_I => vga_we_o, STB0_I => vga_clut_stb, CYC0_I => vga_cyc_o, ACK0_O => mem0_ack_o, ERR0_O => mem0_err_o, + ADR1_I => ADR_I(10 downto 2), DAT1_I => SDAT_I(23 downto 0), DAT1_O => mem1_dat_o, SEL1_I => SEL_I(2 downto 0), + WE1_I => WE_I, STB1_I => CLUT_STB_I, CYC1_I => CYC_I, ACK1_O => mem1_ack_o, ERR1_O => mem1_err_o); + + -- + -- assign outputs + -- + + -- wishbone master + CYC_O <= '0' when (vga_clut_acc = '1') else vga_cyc_o; + STB_O <= '0' when (vga_clut_acc = '1') else vga_stb_o; + ADR_O <= vga_adr_o; + SEL_O <= vga_sel_o; + WE_O <= vga_we_o; + vga_dat_i(31 downto 24) <= MDAT_I(31 downto 24); + vga_dat_I(23 downto 0) <= mem0_dat_o when (vga_clut_acc = '1') else MDAT_I(23 downto 0); + vga_ack_i <= mem0_ack_o when (vga_clut_acc = '1') else ACK_I; + vga_err_i <= mem0_err_o when (vga_clut_acc = '1') else ERR_I; + + -- wishbone slave + SDAT_O <= (x"00" & mem1_dat_o) when (CLUT_STB_I = '1') else vga_dat_o; + ACK_O <= mem1_ack_o when (CLUT_STB_I = '1') else vga_ack_o; + ERR_O <= mem1_err_o when (CLUT_STB_I = '1') else vga_err_o; +end architecture structural; + + Index: tags/rel_1/rtl/vhdl/fifo_dc.vhd =================================================================== --- tags/rel_1/rtl/vhdl/fifo_dc.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/fifo_dc.vhd (revision 42) @@ -0,0 +1,145 @@ +-- +-- File fifo.vhd (universal FIFO) +-- Author : Richard Herveille +-- rev. 0.1 May 04th, 2001 : Initial release +-- rev. 1.0 May 17th, 2001 : Changed core to use dual_ported_memory entity => wrapper around target specific dual ported RAM. +-- +-- WARNING: DO NOT CHANGE THIS FILE +-- CHANGE "DPM.VHD" FOR TARGET SPECIFIC MEMORY BLOCKS +-- +-- rev. 1.1: June 23nd, 2001. Removed unused "drptr" and "fifo_cnt" signals +-- rev. 1.2: June 29th, 2001. Changed core to reflect changes in "dpm.vhd". + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity FIFO_DC is + generic( + DEPTH : natural := 128; + DWIDTH : natural := 32 + ); + port( + rclk : in std_logic; -- read clock input + wclk : in std_logic; -- write clock input + aclr : in std_logic := '1'; -- active low asynchronous clear + + D : in std_logic_vector(DWIDTH -1 downto 0); -- Data input + wreq : in std_logic; -- write request + + Q : out std_logic_vector(DWIDTH -1 downto 0); -- Data output + rreq : in std_logic; -- read request + + rd_empty, -- FIFO is empty, synchronous to read clock + rd_full, -- FIFO is full, synchronous to read clock + wr_empty, -- FIFO is empty, synchronous to write clock + wr_full : out std_logic -- FIFO is full, synchronous to write clock + ); +end entity FIFO_DC; + +architecture structural of FIFO_DC is + -- dual ported memory wrapper + component dual_ported_memory is + generic( + AWIDTH : natural := 8; + DWIDTH : natural := 32 + ); + port( + wclk : in std_logic; -- write clock input + D : in std_logic_vector(DWIDTH -1 downto 0); -- Data input + waddr : in unsigned(AWIDTH -1 downto 0); -- write clock address input + wreq : in std_logic; -- write request + + rclk : in std_logic; -- read clock input + Q : out std_logic_vector(DWIDTH -1 downto 0); -- Data output + raddr : in unsigned(AWIDTH -1 downto 0) -- read clock address input + ); + end component dual_ported_memory; + + -- bitcount, return no.of bits required for 'n' + function bitcount(n : in natural) return natural is + variable tmp : unsigned(32 downto 1); + variable cnt : integer; + begin + tmp := conv_unsigned(n, 32); + cnt := 32; + + while ( (tmp(cnt) = '0') and (cnt > 0) ) loop + cnt := cnt -1; + end loop; + + return natural(cnt); + end function bitcount; + + constant AWIDTH : natural := bitcount(DEPTH -1); -- 256 entries: range 255 downto 0 + + signal rptr, wptr : unsigned(AWIDTH -1 downto 0); + signal ifull, iempty, wempty, wfull, rempty, rfull : std_logic; +begin + -- + -- Pointers + -- + -- read pointer + gen_rd_ptr: process(rclk, aclr) + begin + if (aclr = '0') then + rptr <= (others => '0'); + elsif (rclk'event and rclk = '1') then + if (rreq = '1') then + rptr <= rptr +1; + end if; + end if; + end process gen_rd_ptr; + + -- write pointer + gen_wr_ptr: process(wclk, aclr) + begin + if (aclr = '0') then + wptr <= (others => '0'); + elsif (wclk'event and wclk = '1') then + if (wreq = '1') then + wptr <= wptr +1; + end if; + end if; + end process gen_wr_ptr; + + -- insert memory block. dual_ported_memory is a wrapper around a target specific dual ported RAM + mem: dual_ported_memory generic map(AWIDTH => AWIDTH, DWIDTH => DWIDTH) + port map(wclk => wclk, D => D, waddr => wptr, wreq => wreq, rclk => rclk, Q => Q, raddr => rptr); + + -- + -- status flags + -- + iempty <= '1' when (rptr = wptr) else '0'; + ifull <= '1' when ( (wptr - rptr) >= (DEPTH -2) ) else '0'; + + rd_flags: process(rclk, aclr) + begin + if (aclr = '0') then + rempty <= '1'; + rfull <= '0'; + rd_empty <= '1'; + rd_full <= '0'; + elsif (rclk'event and rclk = '1') then + rempty <= iempty; + rfull <= ifull; + rd_empty <= rempty; + rd_full <= rfull; + end if; + end process rd_flags; + + wr_flags: process(wclk, aclr) + begin + if (aclr = '0') then + wempty <= '1'; + wfull <= '0'; + wr_empty <= '1'; + wr_full <= '0'; + elsif (wclk'event and wclk = '1') then + wempty <= iempty; + wfull <= ifull; + wr_empty <= wempty; + wr_full <= wfull; + end if; + end process wr_flags; +end architecture structural; Index: tags/rel_1/rtl/vhdl/pgen.vhd =================================================================== --- tags/rel_1/rtl/vhdl/pgen.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/pgen.vhd (revision 42) @@ -0,0 +1,134 @@ +-- +-- File pgen.vhd, Video Pixel Generator +-- Project: VGA +-- Author : Richard Herveille +-- rev.: 0.1 April 19th, 2001. Initial release +-- rev.: 1.0 July 15th, 2001. Removed synchronized registers; static settings don't require synchronization. +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity Pgen is + port( + mclk : in std_logic; -- master clock + pclk : in std_logic; -- pixel clock + + ctrl_Ven : in std_logic; -- VideoEnable signal + + -- horizontal timing settings + ctrl_HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg) + Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels) + Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels) + Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line) + Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line) + + -- vertical timing settings + ctrl_VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg) + Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines) + Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines) + Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame) + Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame) + + ctrl_CSyncL : in std_logic; -- composite sync pulse polarization level + ctrl_BlankL : in std_logic; -- blank signal polarization level + + -- status outputs + eoh, -- end of horizontal + eov, -- end of vertical + Gate : out std_logic; -- vertical AND horizontal gate (logical AND function) + + -- pixel control outputs + Hsync, -- horizontal sync pulse + Vsync, -- vertical sync pulse + Csync, -- composite sync: Hsync OR Vsync (logical OR function) + Blank : out std_logic -- blank signals + ); +end entity Pgen; + +architecture dataflow of Pgen is + -- + -- Component declarations + -- + component tgen is + port( + clk : in std_logic; + rst : in std_logic; + + -- horizontal timing settings + HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg) + Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels) + Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels) + Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line) + Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line) + + -- vertical timing settings + VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg) + Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines) + Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines) + Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame) + Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame) + + CSyncL : in std_logic; -- composite sync pulse polarization level (pos/neg) + BlankL : in std_logic; -- blank signal polarization level + + eol, -- end of line + eof, -- end of frame + gate, -- vertical AND horizontal gate (logical and function) + + Hsync, -- horizontal sync pulse + Vsync, -- vertical sync pulse + Csync, -- composite sync pulse + Blank : out std_logic -- blank signal + ); + end component tgen; + + -- + -- signals + -- + signal eol, eof : std_logic; +begin + -- + -- timing block + -- + tblk: block + signal nVen : std_logic; -- video enable signal (active low) + begin + -- synchronize timing/control settings (from master-clock-domain to pixel-clock-domain) + sync_settings: process(pclk) + begin + if (pclk'event and pclk = '1') then + nVen <= not ctrl_Ven; + end if; + end process sync_settings; + + -- hookup video timing generator + vtgen: tgen port map (clk => pclk, rst => nVen, HSyncL => ctrl_HSyncL, Thsync => Thsync, Thgdel => Thgdel, Thgate => Thgate, Thlen => Thlen, + VsyncL => ctrl_VsyncL, Tvsync => Tvsync, Tvgdel => Tvgdel, Tvgate => Tvgate, Tvlen => Tvlen, CSyncL => ctrl_CSyncL, + BlankL => ctrl_BlankL, eol => eol, eof => eof, gate => gate, Hsync => Hsync, Vsync => Vsync, Csync => Csync, Blank => Blank); + end block tblk; + + -- + -- pixel clock + -- + pblk: block + signal seol, seof : std_logic; -- synchronized end-of-line, end-of-frame + signal dseol, dseof : std_logic; -- delayed synchronized eol, eof + begin + -- synchronize eol, eof (from pixel-clock-domain to master-clock-domain) + sync_eol_eof: process(mclk) + begin + if (mclk'event and mclk = '1') then + seol <= eol; + dseol <= seol; + seof <= eof; + dseof <= seof; + eoh <= seol and not dseol; + eov <= seof and not dseof; + end if; + end process sync_eol_eof; + end block pblk; + +end architecture dataflow; Index: tags/rel_1/rtl/vhdl/tgen.vhd =================================================================== --- tags/rel_1/rtl/vhdl/tgen.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/tgen.vhd (revision 42) @@ -0,0 +1,96 @@ +-- +-- File tgen.vhd, Video Horizontal and Vertical Timing Generator +-- Project: VGA +-- Author : Richard Herveille +-- rev.: 0.1 April 13th, 2001 +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity Tgen is + port( + clk : in std_logic; + rst : in std_logic; + + -- horizontal timing settings + HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg) + Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels) + Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels) + Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line) + Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line) + + -- vertical timing settings + VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg) + Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines) + Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines) + Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame) + Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame) + + CSyncL : in std_logic; -- composite sync pulse polarization level (pos/neg) + BlankL : in std_logic; -- blank signals polarizatio level + + eol, -- end of line + eof, -- end of frame + gate, -- vertical AND horizontal gate (logical and function) + + Hsync, -- horizontal sync pulse + Vsync, -- vertical sync pulse + Csync, -- composite sync + Blank : out std_logic -- blank signal + ); +end entity Tgen; + +architecture dataflow of Tgen is + -- + -- Component declarations + -- + component vtim is + port( + clk : in std_logic; -- master clock + ena : in std_logic := '1'; -- count enable + rst : in std_logic; -- synchronous active high reset + + Tsync : in unsigned(7 downto 0); -- sync duration + Tgdel : in unsigned(7 downto 0); -- gate delay + Tgate : in unsigned(15 downto 0); -- gate length + Tlen : in unsigned(15 downto 0); -- line time / frame time + + Sync : out std_logic; -- synchronization pulse + Gate : out std_logic; -- gate + Done : out std_logic -- done with line/frame + ); + end component vtim; + + -- + -- signals + -- + signal Hgate, Vgate : std_logic; + signal Hdone : std_logic; + signal iHsync, iVsync, igate : std_logic; +begin + -- hookup horizontal timing generator + hor_gen: vtim port map (clk => clk, rst => rst, + Tsync => Thsync, Tgdel => Thgdel, Tgate => Thgate, Tlen => Thlen, + Sync => iHsync, Gate => Hgate, Done => Hdone); + + -- hookup vertical timing generator + ver_gen: vtim port map (clk => clk, ena => Hdone, rst => rst, + Tsync => Tvsync, Tgdel => Tvgdel, Tgate => Tvgate, Tlen => Tvlen, + Sync => iVsync, Gate => Vgate, Done => eof); + + -- assign outputs + eol <= Hdone; + igate <= Hgate and Vgate; + gate <= igate; + + Hsync <= iHsync xor HsyncL; + Vsync <= iVsync xor VsyncL; + Csync <= (iHsync or iVsync) xor CsyncL; + Blank <= igate xnor BlankL; +end architecture dataflow; + + Index: tags/rel_1/rtl/vhdl/vga.vhd =================================================================== --- tags/rel_1/rtl/vhdl/vga.vhd (nonexistent) +++ tags/rel_1/rtl/vhdl/vga.vhd (revision 42) @@ -0,0 +1,319 @@ +-- +-- file: vga.vhd +-- project: VGA/LCD controller +-- author: Richard Herveille +-- +-- rev 1.0 May 10th, 2001 +-- rev 1.1 June 3th, 2001. Changed WISHBONE addresses. Addresses are byte oriented, instead of databus-independent +-- rev 1.2 June 29th, 2001. Many hanges in design to reflect changes in fifo's. Design now correctly maps to Xilinx-BlockRAMs. +-- rev 1.3 July 15th, 2001. Added CLUT bank switching + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity VGA is + port ( + CLK_I : in std_logic; + RST_I : in std_logic; + NRESET : in std_logic; + INTA_O : out std_logic; + + -- slave signals + ADR_I : in unsigned(4 downto 2); -- only 32bit databus accesses supported + SDAT_I : in std_logic_vector(31 downto 0); + SDAT_O : out std_logic_vector(31 downto 0); + SEL_I : in std_logic_vector(3 downto 0); + WE_I : in std_logic; + STB_I : in std_logic; + CYC_I : in std_logic; + ACK_O : out std_logic; + ERR_O : out std_logic; + + -- master signals + ADR_O : out unsigned(31 downto 2); + MDAT_I : in std_logic_vector(31 downto 0); + SEL_O : out std_logic_vector(3 downto 0); + WE_O : out std_logic; + STB_O : out std_logic; + CYC_O : out std_logic; + CAB_O : out std_logic; + ACK_I : in std_logic; + ERR_I : in std_logic; + + -- VGA signals + PCLK : in std_logic; -- pixel clock + HSYNC : out std_logic; -- horizontal sync + VSYNC : out std_logic; -- vertical sync + CSYNC : out std_logic; -- composite sync + BLANK : out std_logic; -- blanking signal + R,G,B : out std_logic_vector(7 downto 0) -- RGB color signals + ); +end entity vga; + +architecture dataflow of vga is + -- + -- components + -- + + -- dual clock-fifo. Change the dual-port memory section, depending on the target technology + component FIFO_DC is + generic( + DEPTH : natural := 128; + DWIDTH : natural := 32 + ); + port( + rclk : in std_logic; -- read clock input + wclk : in std_logic; -- write clock input + aclr : in std_logic := '1'; -- active low asynchronous clear + + D : in std_logic_vector(DWIDTH -1 downto 0); -- Data input + wreq : in std_logic; -- write request + + Q : out std_logic_vector(DWIDTH -1 downto 0); -- Data output + rreq : in std_logic; -- read request + + rd_empty, -- FIFO is empty, synchronous to read clock + rd_full, -- FIFO is full, synchronous to read clock + wr_empty, -- FIFO is empty, synchronous to write clock + wr_full : out std_logic -- FIFO is full, synchronous to write clock + ); + end component FIFO_DC; + + -- WISHBONE slave block + component wb_slave is + port ( + CLK_I : in std_logic; + RST_I : in std_logic; + NRESET : in std_logic; + ADR_I : in unsigned(4 downto 2); + DAT_I : in std_logic_vector(31 downto 0); + DAT_O : out std_logic_vector(31 downto 0); + SEL_I : in std_logic_vector(3 downto 0); + WE_I : in std_logic; + STB_I : in std_logic; + CYC_I : in std_logic; + ACK_O : out std_logic; + ERR_O : out std_logic; + INTA_O : out std_logic; + + -- control register settings + BL : out std_logic; -- blanking level + CSL : out std_logic; -- composite sync level + VSL : out std_logic; -- vsync level + HSL : out std_logic; -- hsync level + PC : out std_logic; -- pseudo color + CD : out std_logic_vector(1 downto 0); -- color depth + VBL : out std_logic_vector(1 downto 0); -- burst length + CBSW : out std_logic; -- clut bank switching enable + VBSW : out std_logic; -- video page bank switching enable + Ven : out std_logic; -- video system enable + + -- status register inputs + AVMP, -- active video memory page + ACMP : in std_logic; -- active clut page + bsint_in, + hint_in, + vint_in, + luint_in, + sint_in : in std_logic; -- interrupt request signals + + -- Horizontal Timing Register + Thsync : out unsigned(7 downto 0); + Thgdel : out unsigned(7 downto 0); + Thgate : out unsigned(15 downto 0); + Thlen : out unsigned(15 downto 0); + + -- Vertical Timing Register + Tvsync : out unsigned(7 downto 0); + Tvgdel : out unsigned(7 downto 0); + Tvgate : out unsigned(15 downto 0); + Tvlen : out unsigned(15 downto 0); + + VBARa, + VBARb : buffer unsigned(31 downto 2); + CBAR : buffer unsigned(31 downto 11) + ); + end component wb_slave; + + -- WISHBONE master block + component wb_master is + port( + -- WISHBONE signals + CLK_I : in std_logic; -- master clock input + RST_I : in std_logic; -- synchronous active high reset + nRESET : in std_logic; -- asynchronous active low reset + CYC_O : out std_logic; -- cycle output + STB_O : out std_logic; -- strobe output + CAB_O : out std_logic; -- Consecutive Address Burst output + WE_O : out std_logic; -- write enable output + ADR_O : out unsigned(31 downto 2); -- address output + SEL_O : out std_logic_vector(3 downto 0); -- Byte Select outputs (only 32bit accesses are supported) + ACK_I : in std_logic; -- WISHBONE cycle acknowledge signal + ERR_I : in std_logic; -- oops, bus-error + DAT_I : in std_logic_vector(31 downto 0); -- WISHBONE data in + + SINT : out std_logic; -- Non recoverable error, interrupt host + + -- control register settings + ctrl_Ven : in std_logic; -- video enable bit + ctrl_cd : in std_logic_vector(1 downto 0); -- color depth + ctrl_pc : in std_logic; -- 8bpp pseudo color/bw + ctrl_vbl : in std_logic_vector(1 downto 0); -- burst length + ctrl_vbsw : in std_logic; -- enable video bank switching + ctrl_cbsw : in std_logic; -- enable clut bank switching + + -- video memory addresses + VBAa, -- Video Memory Base Address-A + VBAb : in unsigned(31 downto 2); -- Video Memory Base Address-B + CBA : in unsigned(31 downto 11); -- CLUT Base Address Register + + Thgate : unsigned(15 downto 0); -- horizontal visible area (in pixels) + Tvgate : unsigned(15 downto 0); -- vertical visible area (in horizontal lines) + + stat_AVMP : out std_logic; -- active video memory page + stat_ACMP : out std_logic; -- active color lookup table + bs_req : out std_logic; -- bank-switch request: memory page switched (when enabled). bs_req is always generated + + -- to/from line fifo + line_fifo_wreq : out std_logic; + line_fifo_d : out std_logic_vector(23 downto 0); + line_fifo_full : in std_logic + ); + end component wb_master; + + -- pixel generator. Generates video and pixel timing. + component Pgen is + port( + mclk : in std_logic; -- master clock + pclk : in std_logic; -- pixel clock + + ctrl_Ven : in std_logic; -- VideoEnable signal + + -- horizontal timing settings + ctrl_HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg) + Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels) + Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels) + Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line) + Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line) + + -- vertical timing settings + ctrl_VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg) + Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines) + Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines) + Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame) + Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame) + + ctrl_CSyncL : in std_logic; -- composite sync pulse polarization level + ctrl_BlankL : in std_logic; -- blank signal polarization level + + -- status outputs + eoh, -- end of horizontal + eov, -- end of vertical + Gate : out std_logic; -- vertical AND horizontal gate (logical AND function) + + -- pixel control outputs + Hsync, -- horizontal sync pulse + Vsync, -- vertical sync pulse + Csync, -- composite sync: Hsync OR Vsync (logical OR function) + Blank : out std_logic -- blank signals + ); + end component Pgen; + + -- + -- signals + -- + + -- from wb_slave + signal ctrl_bl, ctrl_csl, ctrl_vsl, ctrl_hsl, ctrl_pc, ctrl_cbsw, ctrl_vbsw, ctrl_ven : std_logic; + signal ctrl_cd, ctrl_vbl : std_logic_vector(1 downto 0); + signal Thsync, Thgdel, Tvsync, Tvgdel : unsigned(7 downto 0); + signal Thgate, Thlen, Tvgate, Tvlen : unsigned(15 downto 0); + signal VBARa, VBARb : unsigned(31 downto 2); + signal CBAR : unsigned(31 downto 11); + + -- to wb_slave + signal stat_avmp, stat_acmp, bsint, hint, vint, luint, sint : std_logic; + + -- from wb_master + signal line_fifo_wreq : std_logic; + signal line_fifo_d : std_logic_vector(23 downto 0); + + -- from pixel generator + signal cgate : std_logic; -- composite gate signal + signal ihsync, ivsync, icsync, iblank : std_logic; -- intermediate horizontal/vertical/composite sync, intermediate blank +-- signal dhsync, dvsync, dcsync, dblank : std_logic; -- delayed intermedates (needed for fifo synchronization) + + -- from line fifo + signal line_fifo_full_wr, line_fifo_empty_rd : std_logic; + signal RGB : std_logic_vector(23 downto 0); +begin + + -- hookup wishbone slave + u1: wb_slave port map (CLK_I => CLK_I, RST_I => RST_I, nRESET => nRESET, ADR_I => ADR_I, DAT_I => SDAT_I, DAT_O => SDAT_O, + SEL_I => SEL_I, WE_I => WE_I, STB_I => STB_I, CYC_I => CYC_I, ACK_O => ACK_O, ERR_O => ERR_O, INTA_O => INTA_O, + BL => ctrl_bl, csl => ctrl_csl, vsl => ctrl_vsl, hsl => ctrl_hsl, pc => ctrl_pc, cd => ctrl_cd, vbl => ctrl_vbl, + cbsw => ctrl_cbsw, vbsw => ctrl_vbsw, ven => ctrl_ven, acmp => stat_acmp, avmp => stat_avmp, bsint_in => bsint, + hint_in => hint, vint_in => vint, luint_in => luint, sint_in => sint, Thsync => Thsync, Thgdel => Thgdel, + Thgate => Thgate, Thlen => Thlen, Tvsync => Tvsync, Tvgdel => Tvgdel, Tvgate => Tvgate, Tvlen => Tvlen, + VBARa => VBARa, VBARb => VBARb, CBAR => CBAR); + + -- hookup wishbone master + u2: wb_master port map (CLK_I => CLK_I, RST_I => RST_I, nReset => nReset, CYC_O => CYC_O, STB_O => STB_O, CAB_O => CAB_O, WE_O => WE_O, + ADR_O => ADR_O, SEL_O => SEL_O, ACK_I => ACK_I, ERR_I => ERR_I, DAT_I => MDAT_I, SINT => sint, + ctrl_Ven => ctrl_ven, ctrl_cd => ctrl_cd, ctrl_pc => ctrl_pc, ctrl_vbl => ctrl_vbl, ctrl_cbsw => ctrl_cbsw, ctrl_vbsw => ctrl_vbsw, + VBAa => VBARa, VBAb => VBARb, CBA => CBAR, Thgate => Thgate, Tvgate => Tvgate, stat_acmp => stat_acmp, stat_AVMP => stat_avmp, + bs_req => bsint, line_fifo_wreq => line_fifo_wreq, line_fifo_d => line_fifo_d, line_fifo_full => line_fifo_full_wr); + + -- hookup pixel and video timing generator + u3: pgen port map (mclk => CLK_I, pclk => pclk, ctrl_Ven => ctrl_ven, + ctrl_HSyncL => ctrl_hsl, Thsync => Thsync, Thgdel => Thgdel, Thgate => Thgate, Thlen => Thlen, ctrl_VSyncL => ctrl_vsl, + Tvsync => Tvsync, Tvgdel => Tvgdel, Tvgate => Tvgate, Tvlen => Tvlen, ctrl_CSyncL => ctrl_csl, ctrl_BlankL => ctrl_bl, + eoh => hint, eov => vint, gate => cgate, Hsync => ihsync, Vsync => ivsync, Csync => icsync, Blank => iblank); + + -- delay video control signals 1 clock cycle (dual clock fifo synchronizes output) + del_video_sigs: process(pclk) + begin + if (pclk'event and pclk = '1') then + HSYNC <= ihsync; + VSYNC <= ivsync; + CSYNC <= icsync; + BLANK <= iblank; + end if; + end process del_video_sigs; + + -- hookup line-fifo + u4: FIFO_DC generic map (DEPTH => 256, DWIDTH => 24) + port map (rclk => pclk, wclk => CLK_I, aclr => ctrl_Ven, D => line_fifo_d, wreq => line_fifo_wreq, + q => RGB, rreq => cgate, rd_empty => line_fifo_empty_rd, wr_full => line_fifo_full_wr); + R <= RGB(23 downto 16); + G <= RGB(15 downto 8); + B <= RGB(7 downto 0); + + -- generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt) + luint_blk: block + signal luint_pclk, sluint : std_logic; + begin + gen_luint_pclk: process(pclk) + begin + if (pclk'event and pclk = '1') then + luint_pclk <= cgate and line_fifo_empty_rd; + end if; + end process gen_luint_pclk; + + process(CLK_I) + begin + if(CLK_I'event and CLK_I = '1') then + sluint <= luint_pclk; -- resample at CLK_I clock + luint <= sluint; -- sample again, reduce metastability risk + end if; + end process; + end block luint_blk; + +end architecture dataflow; + + + + + + Index: tags/rel_1/bench/verilog/tests.v =================================================================== --- tags/rel_1/bench/verilog/tests.v (nonexistent) +++ tags/rel_1/bench/verilog/tests.v (revision 42) @@ -0,0 +1,1291 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Tests Library //// +//// //// +//// //// +//// Authors: Rudolf Usselmann, Richard Herveille //// +//// rudi@asics.ws, richard@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: tests.v,v 1.5 2002-04-20 09:57:55 rherveille Exp $ +// +// $Date: 2002-04-20 09:57:55 $ +// $Revision: 1.5 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + + +task show_errors; + +begin + +$display("\n"); +$display(" +--------------------+"); +$display(" | Total ERRORS: %0d |", error_cnt); +$display(" +--------------------+"); + +end +endtask + + +task reg_test; + +reg [31:0] data; +reg [31:0] pattern; +integer n; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** Register Test ***"); +$display("*****************************************************\n"); + + // Check reset Values + $display("Testing Reset Values ..."); + check( `CTRL, 0, 32'h0000_ffff, "CTRL "); + check( `STAT, 0, 32'h0000_0073, "STAT "); + check( `HTIM, 0, 32'hffff_ffff, "HTIM "); + check( `VTIM, 0, 32'hffff_ffff, "VTIM "); + check( `HVLEN, 0, 32'hffff_ffff, "HVLEN"); + check( `VBARA, 0, 32'hffff_ffff, "VBARA"); + check( `VBARB, 0, 32'hffff_ffff, "VBARB"); + + $display("Testing Pattern R/W ..."); +for(n=0;n<6;n=n+1) + begin + case(n) + 0: pattern = 32'h0000_0000; + 1: pattern = 32'hffff_ffff; + 2: pattern = 32'haaaa_aaaa; + 3: pattern = 32'h5555_5555; + 4: pattern = 32'hcccc_cccc; + 5: pattern = 32'h3333_3333; + endcase + + m0.wb_wr1( `CTRL, 4'hf, pattern ); + check( `CTRL, pattern, 32'h0000_ffff, "CTRL "); + + m0.wb_wr1( `HTIM, 4'hf, pattern ); + check( `HTIM, pattern, 32'hffff_ffff, "HTIM "); + + m0.wb_wr1( `VTIM, 4'hf, pattern ); + check( `VTIM, pattern, 32'hffff_ffff, "VTIM "); + + m0.wb_wr1( `HVLEN, 4'hf, pattern ); + check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN"); + + m0.wb_wr1( `VBARA, 4'hf, pattern ); + check( `VBARA, pattern, 32'hffff_fffc, "VBARA"); + + m0.wb_wr1( `VBARB, 4'hf, pattern ); + check( `VBARB, pattern, 32'hffff_fffc, "VBARB"); + + end + +repeat(10) @(posedge clk); + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + + +task check; +input [31:0] addr; +input [31:0] edata; +input [31:0] mask; +input [39:0] name; + +reg [31:0] data; +begin + +m0.wb_rd1( addr, 4'hf, data ); +if(( (data & mask) != (edata & mask)) | ((^data) === 1'bx) ) + begin + $display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)", + name, edata & mask, data, $time); + error_cnt = error_cnt + 1; + end + +end +endtask + + + + +task tim_test; + +integer mode; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** Timing Test ***"); +$display("*****************************************************\n"); + + s0.fill_mem(0); + + repeat(10) @(posedge clk); + + m0.wb_wr1( `VBARA, 4'hf, 0 ); + m0.wb_wr1( `VBARB, 4'hf, 0 ); + m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000); + repeat(10) @(posedge clk); +mode = 4; + +for(mode=0;mode<6;mode=mode+1) + begin + scen = 0; + $display("Mode: %0d", mode); + + case(mode) + 0: + begin + thsync = 0; + thgdel = 0; + thgate = 340; + thlen = 345; + + tvsync = 0; + tvgdel = 0; + tvgate = 240; + tvlen = 245; + + hpol = 0; + vpol = 0; + cpol = 0; + bpol = 0; + end + + 1: + begin + thsync = 18; + thgdel = 18; + thgate = 340; + thlen = 390; + + tvsync = 18; + tvgdel = 18; + tvgate = 240; + tvlen = 290; + + hpol = 1; + vpol = 0; + cpol = 0; + bpol = 0; + end + + 2: + begin + thsync = 1; + thgdel = 1; + thgate = 640; + thlen = 643; + + tvsync = 1; + tvgdel = 1; + tvgate = 480; + tvlen = 483; + + hpol = 0; + vpol = 1; + cpol = 0; + bpol = 0; + end + + 3: + begin + thsync = 0; + thgdel = 2; + thgate = 800; + thlen = 804; + + tvsync = 0; + tvgdel = 2; + tvgate = 600; + tvlen = 604; + + hpol = 0; + vpol = 0; + cpol = 1; + bpol = 0; + end + + 4: + begin + thsync = 3; + thgdel = 2; + thgate = 800; + thlen = 806; + + tvsync = 2; + tvgdel = 2; + tvgate = 600; + tvlen = 606; + + hpol = 0; + vpol = 0; + cpol = 0; + bpol = 1; + end + + 5: + begin + thsync = 6; + thgdel = 2; + thgate = 800; + thlen = 810; + + tvsync = 4; + tvgdel = 2; + tvgate = 600; + tvlen = 607; + + hpol = 1; + vpol = 1; + cpol = 1; + bpol = 1; + end + endcase + +/* + thsync = 0; + thgdel = 0; + thgate = 64; + thlen = 70; + + tvsync = 0; + tvgdel = 0; + tvgate = 64; + tvlen = 70; + + hpol = 0; + vpol = 0; + cpol = 0; + bpol = 0; +*/ + + + m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); + m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); + m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); + m0.wb_wr1( `CTRL, 4'hf, { + 16'h0, + bpol, cpol, + vpol, hpol, + 1'b0, // PC + 2'h0, // CD + 2'h0, // VBL + 2'h0, // Reserved + 5'h01 // Bank Switch, INT, VideoEn + }); + + repeat(2) @(posedge vsync); + scen = 1; + repeat(4) @(posedge vsync); + end + +scen = 0; +repeat(10) @(posedge clk); + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + + + +task pd1_test; + +integer mode; +integer n, p, l; +reg [31:0] pn; +reg [31:0] pra, paa, tmp; +reg [23:0] pd; +reg [1:0] cd; +reg pc; +reg [31:0] data; +reg [31:0] cbar; +reg [7:0] vbl; + +begin + +$display("\n\n"); +$display("*****************************************************"); +$display("*** Pixel Data Test 1 ***"); +$display("*****************************************************\n"); + + m0.wb_wr1( `VBARA, 4'hf, 0 ); + m0.wb_wr1( `VBARB, 4'hf, 123456 ); + + cbar = 32'h0000_0800; + + thsync = 0; + thgdel = 0; + thgate = 320; + thlen = 345; + + tvsync = 0; + tvgdel = 0; + tvgate = 240; + tvlen = 245; + + thsync = 39; + thgdel = 124; + thgate = 646; + thlen = 832; + + tvsync = 2; + tvgdel = 25; + tvgate = 484; + tvlen = 520; + + thsync = 6; + thgdel = 20; + thgate = 319; + thlen = 390; + + tvsync = 1; + tvgdel = 8; + tvgate = 239; + tvlen = 280; + +/* + thsync = 0; + thgdel = 0; + thgate = 63; + thlen = 70; + + tvsync = 0; + tvgdel = 0; + tvgate = 32; + tvlen = 36; + + thsync = 119; + thgdel = 61; + thgate = 805; + thlen = 1038; + + tvsync = 5; + tvgdel = 20; + tvgate = 600; + tvlen = 665; + +*/ + + hpol = 0; + vpol = 0; + cpol = 0; + bpol = 0; + + m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); + m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); + m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); + +mode = 2; +vbl = 0; + +for(vbl=0;vbl<4;vbl=vbl+1) +for(mode=0;mode<4;mode=mode+1) + begin + + // ------------------------------- + // Turn Off VGA before Mode Change + + m0.wb_wr1( `CTRL, 4'hf, { + 16'h0, // Reserved + bpol, cpol, + vpol, hpol, + pc, // 1'b0, // PC + cd, // 2'h2, // CD + 2'h0, // VBL + 1'b0, // CBSWE + 1'b0, // VBSWE + 1'b0, // CBSIE + 1'b0, // VBSIE + 1'b0, // HIE + 1'b0, // VIE + 1'b0 // Video Enable + }); + + s0.fill_mem(1); + +`ifdef USE_VC +// Fill internal Color Lookup Table +repeat(10) @(posedge clk); +for(n=0;n<512;n=n+1) + begin + //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data ); + data = s0.mem[ cbar[31:2] + n]; + m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data ); + end +repeat(10) @(posedge clk); +`endif + + case(mode) + 0: + begin + cd = 2'h2; + pc = 1'b0; + end + 1: + begin + cd = 2'h0; + pc = 1'b0; + end + 2: + begin + cd = 2'h0; + pc = 1'b1; + end + 3: + begin + cd = 2'h1; + pc = 1'b0; + end + endcase + + //repeat(50) @(posedge clk); + + // ------------------------------- + // Turn VGA back On ... + m0.wb_wr1( `CTRL, 4'hf, { + 16'h0, // Reserved + bpol, cpol, + vpol, hpol, + pc, // 1'b0, // PC + cd, // 2'h2, // CD + vbl[1:0], // VBL + 1'b0, // Reserved + 1'b0, // CBSWE + 1'b0, // VBSWE + 1'b0, // BSIE + 1'b0, // HIE + 1'b0, // VIE + 1'b1 // Video Enable + }); + + $display("VBL: %0d, Mode: %0d", vbl, mode); + repeat(2) @(posedge vsync); + + // For Each Line + for(l=0;l 10) $stop; + end + + @(posedge pclk); + + end + end +end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + + +task ur_test; + +integer mode; +integer n, p, l; +reg [31:0] pn; +reg [31:0] pra, paa, tmp; +reg [23:0] pd; +reg [1:0] cd; +reg pc; +reg [31:0] cbar; +reg [31:0] data; +reg [7:0] vbl; + +begin + +$display("\n\n"); +$display("*****************************************************"); +$display("*** FIFO Underrun Test 1 ***"); +$display("*****************************************************\n"); + + s0.delay=5; + int_warn = 0; + + m0.wb_wr1( `VBARA, 4'hf, 0 ); + m0.wb_wr1( `VBARB, 4'hf, 123456 ); + + cbar = 32'h0000_0800; + + thsync = 0; + thgdel = 0; + thgate = 340; + thlen = 345; + + tvsync = 0; + tvgdel = 0; + tvgate = 240; + tvlen = 245; + + thsync = 39; + thgdel = 124; + thgate = 646; + thlen = 832; + + tvsync = 2; + tvgdel = 25; + tvgate = 484; + tvlen = 520; + + thsync = 6; + thgdel = 20; + thgate = 319; + thlen = 390; + + tvsync = 1; + tvgdel = 8; + tvgate = 239; + tvlen = 280; + +/* + thsync = 0; + thgdel = 0; + thgate = 63; + thlen = 70; + + tvsync = 0; + tvgdel = 0; + tvgate = 32; + tvlen = 36; + + thsync = 119; + thgdel = 61; + thgate = 805; + thlen = 1038; + + tvsync = 5; + tvgdel = 20; + tvgate = 600; + tvlen = 665; + +*/ + + hpol = 0; + vpol = 0; + cpol = 0; + bpol = 0; + + m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); + m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); + m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); + + mode = 2; + + // ------------------------------- + // Turn Off VGA before Mode Change + + m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000); + + s0.fill_mem(1); + +`ifdef USE_VC +// Fill internal Color Lookup Table +repeat(10) @(posedge clk); +for(n=0;n<512;n=n+1) + begin + //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data ); + data = s0.mem[ cbar[31:2] + n]; + m0.wb_wr1( 32'h8000_0000 + (n*4), 4'hf, data ); + end +repeat(10) @(posedge clk); +`endif + + case(mode) + 0: + begin + cd = 2'h2; + pc = 1'b0; + end + 1: + begin + cd = 2'h0; + pc = 1'b0; + end + 2: + begin + cd = 2'h0; + pc = 1'b1; + end + 3: + begin + cd = 2'h1; + pc = 1'b0; + end + endcase + + // ------------------------------- + // Turn VGA back On ... + m0.wb_wr1( `CTRL, 4'hf, { + 16'h0, // Reserved + bpol, cpol, + vpol, hpol, + pc, // 1'b0, // PC + cd, // 2'h2, // CD + 2'b00, // VBL + 1'b0, // Reserved + 1'b0, // CBSWE + 1'b0, // VBSWE + 1'b0, // BSIE + 1'b0, // HIE + 1'b0, // VIE + 1'b1 // Video Enable + }); + + while(!int) @(posedge clk); + m0.wb_rd1( `STAT, 4'hf, data); + if(data[1] !== 1'b1) + begin + $display("ERROR: Did not get Line FIFO Interrupt. (%0t)", + $time); + end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000); +int_warn = 1; +s0.delay=1; +repeat(10) @(posedge clk); + +end +endtask + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: tags/rel_1/bench/verilog/wb_slv_model.v =================================================================== --- tags/rel_1/bench/verilog/wb_slv_model.v (nonexistent) +++ tags/rel_1/bench/verilog/wb_slv_model.v (revision 42) @@ -0,0 +1,157 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Slave Model //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_slv_model.v,v 1.2 2002-02-07 05:38:32 rherveille Exp $ +// +// $Date: 2002-02-07 05:38:32 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/21 05:42:32 rudi +// +// - Changed Directory Structure +// - Added verilog Source Code +// - Changed IO pin names and defines statements +// +// +// +// + +`include "wb_model_defines.v" + +module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +input [31:0] adr, din; +output [31:0] dout; +input cyc, stb; +input [3:0] sel; +input we; +output ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter mem_size = 13; +parameter sz = (1<9000) + begin + $display("\n\n*************************************\n"); + $display("ERROR: Watch Dog Counter Expired\n"); + $display("*************************************\n\n\n"); + $finish; + end + + +always @(posedge int) + if(int_warn) + begin + $display("\n\n*************************************\n"); + $display("WARNING: Recieved Interrupt (%0t)", $time); + $display("*************************************\n\n\n"); + end + +always #2.5 clk = ~clk; +always #(PCLK_C/2) pclk = ~pclk; + +assign clk_v = clk; + +///////////////////////////////////////////////////////////////////// +// +// WISHBONE DMA IP Core +// + + +// Module Prototype + +`ifdef USE_VC +vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 ( + .wb_clk_i( clk ), + .wb_rst_i( 1'b0 ), + .rst_i( rst ), + .wb_inta_o( int ), + + //-- slave signals + .wbs_adr_i( wb_addr_i[11:0] ), + .wbs_dat_i( wb_data_i ), + .wbs_dat_o( wb_data_o ), + .wbs_sel_i( wb_sel_i ), + .wbs_we_i( wb_we_i ), + .wbs_stb_i( wb_stb_i ), + .wbs_cyc_i( wb_cyc_i ), + .wbs_ack_o( wb_ack_o ), + .wbs_err_o( wb_err_o ), + + //-- master signals + .wbm_adr_o( wb_addr_o[31:0] ), + .wbm_dat_i( wbm_data_i ), + .wbm_sel_o( wb_sel_o ), + .wbm_we_o( wb_we_o ), + .wbm_stb_o( wb_stb_o ), + .wbm_cyc_o( wb_cyc_o ), + .wbm_cab_o( ), + .wbm_ack_i( wb_ack_i ), + .wbm_err_i( wb_err_i ), + + //-- VGA signals + .clk_p_i( pclk ), + .hsync_pad_o( hsync ), + .vsync_pad_o( vsync ), + .csync_pad_o( csync ), + .blank_pad_o( blanc ), + .r_pad_o( red ), + .g_pad_o( green ), + .b_pad_o( blue ) + ); + +`else + +VGA u0 ( .CLK_I( clk_v ), + .RST_I( ~rst ), + .NRESET( rst ), + .INTA_O( int ), + + //-- slave signals + .ADR_I( wb_addr_i[4:2] ), + .SDAT_I( wb_data_i ), + .SDAT_O( wb_data_o ), + .SEL_I( wb_sel_i ), + .WE_I( wb_we_i ), + .STB_I( wb_stb_i ), + .CYC_I( wb_cyc_i ), + .ACK_O( wb_ack_o ), + .ERR_O( wb_err_o ), + + //-- master signals + .ADR_O( wb_addr_o[31:2] ), + .MDAT_I( wbm_data_i ), + .SEL_O( wb_sel_o ), + .WE_O( wb_we_o ), + .STB_O( wb_stb_o ), + .CYC_O( wb_cyc_o ), + .CAB_O( ), + .ACK_I( wb_ack_i ), + .ERR_I( wb_err_i ), + + //-- VGA signals + .PCLK( pclk ), + .HSYNC( hsync ), + .VSYNC( vsync ), + .CSYNC( csync ), + .BLANK( blanc ), + .R( red ), + .G( green ), + .B( blue ) + ); + +`endif + +wb_mast m0( .clk( clk ), + .rst( rst ), + .adr( wb_addr_i ), + .din( wb_data_o ), + .dout( wb_data_i ), + .cyc( wb_cyc_i ), + .stb( wb_stb_i ), + .sel( wb_sel_i ), + .we( wb_we_i ), + .ack( wb_ack_o ), + .err( wb_err_o ), + .rty( 1'b0 ) + ); + +wb_slv #(24) s0(.clk( clk ), + .rst( rst ), + .adr( {1'b0, wb_addr_o[30:0]} ), + .din( 32'h0 ), + .dout( wbm_data_i ), + .cyc( wb_cyc_o ), + .stb( wb_stb_o ), + .sel( wb_sel_o ), + .we( wb_we_o ), + .ack( wb_ack_i ), + .err( wb_err_i ), + .rty( ) + ); + +`include "tests.v" + +endmodule + +/* +module vdata_mon(clk, rst, hsync, vsync, blank, pixel, line); +input clk, rst; +input hsync, vsync, blank; +output [31:0] pixel, line; + +reg [31:0] pixel, line; + +always @(negedge blank) + line = line + 1; + +always @(posedge vsync or negedge rst) + line = -1; + +always @(posedge clk) + if(!blank) pixel = pixel + 1; + else pixel = 0; + +endmodule +*/ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: tags/rel_1/bench/verilog/sync_check.v =================================================================== --- tags/rel_1/bench/verilog/sync_check.v (nonexistent) +++ tags/rel_1/bench/verilog/sync_check.v (revision 42) @@ -0,0 +1,223 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Top Level Test Bench //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: sync_check.v,v 1.2 2001-11-15 07:04:15 rherveille Exp $ +// +// $Date: 2001-11-15 07:04:15 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// + +`timescale 1ns / 10ps + +module sync_check( pclk, rst, enable, hsync, vsync, csync, blanc, + hpol, vpol, cpol, bpol, + thsync, thgdel, thgate, thlen, + tvsync, tvgdel, tvgate, tvlen); + +input pclk, rst, enable, hsync, vsync, csync, blanc; +input hpol, vpol, cpol, bpol; +input [7:0] thsync, thgdel; +input [15:0] thgate, thlen; +input [7:0] tvsync, tvgdel; +input [15:0] tvgate, tvlen; + + +time last_htime; +reg hvalid; +time htime; +time hhtime; + +time last_vtime; +reg vvalid; +time vtime; +time vhtime; + +wire [31:0] htime_exp; +wire [31:0] hhtime_exp; +wire [31:0] vtime_exp; +wire [31:0] vhtime_exp; + +wire hcheck; +wire vcheck; + +wire [31:0] bh_start; +wire [31:0] bh_end; +wire [31:0] bv_start; +wire [31:0] bv_end; + +integer bdel1; +reg bval1; +reg bval; +integer bdel2; +wire bcheck; + +//initial hvalid=0; +//initial vvalid=0; + +parameter clk_time = 40; + +assign hcheck = enable; +assign vcheck = enable; +assign hhtime_exp = (thsync + 1) * clk_time; +assign htime_exp = (thlen + 2) * clk_time; +assign vhtime_exp = (htime_exp * (tvsync + 1)); +assign vtime_exp = htime_exp * (tvlen+2); + +always @(posedge pclk) + if(!rst | !enable) + begin + hvalid = 0; + vvalid = 0; + end + +// Verify HSYNC Timing +always @(hsync) + if(hcheck) + begin + if(hsync == ~hpol) + begin + htime = $time - last_htime; + //if(hvalid) $display("HSYNC length time: %0t", htime); + if(hvalid & (htime != htime_exp)) + $display("HSYNC length ERROR: Expected: %0d Got: %0d (%0t)", + htime_exp, htime, $time); + last_htime = $time; + hvalid = 1; + end + + if(hsync == hpol) + begin + hhtime = $time - last_htime; + //if(hvalid) $display("HSYNC pulse time: %0t", hhtime); + if(hvalid & (hhtime != hhtime_exp)) + $display("HSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)", + hhtime_exp, hhtime, $time); + end + end + + +// Verify VSYNC Timing +always @(vsync) + if(vcheck) + begin + if(vsync == ~vpol) + begin + vtime = $time - last_vtime; + //if(vvalid) $display("VSYNC length time: %0t", vtime); + if(vvalid & (vtime != vtime_exp)) + $display("VSYNC length ERROR: Expected: %0d Got: %0d (%0t)", + vtime_exp, vtime, $time); + last_vtime = $time; + vvalid = 1; + end + + if(vsync == vpol) + begin + vhtime = $time - last_vtime; + //if(vvalid) $display("VSYNC pulse time: %0t", vhtime); + if(vvalid & (vhtime != vhtime_exp)) + $display("VSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)", + vhtime_exp, vhtime, $time); + end + end + +// Verify BLANC Timing +assign bv_start = tvsync + tvgdel + 2; +assign bv_end = bv_start + tvgate + 2; + +assign bh_start = thsync + thgdel + 1; +assign bh_end = bh_start + thgate + 2; + +assign bcheck = enable; + +always @(vsync) + if(vsync == ~vpol) + bdel1 = 0; + +always @(hsync) + if(hsync == ~hpol) + bdel1 = bdel1 + 1; + +always @(bdel1) + bval1 = (bdel1 > bv_start) & (bdel1 < bv_end); + +always @(hsync) + if(hsync == ~hpol) + bdel2 = 0; + +always @(posedge pclk) + bdel2 = bdel2 + 1; + +initial bval = 1; +always @(bdel2) + bval = #1 !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end)); + + +always @(bval or blanc) + #0.01 + if(enable) + if(((blanc ^ bpol) != bval) & bcheck) + $display("BLANK ERROR: Expected: %0d Got: %0d (%0t)", + bval, (blanc ^ bpol), $time); + +// verify CSYNC +always @(csync or vsync or hsync) + if(enable) + if( (csync ^ cpol) != ( (vsync ^ vpol) | (hsync ^ hpol) ) ) + $display("CSYNC ERROR: Expected: %0d Got: %0d (%0t)", + ( (vsync ^ vpol) | (hsync ^ hpol) ), (csync ^ cpol), $time); + + +endmodule + + + + + + + Index: tags/rel_1/bench/verilog/wb_mast_model.v =================================================================== --- tags/rel_1/bench/verilog/wb_mast_model.v (nonexistent) +++ tags/rel_1/bench/verilog/wb_mast_model.v (revision 42) @@ -0,0 +1,356 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Master Model //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_mast_model.v,v 1.1 2001-08-21 05:42:32 rudi Exp $ +// +// $Date: 2001-08-21 05:42:32 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// + +`include "wb_model_defines.v" + +module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +output [31:0] adr; +input [31:0] din; +output [31:0] dout; +output cyc, stb; +output [3:0] sel; +output we; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] adr; +reg [31:0] dout; +reg cyc, stb; +reg [3:0] sel; +reg we; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + //adr = 32'hxxxx_xxxx; + //adr = 0; + adr = 32'hffff_ffff; + dout = 32'hxxxx_xxxx; + cyc = 0; + stb = 0; + sel = 4'hx; + we = 1'hx; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + +//////////////////////////////////////////////////////////////////// +// +// Write 1 Word Task +// + +task wb_wr1; +input [31:0] a; +input [3:0] s; +input [31:0] d; + +begin + +@(posedge clk); +#1; +adr = a; +dout = d; +cyc = 1; +stb = 1; +we=1; +sel = s; + +@(posedge clk); +while(~ack) @(posedge clk); +#1; +cyc=0; +stb=0; +adr = 32'hxxxx_xxxx; +dout = 32'hxxxx_xxxx; +we = 1'hx; +sel = 4'hx; + +//@(posedge clk); +end +endtask + + +//////////////////////////////////////////////////////////////////// +// +// Write 4 Words Task +// + +task wb_wr4; +input [31:0] a; +input [3:0] s; +input delay; +input [31:0] d1; +input [31:0] d2; +input [31:0] d3; +input [31:0] d4; + +integer delay; + +begin + +@(posedge clk); +#1; +cyc = 1; +sel = s; + +repeat(delay) + begin + @(posedge clk); + #1; + end +adr = a; +dout = d1; +stb = 1; +we=1; +while(~ack) @(posedge clk); +#2; +stb=0; +we=1'bx; +dout = 32'hxxxx_xxxx; + + +repeat(delay) + begin + @(posedge clk); + #1; + end +stb=1; +adr = a+4; +dout = d2; +we=1; +@(posedge clk); +while(~ack) @(posedge clk); +#2; +stb=0; +we=1'bx; +dout = 32'hxxxx_xxxx; + +repeat(delay) + begin + @(posedge clk); + #1; + end +stb=1; +adr = a+8; +dout = d3; +we=1; +@(posedge clk); +while(~ack) @(posedge clk); +#2; +stb=0; +we=1'bx; +dout = 32'hxxxx_xxxx; + +repeat(delay) + begin + @(posedge clk); + #1; + end +stb=1; +adr = a+12; +dout = d4; +we=1; +@(posedge clk); +while(~ack) @(posedge clk); +#1; +stb=0; +cyc=0; + +adr = 32'hxxxx_xxxx; +dout = 32'hxxxx_xxxx; +we = 1'hx; +sel = 4'hx; + +end +endtask + + +//////////////////////////////////////////////////////////////////// +// +// Read 1 Word Task +// + +task wb_rd1; +input [31:0] a; +input [3:0] s; +output [31:0] d; + +begin + +@(posedge clk); +#1; +adr = a; +cyc = 1; +stb = 1; +we = 0; +sel = s; + +//@(posedge clk); +while(~ack) @(posedge clk); +d = din; +#1; +cyc=0; +stb=0; +//adr = 32'hxxxx_xxxx; +//adr = 0; +adr = 32'hffff_ffff; +dout = 32'hxxxx_xxxx; +we = 1'hx; +sel = 4'hx; + +end +endtask + + +//////////////////////////////////////////////////////////////////// +// +// Read 4 Words Task +// + + +task wb_rd4; +input [31:0] a; +input [3:0] s; +input delay; +output [31:0] d1; +output [31:0] d2; +output [31:0] d3; +output [31:0] d4; + +integer delay; +begin + +@(posedge clk); +#1; +cyc = 1; +we = 0; +sel = s; +repeat(delay) @(posedge clk); + +adr = a; +stb = 1; +while(~ack) @(posedge clk); +d1 = din; +#2; +stb=0; +we = 1'hx; +sel = 4'hx; +repeat(delay) + begin + @(posedge clk); + #1; + end +we = 0; +sel = s; + +adr = a+4; +stb = 1; +@(posedge clk); +while(~ack) @(posedge clk); +d2 = din; +#2; +stb=0; +we = 1'hx; +sel = 4'hx; +repeat(delay) + begin + @(posedge clk); + #1; + end +we = 0; +sel = s; + + +adr = a+8; +stb = 1; +@(posedge clk); +while(~ack) @(posedge clk); +d3 = din; +#2; +stb=0; +we = 1'hx; +sel = 4'hx; +repeat(delay) + begin + @(posedge clk); + #1; + end +we = 0; +sel = s; + +adr = a+12; +stb = 1; +@(posedge clk); +while(~ack) @(posedge clk); +d4 = din; +#1; +stb=0; +cyc=0; +we = 1'hx; +sel = 4'hx; +adr = 32'hffff_ffff; +end +endtask + + +endmodule Index: tags/rel_1/bench/verilog/wb_model_defines.v =================================================================== --- tags/rel_1/bench/verilog/wb_model_defines.v (nonexistent) +++ tags/rel_1/bench/verilog/wb_model_defines.v (revision 42) @@ -0,0 +1,57 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Model Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_model_defines.v,v 1.1 2001-08-21 05:42:32 rudi Exp $ +// +// $Date: 2001-08-21 05:42:32 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/03/19 13:12:48 rudi +// Initial Release +// +// +// + +//`timescale 1ns / 10ps +`timescale 1ns / 1ns Index: tags/rel_1/software/include/oc_vga_lcd.h =================================================================== --- tags/rel_1/software/include/oc_vga_lcd.h (nonexistent) +++ tags/rel_1/software/include/oc_vga_lcd.h (revision 42) @@ -0,0 +1,123 @@ +/* +///////////////////////////////////////////////////////////////////// +//// //// +//// Include file for OpenCores VGA/LCD Controller //// +//// //// +//// File : oc_vga_lcd.h //// +//// Function: c-include file //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) //// +//// www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +*/ + +/* + * Definitions for the Opencores VGA/LCD Controller Core + */ + +/* --- Register definitions --- */ + +/* ----- Read-write access */ + +#define OC_VGA_CTRL 0x000 /* Control register */ +#define OC_VGA_STAT 0x004 /* Status register */ +#define OC_VGA_HTIM 0x008 /* Horizontal Timing register */ +#define OC_VGA_VTIM 0x00c /* Vertical Timing register */ +#define OC_VGA_HVLEN 0x010 /* Horizontal/Vertical length register*/ +#define OC_VGA_VBARA 0x014 /* Video Base Address register A */ +#define OC_VGA_VBARB 0x018 /* Video Base Address register B */ + +/* ----- Bits definition */ + +/* ----- Control register */ + /* bits 31-16 are reserved */ +#define OC_VGA_BL (1<<15) /* Blank level bit: */ +#define OC_VGA_CSL (1<<14) /* Composite Sync. level bit */ +#define OC_VGA_VSL (1<<13) /* Vertical Sync. level bit */ +#define OC_VGA_HSL (1<<12) /* Horizontal Sync. level bit */ + /* 0 - Positive */ + /* 1 - Negative */ +#define OC_VGA_PC (1<<11) /* Pseudo Color (only for 8bpp mode) */ + /* 0 - 8bpp gray scale */ + /* 1 - 8bpp pseudo color */ +#define OC_VGA_CD (1<< 9) /* Color Depth */ + /* 00 - 8bits per pixel */ + /* 01 - 16bits per pixel */ + /* 10 - 24bits per pixel */ + /* 11 - reserved */ +#define OC_VGA_VBL (1<< 7) /* Video burst length */ + /* 00 - 1 cycle */ + /* 01 - 2 cycle */ + /* 10 - 4 cycle */ + /* 11 - 8 cycle */ +#define OC_VGA_CBSWE (1<<6) /* CLUT Bank Switch Enable bit */ +#define OC_VGA_VBSWE (1<<5) /* Video Bank Switch Enable bit */ +#define OC_VGA_CBSIE (1<<4) /* CLUT Bank Switch Interrupt enable */ +#define OC_VGA_VBSIE (1<<3) /* Video Bank Switch Interrupt enable */ +#define OC_VGA_HIE (1<<2) /* Horizontal Interrupt enable */ +#define OC_VGA_VIE (1<<1) /* Vertical Interrupt enable */ +#define OC_VGA_VEN (1<<0) /* Video Enable bit */ + /* 1 - Enabled */ + /* 0 - Disabled */ + +/* ----- Status register */ + /* bits 31-18 are reserved */ +#define OC_VGA_ACMP (1<<17) /* Active CLUT Memory Page */ +#define OC_VGA_AVMP (1<<16) /* Active Video Memory Page */ + /* bits 15-8 are reserved */ +#define OC_VGA_CBSINT (1<<7) /* CLUT Bank Switch Interrupt pending */ +#define OC_VGA_VBSINT (1<<6) /* Bank Switch Interrupt pending */ +#define OC_VGA_HINT (1<<5) /* Horizontal Interrupt pending */ +#define OC_VGA_VINT (1<<4) /* Vertical Interrupt pending */ + /* bits 3-2 are reserved */ +#define OC_VGA_LUINT (1<<1) /* LineFIFO Underrun interrupt pending*/ +#define OC_VGA_SINT (1<<0) /* System Error Interrupt pending */ + + +/* ----- Horizontal/Vertical Timing registers */ + +#define OC_VGA_TSYNC (1<<24) /* Synchronization pulse width */ +#define OC_VGA_TGDEL (1<<16) /* Gate delay time */ +#define OC_VGA_TGATE (1<< 0) /* Gate time */ + + +/* ----- Horizontal and Vertcial Length registers */ + +#define OC_VGA_THLEN (1<<16) /* Horizontal length */ +#define OC_VGA_TVLEN (1<< 0) /* Vertical length */ + + +/* bit testing and setting macros */ + +#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) +#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) +#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) +#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) +#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) +#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file Index: tags/rel_1/sim/rtl_sim/bin/Makefile =================================================================== --- tags/rel_1/sim/rtl_sim/bin/Makefile (nonexistent) +++ tags/rel_1/sim/rtl_sim/bin/Makefile (revision 42) @@ -0,0 +1,155 @@ + +all: sim +SHELL = /bin/sh +#MS="-s" + +########################################################################## +# +# DUT Sources +# +########################################################################## +DUT_SRC_DIR=../../../rtl/verilog +_TARGETS_= $(DUT_SRC_DIR)/ro_cnt.v \ + $(DUT_SRC_DIR)/ud_cnt.v \ + $(DUT_SRC_DIR)/vga_vga_and_clut.v \ + $(DUT_SRC_DIR)/vga_top.v \ + $(DUT_SRC_DIR)/vga_csm_pb.v \ + $(DUT_SRC_DIR)/vga_fifo_dc.v \ + $(DUT_SRC_DIR)/vga_fifo.v \ + $(DUT_SRC_DIR)/vga_vtim.v \ + $(DUT_SRC_DIR)/vga_pgen.v \ + $(DUT_SRC_DIR)/vga_colproc.v \ + $(DUT_SRC_DIR)/vga_tgen.v \ + $(DUT_SRC_DIR)/vga_wb_master.v \ + $(DUT_SRC_DIR)/vga_wb_slave.v + + +########################################################################## +# +# Test Bench Sources +# +########################################################################## +TB_SRC_DIR=../../../bench/verilog +_TB_=" $(TB_SRC_DIR)/test_bench_top.v \ + $(TB_SRC_DIR)/wb_slv_model.v \ + $(TB_SRC_DIR)/wb_mast_model.v \ + $(TB_SRC_DIR)/sync_check.v \ + $(DUT_SRC_DIR)/vga_dpm.v \ + " + +########################################################################## +# +# Misc Variables +# +########################################################################## + +_TOP_=test +INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" +LOGF=-LOGFILE .nclog +NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT +UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v +GATE_NETLIST=../../../syn/out/vga_vga_and_clut_ps.v + +########################################################################## +# +# Make Targets +# +########################################################################## +simw: + @$(MAKE) -s sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES" + +ss: + signalscan -do waves/waves.do -waves waves/waves.trn & + +sim: + @echo "" + @echo "----- Running NCVLOG ... ----------" + @$(MAKE) $(MS) vlog \ + TARGETS="$(_TARGETS_)" \ + TB=$(_TB_) \ + INCDIR=$(INCDIR) \ + WAVES="$(WAVES)" \ + TOP=test + @echo "" + @echo "----- Running NCELAB ... ----------" + @$(MAKE) $(MS) elab \ + ACCESS="$(ACCESS)" TOP=$(_TOP_) + @echo "" + @echo "----- Running NCSIM ... ----------" + @$(MAKE) $(MS) ncsim \ + TOP=test + @echo "" + + +gatew: + @$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" + +gate: + @echo "" + @echo "----- Running NCVLOG ... ----------" + $(MAKE)$(MS) vlog \ + TARGETS="$(UMC_LIB) $(GATE_NETLIST)" \ + TB=$(_TB_) \ + INCDIR=$(INCDIR) \ + WAVES="$(WAVES)" + @echo "" + @echo "----- Running NCELAB ... ----------" + @$(MAKE) $(MS) elab \ + ACCESS="$(ACCESS)" TOP=$(_TOP_) + @echo "" + @echo "----- Running NCSIM ... ----------" + @$(MAKE) $(MS) ncsim TOP=$(_TOP_) + @echo "" + + +hal: + @echo "" + @echo "----- Running HAL ... ----------" + hal +incdir+$(DUT_SRC_DIR) \ + -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ + $(_TARGETS_) + @echo "----- DONE ... ----------" + +clean: + rm -rf ./waves/*.dsn ./waves/*.trn \ + ncwork/work/* ncwork/count/* \ + ncwork/work/.i* ncwork/count/.i* + +########################################################################## +# +# NCVLOG +# +########################################################################## + +vhdl: + ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK count -V93 $(DUT_SRC_DIR)/counter.vhd + ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK work -V93 $(TARGETS) + +vlog: + ncvlog $(NCCOMMON) $(LOGF) \ + -WORK work $(WAVES) $(TARGETS) $(TB) $(INCDIR) + +########################################################################## +# +# NCELAB +# +########################################################################## + +elab: + ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK work $(ACCESS) \ + work.$(TOP) + +########################################################################## +# +# NCSIM +# +########################################################################## + +ncsim: + ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -EXIT -ERRORMAX 10 work.$(TOP) + +

tags/rel_1/sim/rtl_sim/bin/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_1/syn/bin/read.dc =================================================================== --- tags/rel_1/syn/bin/read.dc (nonexistent) +++ tags/rel_1/syn/bin/read.dc (revision 42) @@ -0,0 +1,66 @@ +############################################################################### +# +# Pre Synthesis Script +# +# This script only reads in the design and saves it in a DB file +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_pre.log" +append pre_comp_db_file ../out/$design_name "_pre.db" + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Analyzing all design files ..." >> $log_file + +foreach module $design_files { + echo "+++++++++ Reading: $module" >> $log_file + echo +++++++++ Reading: $module + set module_file_name "" + append module_file_name $module ".v" + analyze -f verilog $module_file_name >> $log_file + elaborate $module >> $log_file + } + +current_design $active_design + +echo "+++++++++ Linking Design ..." >> $log_file +link >> $log_file + +echo "+++++++++ Uniquifying Design ..." >> $log_file +uniquify >> $log_file + +echo "+++++++++ Checking Design ..." >> $log_file +check_design >> $log_file + +# ============================================== +# Save Design +echo "+++++++++ Saving Design ..." >> $log_file +write_file -hierarchy -format db -output $pre_comp_db_file + Index: tags/rel_1/syn/bin/comp.dc =================================================================== --- tags/rel_1/syn/bin/comp.dc (nonexistent) +++ tags/rel_1/syn/bin/comp.dc (revision 42) @@ -0,0 +1,134 @@ +############################################################################### +# +# Actual Synthesis Script +# +# This script does the actual synthesis +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_cmp.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +append post_comp_db_file ../out/$design_name ".db" +append post_syn_verilog_file ../out/$design_name "_ps.v" +set junk_file /dev/null + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Reading Design ..." >> $log_file +read_file $pre_comp_db_file >> $log_file + +# ============================================== +# Operating conditions + +echo "+++++++++ Setting up Operation Conditions ..." >> $log_file +current_design $design_name +set_operating_conditions WORST >> $log_file + +# Turn off automatic wire load selection, as this +# always (WHY ???) defaults to "zero_load" +#set auto_wire_load_selection false +#set_wire_load_mode enclosed >> $log_file +#set_wire_load_mode top >> $log_file +#set_wire_load_model -name suggested_40K >> $log_file + +# ============================================== +# Setup Clocks and Resets + +echo "+++++++++ Setting up Clocks ..." >> $log_file + +set_drive 0 wb_clk_i +set_drive 0 clk_pclk_i + +# !!! WISHBONE Clock !!! +set clock_period 5 +create_clock -period $clock_period wb_clk_i +set_clock_skew -uncertainty 0.1 wb_clk_i +set_clock_transition 0.5 wb_clk_i +set_dont_touch_network wb_clk_i + +# !!! Pixel Clock !!! +set clock_period2 20 +create_clock -period $clock_period2 clk_pclk_i +set_clock_skew -uncertainty 0.5 clk_pclk_i +set_clock_transition 0.9 clk_pclk_i +set_dont_touch_network clk_pclk_i + +# !!! Reset !!! +set_drive 0 wb_rst_i +set_dont_touch_network wb_rst_i +set_drive 0 rst_nreset_i +set_dont_touch_network rst_nreset_i + +# ============================================== +# Setup IOs + +echo "+++++++++ Setting up IOs ..." >> $log_file + +# Need to spell out external IOs + +set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file +set_load 0.2 [all_outputs] + +set_input_delay -max 2 -clock wb_clk_i [all_inputs] +set_output_delay -max 2 -clock wb_clk_i [all_outputs] + +set_input_delay -max 2 -clock clk_pclk_i [all_inputs] +set_output_delay -max 2 -clock clk_pclk_i [all_outputs] + +# ============================================== +# Setup Area Constrains +set_max_area 0.0 +set compile_sequential_area_recovery true + +# ============================================== +# Force Ultra +set_ultra_optimization -f + +# ============================================== +# Compile Design + +echo "+++++++++ Starting Compile ..." >> $log_file +#compile -map_effort low -area_effort low >> $log_file +compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file + +# ============================================== +# Write Out the optimized design + +echo "+++++++++ Saving Optimized Design ..." >> $log_file +write_file -hierarchy -format verilog -output $post_syn_verilog_file +write_file -hierarchy -format db -output $post_comp_db_file + +# ============================================== +# Create Some Basic Reports + +echo "+++++++++ Reporting Final Results ..." >> $log_file +report_timing -nworst 10 >> $log_file +report_area >> $log_file + + Index: tags/rel_1/syn/bin/lib_spec.dc =================================================================== --- tags/rel_1/syn/bin/lib_spec.dc (nonexistent) +++ tags/rel_1/syn/bin/lib_spec.dc (revision 42) @@ -0,0 +1,36 @@ +############################################################################### +# +# Library Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Libraries + +set search_path [list $search_path . \ + /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ + $hdl_src_dir] + +set snps [getenv "SYNOPSYS"] + +set synthetic_library "" +append synthetic_library $snps "/libraries/syn/dw01.sldb " +append synthetic_library $snps "/libraries/syn/dw02.sldb " +append synthetic_library $snps "/libraries/syn/dw03.sldb " +append synthetic_library $snps "/libraries/syn/dw04.sldb " +append synthetic_library $snps "/libraries/syn/dw05.sldb " +append synthetic_library $snps "/libraries/syn/dw06.sldb " +append synthetic_library $snps "/libraries/syn/dw07.sldb " + +set target_library { umcl18u250t2_typ.db } +set link_library "" +append link_library $target_library " " $synthetic_library +set symbol_library { umcl18u250t2.sdb } + Index: tags/rel_1/syn/bin/design_spec.dc =================================================================== --- tags/rel_1/syn/bin/design_spec.dc (nonexistent) +++ tags/rel_1/syn/bin/design_spec.dc (revision 42) @@ -0,0 +1,27 @@ +############################################################################### +# +# Design Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters + +set design_files {ud_cnt ro_cnt vga_fifo_dc vga_fifo vga_colproc vga_vtim vga_pgen vga_wb_master vga_tgen vga_wb_slave vga_csm_pb vga_top vga_vga_and_clut} + + +set design_name vga_vga_and_clut +set active_design vga_vga_and_clut + +# Next Statement defines all clocks and resets in the design +set special_net {rst clk_i pclk} + +set hdl_src_dir ../../rtl/verilog/ +

Browse

Tools

Subversion Repositories vga_lcd

Compare Revisions

Rev 41 → Rev 42