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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path
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    from Rev 415 to Rev 416
    Reverse comparison

Rev 415 → Rev 416

/trunk/or1ksim/cpu/or32/execute.c
388,6 → 388,8
is not called from anywhere else in the code. I have
placed it here for safety. CZ 21/06/01 */
 
// SIMON
pc_phy = translate_vrt_to_phy_add(pc);
PrepareException(); /* Update the pc for pending exceptions */
 
/* MM: Check for breakpoint. This has to be done in fetch cycle,
449,10 → 451,11
pcnext = t_pcnext;
 
/* Simulate instruction cache and IMMU. */
pc_phy = translate_vrt_to_phy_add(pc);
/* pc_phy = translate_vrt_to_phy_add(pc);
if(!verify_memoryarea(pc_phy))
except_handle(EXCEPT_BUSERR, pc);
*/
}
 
/* Added by CZ on 27/05/01 */
845,6 → 848,8
pcdelay = eval_operand32(0, &breakpoint);
next_delay_insn = 1;
}
// SIMON
#if 0
void l_rfe() {
cur->func_unit = exception;
pcdelay = mfspr(SPR_EPCR_BASE);
853,6 → 858,13
if (temp_disable_except == 0)
temp_disable_except = 1;
}
#else
void l_rfe() {
cur->func_unit = exception;
pcnext = mfspr(SPR_EPCR_BASE);
mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
}
#endif
void l_nop() {
cur->func_unit = nop;
if (nop_period > nop_maxperiod)
/trunk/or1ksim/cpu/common/abstract.c
267,7 → 267,8
struct dev_memarea *dev;
 
slp_checkaccess(memaddr, SLP_MEMREAD);
memaddr = simulate_ic_mmu_fetch(memaddr);
// memaddr = simulate_ic_mmu_fetch(memaddr);
ic_simulate_fetch(memaddr);
if (DEBUG_ENABLED)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
temp = evalsim_mem32(memaddr);
/trunk/or1ksim/mmu/immu.c
151,7 → 151,6
int minway = 0;
 
immu_stats.fetch_tlbmiss++;
cont_run=0;
#if 0
for (i = 0; i < ITLB_WAYS; i++)
if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru)

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