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/trunk/tx_engine/debug_pause.do File deleted

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/trunk/tx_engine/transmit.doc

trunk/tx_engine/transmit.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/tx_engine/TransmitTop.mpf =================================================================== --- trunk/tx_engine/TransmitTop.mpf (revision 42) +++ trunk/tx_engine/TransmitTop.mpf (nonexistent) @@ -1,376 +0,0 @@ -; -; Copyright Model Technology, a Mentor Graphics Corporation company 2003, -; All rights reserved. -; -[Library] -std = $MODEL_TECH/../std -ieee = $MODEL_TECH/../ieee -verilog = $MODEL_TECH/../verilog -vital2000 = $MODEL_TECH/../vital2000 -std_developerskit = $MODEL_TECH/../std_developerskit -synopsys = $MODEL_TECH/../synopsys -modelsim_lib = $MODEL_TECH/../modelsim_lib - -UNISIMS_VER = C:\FPGAdv62PS\Modeltech\Xilinx_libs\unisims_ver -SIMPRIMS_VER = C:\FPGAdv62PS\Modeltech\Xilinx_libs\simprims_ver -XILINXCORELIB_VER = C:\FPGAdv62PS\Modeltech\Xilinx_libs\XilinxCoreLib_ver -UNISIM = C:\FPGAdv62PS\Modeltech\Xilinx_libs\unisim -SIMPRIM = C:\FPGAdv62PS\Modeltech\Xilinx_libs\simprim -XILINXCORELIB = C:\FPGAdv62PS\Modeltech\Xilinx_libs\XilinxCoreLib -work = work -[vcom] -; Turn on VHDL-1993 as the default. Default is off (VHDL-1987). -; VHDL93 = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explict enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = false - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -[vlog] - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn on `protect compiler directive processing. -; Default is to ignore `protect directives. -; Protect = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Turn on incremental compilation of modules. Default is off. -; Incremental = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -[vsim] -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -resolution = 1ns - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = ns - -; Default run length -RunLength = 100 ns - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 5000 - -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately reserve a VHDL license -; vlog Immediately reserve a Verilog license -; plus Immediately reserve a VHDL and Verilog license -; nomgc Do not look for Mentor Graphics Licenses -; nomti Do not look for Model Technology Licenses -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; Single value: -; License = plus -; Multi-value: -; License = noqueue plus - -; Stop the simulator after an assertion message -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Assertion Message Format -; %S - Severity Level -; %R - Report Message -; %T - Time of assertion -; %D - Delta -; %I - Instance or Region pathname (if available) -; %i - Instance pathname with process -; %O - Process name -; %K - Kind of object path is to return: Instance, Signal, Process or Unknown -; %P - Instance or Region path without leaf process -; %F - File -; %L - Line number of assertion or, if assertion is in a subprogram, line -; from which the call is made -; %% - Print '%' character -; If specific format for assertion level is defined, use its format. -; If specific format is not define for assertion level, use AssertionFormatBreak -; if assertion triggers a breakpoint (controlled by BreakOnAssertion level), -; otherwise use AssertionFormat. -; -; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" -; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" - -; Assertion File - alternate file for storing assertion messages -; AssertFile = assert.log - -; Default radix for all windows and commands. -; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned -DefaultRadix = symbolic - -; VSIM Startup command -; Startup = do startup.do - -; File for saving command transcript -TranscriptFile = transcript - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Disable assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Default force kind. May be freeze, drive, or deposit -; or in other terms, fixed, wired, or charged. -; DefaultForceKind = freeze - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control number of VHDL files open concurrently -; This number should always be less than the -; current ulimit setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the waveform window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings from the std_logic_arith, std_logic_unsigned -; and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from the IEEE numeric_std and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Control the format of a generate statement label. Do not quote it. -; GenerateFormat = %s__%d - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -; DefaultRestartOptions = -force - -; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs -; (> 500 megabyte memory footprint). Default is disabled. -; Specify number of megabytes to lock. -; LockedMemory = 1000 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (log only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -[lmc] -; ModelSim's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so - -; ModelSim's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so -[Project] -Project_Version = 5 -Project_DefaultLib = work -Project_SortMethod = unused -Project_Files_Count = 9 -Project_File_0 = CRC32_D8.v -Project_File_P_0 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1138046060 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 3 dont_compile 0 -Project_File_1 = C:/Documents and Settings/Administrator/Desktop/Transmit Code/TransmitTop/TransmitTop_pause_tb.v -Project_File_P_1 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1141519658 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 7 dont_compile 0 -Project_File_2 = C:/Documents and Settings/Administrator/Desktop/Transmit Code/TransmitTop/TransmitTop_min_frame_tb.v -Project_File_P_2 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1140359148 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 6 dont_compile 0 -Project_File_3 = TransmitTop.v -Project_File_P_3 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 1 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1143300944 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0 -Project_File_4 = CRC32_D64.v -Project_File_P_4 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1141580292 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 2 dont_compile 0 -Project_File_5 = ack_counter.v -Project_File_P_5 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1137802524 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 0 dont_compile 0 -Project_File_6 = TransmitTop_tb.v -Project_File_P_6 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1140351806 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 5 dont_compile 0 -Project_File_7 = C:/Documents and Settings/Administrator/Desktop/Transmit Code/TransmitTop/Copy of TransmitTop.v -Project_File_P_7 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1142704298 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 8 dont_compile 0 -Project_File_8 = byte_counter.v -Project_File_P_8 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1142697560 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 1 dont_compile 0 -Project_Sim_Count = 0 -Project_Folder_Count = 0 Index: trunk/tx_engine/byte_counter.v =================================================================== --- trunk/tx_engine/byte_counter.v (revision 42) +++ trunk/tx_engine/byte_counter.v (nonexistent) @@ -1,31 +0,0 @@ -module byte_count_module(CLK, RESET, START, BYTE_COUNTER); - -// Ports declaration -input CLK; -input RESET; -input START; - - - -output [15:0] BYTE_COUNTER; - -reg [15:0] BYTE_COUNTER; -reg [15:0] counter; - -always @(posedge CLK or posedge RESET) -begin - if (RESET == 1) begin - counter = 16'h0000; - end - - // the ack is delayed which starts the counter - else if (START == 1) begin - counter = counter + 8; - end - - BYTE_COUNTER = counter; -end - - -endmodule // End of Module - Index: trunk/tx_engine/debug.do =================================================================== --- trunk/tx_engine/debug.do (revision 42) +++ trunk/tx_engine/debug.do (nonexistent) @@ -1,130 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_CLK -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/RESET -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_START -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_UNDERRUN -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_ACK -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/FC_TRANS_PAUSEDATA -add wave -noupdate -format Logic -radix unsigned /TransmitTop_min_frame_tb/U_top_module/FC_TRANS_PAUSEVAL -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/FC_TX_PAUSEDATA -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/FC_TX_PAUSEVALID -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/FRAME_START -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/reset_int -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/DELAY_ACK -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/BYTE_COUNTER -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/final_byte_count -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_REG -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL1 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL2 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL3 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL4 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL5 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL6 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL7 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL8 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL9 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL10 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL11 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL12 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL13 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL14 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL15 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_REG -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL1 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL2 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL3 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL4 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL5 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL6 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL7 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL8 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL9 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL10 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL11 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL12 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL13 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL14 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL15 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/reset_err_pause -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/apply_pause_delay -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/store_pause_frame -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXD_PAUSE_DEL0 -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXD_PAUSE_DEL1 -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXD_PAUSE_DEL2 -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXC_PAUSE_DEL0 -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXC_PAUSE_DEL1 -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXC_PAUSE_DEL2 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/PAUSEVAL_DEL -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/PAUSEVAL_DEL1 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/PAUSEVAL_DEL2 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/set_pause_stats -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/store_transmit_pause_value -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/pause_frame_counter -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/shift_pause_data -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/shift_pause_valid -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/load_final_CRC -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/append_end_frame -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/START_CRC8_DEL -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/load_CRC8 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/insert_error -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/store_tx_data_valid -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/store_tx_data -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/tx_data_int -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/store_CRC64 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/frame_start_del -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/final_byte_count -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/byte_count_reg -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/append_reg -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/start_CRC8 -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/transmit_pause_frame_del -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/transmit_pause_frame -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/append_start_pause -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/append_start_pause_del -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/transmit_pause_frame_valid -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/load_CRC8 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/CRC_OUT -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/vlan_enabled_int -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/jumbo_enabled_int -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/length_register -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/tx_undderrun_int -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/MAX_FRAME_SIZE -add wave -noupdate -divider CRC64 -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/DATA_IN -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/CLK -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/RESET -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/START -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/CRC_OUT -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/CRC_REG -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/startCRC -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/data_del -add wave -noupdate -divider CRC8 -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/DATA_IN -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/CLK -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/RESET -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/START -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/LOAD -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/CRC_IN -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/CRC_OUT -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/start_int -add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/data_int -add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/vlan_enabled_int -add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/length_register -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {240 ns} 0} -WaveRestoreZoom {0 ns} {747 ns} -configure wave -namecolwidth 393 -configure wave -valuecolwidth 134 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 Index: trunk/tx_engine/TransmitTop.v =================================================================== --- trunk/tx_engine/TransmitTop.v (revision 42) +++ trunk/tx_engine/TransmitTop.v (nonexistent) @@ -1,1410 +0,0 @@ -///////////////////////////////////////////////////////////////////////////// -// -// Name of module -// 23/1/06 - So far Mentor Precision indicates the current system runs as 101 MHz. -// -///////////////////////////////////////////////////////////////////////////// -module TRANSMIT_TOP( -TX_DATA, -TX_DATA_VALID, -TX_CLK, -RESET, -TX_START, -TX_ACK, -TX_UNDERRUN, -TX_IFG_DELAY, -RXTXLINKFAULT, -LOCALLINKFAULT, -TX_STATS_VALID, -TXSTATREGPLUS, -TXD, -TXC, -FC_TRANS_PAUSEDATA, -FC_TRANS_PAUSEVAL, -FC_TX_PAUSEDATA, -FC_TX_PAUSEVALID, -TX_CFG_REG_VALUE, -TX_CFG_REG_VALID -); - - -///////////////////////////////////////////////////////////////////////////// -// -// Input and output ports definitions -// -///////////////////////////////////////////////////////////////////////////// - -//Input from user logic -input [63:0] TX_DATA; -input [7:0] TX_DATA_VALID; // To accept the data valid to be available -input TX_CLK; -input RESET; -input TX_START; // This signify the first frame of data -input TX_UNDERRUN; // this will cause an error to be injected into the data -input [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal - -//input to transmit fault signals -input RXTXLINKFAULT; -input LOCALLINKFAULT; - -input [31:0] TX_CFG_REG_VALUE; -input TX_CFG_REG_VALID; - -//output to stat register -output TX_STATS_VALID; -output [24:0] TXSTATREGPLUS; // a pulse for each reg for stats - -//output to user logic -output TX_ACK; //Generated by a counter - -//output to XGMII -output [63:0] TXD; -output [7:0] TXC; - -//output [15:0] BYTE_COUNTER_OUT; - -//Pause inputs -//Transmit pause frames -input [15:0] FC_TRANS_PAUSEDATA; //pause frame data -input FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent - -//apply pause timing -input [15:0] FC_TX_PAUSEDATA; -input FC_TX_PAUSEVALID; - - - -///////////////////////////////////////////////////////////////////////////// -// -// Definitions and parameters -// -///////////////////////////////////////////////////////////////////////////// - -//possibility to put this in a package. - -//opcode definitions -parameter PAUSE_OPCODE = 16'b1000100000001000; //8808 -parameter VLAN_OPCODE = 16'b1000000100000000; //8100 - -//frame size definitions -parameter VLAN_FRAME_SIZE = 16'b0000010111110010;//1522 bytes -parameter JUMBO_FRAME_SIZE = 16'b0010001100101000;//9000 bytes -parameter NORMAL_FRAME_SIZE = 16'b0000010111101110;//1518 bytes -parameter MIN_FRAME_SIZE = 16'b0000000000111100; //60 bytes - - -//Frame definition -parameter IDLE_FRAME = 8'b00000111; //only six preambles as the first preamble is converted into a start flag -parameter IDLE_FRAME_8BYTES = 64'b0000011100000111000001110000011100000111000001110000011100000111; -parameter START_SEQ = 64'b1010101110101010101010101010101010101010101010101010101011111011; -parameter LOCAL_FAULT_SEQ = 64'b0000000100000000000000000000000000000001000000000000000000000000; -parameter REMOTE_FAULT_SEQ = 64'b0000001000000000000000000000000000000010000000000000000000000000; -parameter START_FRAME = 8'b11111011; //only valid in frame 0 -parameter TERMINATE_FRAME = 8'b11111101; -parameter SFD_FRAME = 8'b10101011; -parameter PREAMBLE_FRAME = 8'b10101010; -parameter ERROR_FRAME = 8'b11111110; - - -parameter SOURCE_ADDR = 48'h010101010101; -parameter DEST_ADDR = 48'h101010101010; - -parameter PAUSE_FRAME_LENGTH = 8'h02; - - -//need a parameter for min frame gap. - -//Link fault signalling -// send lane 0 - - -///////////////////////////////////////////////////////////////////////////// -// -// Registers and wires -// -///////////////////////////////////////////////////////////////////////////// - - - - -wire TX_ACK; - -reg [24:0] TXSTATREGPLUS; - -reg TX_STATS_VALID; - -reg FRAME_START; - -wire reset_int; - -reg [15:0] DELAY_ACK; - -reg [7:0] TX_DATA_VALID_REG; -reg [7:0] TX_DATA_VALID_DEL1; -reg [7:0] TX_DATA_VALID_DEL2; -reg [7:0] TX_DATA_VALID_DEL3; -reg [7:0] TX_DATA_VALID_DEL4; -reg [7:0] TX_DATA_VALID_DEL5; -reg [7:0] TX_DATA_VALID_DEL6; -reg [7:0] TX_DATA_VALID_DEL7; -reg [7:0] TX_DATA_VALID_DEL8; -reg [7:0] TX_DATA_VALID_DEL9; -reg [7:0] TX_DATA_VALID_DEL10; -reg [7:0] TX_DATA_VALID_DEL11; -reg [7:0] TX_DATA_VALID_DEL12; -reg [7:0] TX_DATA_VALID_DEL13; -reg [7:0] TX_DATA_VALID_DEL14; -reg [7:0] TX_DATA_VALID_DEL15; - -reg [63:0] TX_DATA_DEL1; -reg [63:0] TX_DATA_DEL2; -reg [63:0] TX_DATA_DEL3; -reg [63:0] TX_DATA_DEL4; -reg [63:0] TX_DATA_DEL5; -reg [63:0] TX_DATA_DEL6; -reg [63:0] TX_DATA_DEL7; -reg [63:0] TX_DATA_DEL8; -reg [63:0] TX_DATA_DEL9; -reg [63:0] TX_DATA_DEL10; -reg [63:0] TX_DATA_DEL11; -reg [63:0] TX_DATA_DEL12; -reg [63:0] TX_DATA_DEL13; -reg [63:0] TX_DATA_DEL14; -reg [63:0] TX_DATA_DEL15; - -reg [7:0] OVERFLOW_VALID; -reg [63:0] OVERFLOW_DATA; - -reg [63:0] TXD; -reg [7:0] TXC; - -reg [63:0] TX_DATA_REG, TX_DATA_VALID_DELAY; - -wire [31:0] CRC_32_64; - -wire [15:0] BYTE_COUNTER; - -reg frame_start_del; - -reg transmit_pause_frame_del, transmit_pause_frame_del2, transmit_pause_frame, append_start_pause, append_start_pause_del , transmit_pause_frame_valid, reset_err_pause, load_CRC8, transmit_pause_frame_del3; - -reg [7:0] tx_data_int; -reg start_CRC8, START_CRC8_DEL; -reg append_end_frame; - - -reg insert_error; - -reg [7:0] store_tx_data_valid; -reg [63:0] store_tx_data; -reg [31:0] store_CRC64; -reg [7:0] store_valid; -reg load_final_CRC; - -reg [15:0] final_byte_count, byte_count_reg; - -wire [31:0] CRC_OUT; - -reg [9:0] append_reg; - - -reg [15:0] length_register; - -reg tx_undderrun_int; - -reg [15:0] MAX_FRAME_SIZE; - -reg vlan_enabled_int; -reg jumbo_enabled_int; -reg tx_enabled_int; -reg fcs_enabled_int; -reg reset_tx_int; -reg read_ifg_int; - -reg apply_pause_delay; -reg [15:0] store_pause_frame; - -reg [63:0] TXD_PAUSE_DEL0; -reg [63:0] TXD_PAUSE_DEL1; -reg [63:0] TXD_PAUSE_DEL2; - -reg [7:0] TXC_PAUSE_DEL0; -reg [7:0] TXC_PAUSE_DEL1; -reg [7:0] TXC_PAUSE_DEL2; - -reg PAUSEVAL_DEL; -reg PAUSEVAL_DEL1; -reg PAUSEVAL_DEL2; -wire RESET_ERR_PAUSE; - -reg set_pause_stats; -reg [15:0] store_transmit_pause_value; -reg [3:0] pause_frame_counter; -reg [63:0] shift_pause_data; - -reg [7:0] shift_pause_valid; -reg [7:0] shift_pause_valid_del; - -reg [14:0] byte_count_stat; - -reg [24:0] txstatplus_int; - - -///////////////////////////////////////////////////////////////////////////// -// -// Start of code -// -///////////////////////////////////////////////////////////////////////////// - - - - -//TODO - -//RX side. need to be able to receive data and calculate the CRC switching between 64 and 8 bit datapath. -//Therefore, the data need to be counted correctly. -//ERROR checking module or process will be needed. This will check if frame is correct length. -//Need to be able to remove redundant frames or columns and also padding. The error module will -//also check the tx_underrun signal as well. - -//need to be able to cut-off bytes. - -//Need to add the link fault signalling and config registers. - - -//TX side. need to be able to insert the CRC with the data. -//need to define the first column of txd which is START 6 PRE and SFD. -//need to be able invert data_valid for txc. -//need to be able to transmit IDLEs. - - -//Format of output -//IDLE 07, START FB TERMINATE FD SFD 10101011 PREAMBLE 10101010 ERROR FE. - -//IDLE START PREAMBLE SFD DA SA L/T DATA TERMINATE IDLE - - - - - - - - -///////////////////////////////////////////////////////////////////////////// -// -// Ack counter -// -///////////////////////////////////////////////////////////////////////////// - - -//Ack counter. need to be able to load the frame length, pause frame inter frame delay into the ack counter -// as this will delay the ack signal. The ack signal will initiate the rest of the data transmission from the -// user logic. - -//need to stop the ack signal from transmitting when a PAUSE frame is transmitting - -// Connect DUT to test bench -ack_counter U_ACK_CNT( -.clock(TX_CLK), -.reset(reset_int | reset_tx_int), -.ready(FRAME_START | transmit_pause_frame), -.tx_start(TX_START), -.max_count(DELAY_ACK), -.tx_ack(TX_ACK) -); - -//CRC for 64 bit data -//This seem to be one of the culprit for the timing violation -CRC32_D64 U_CRC64( -.DATA_IN(TX_DATA_REG), //need to swap between pause data -.CLK(TX_CLK), -.RESET(reset_int | TX_ACK | append_start_pause), -.START(frame_start_del | transmit_pause_frame_valid), -.CRC_OUT(CRC_32_64) //need to switch to output some how for a pause frame -); - - -//CRC for 8 bit data -CRC32_D8 U_CRC8( -.DATA_IN(tx_data_int), //8bit data -.CLK(TX_CLK), -.RESET(reset_int), -.START(start_CRC8), //this signal will be use to start -.LOAD(load_CRC8), //use this to load first -.CRC_IN(CRC_32_64), -.CRC_OUT(CRC_OUT) -); - - -//The start signal need to be high for the count -//This seem to be one of the culprit for the timing violation -byte_count_module U_byte_count_module( -.CLK(TX_CLK), -.RESET(reset_int | TX_ACK), -.START(frame_start_del & FRAME_START), -.BYTE_COUNTER(BYTE_COUNTER) -); - - - -///////////////////////////////////////////////////////////////////////////// -// -// PAUSE FRAME -// -///////////////////////////////////////////////////////////////////////////// - -always @(posedge TX_CLK) -begin - PAUSEVAL_DEL <= FC_TRANS_PAUSEVAL; - PAUSEVAL_DEL1 <= PAUSEVAL_DEL; - PAUSEVAL_DEL2 <= PAUSEVAL_DEL1; -end - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - transmit_pause_frame <= 0; - end - else if (PAUSEVAL_DEL2) begin - transmit_pause_frame <= 1; - end - else if (pause_frame_counter == 8) begin - transmit_pause_frame <= 0; - end -end - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - set_pause_stats <= 0; - end - else if (PAUSEVAL_DEL2) begin - set_pause_stats <= 1; - end - else if (append_end_frame) begin - set_pause_stats <= 0; - end -end - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - TXD_PAUSE_DEL0 <= 0; - TXD_PAUSE_DEL1 <= 0; - TXD_PAUSE_DEL2 <= 0; - - TXC_PAUSE_DEL0 <= 0; - TXC_PAUSE_DEL1 <= 0; - TXC_PAUSE_DEL2 <= 0; - - - store_transmit_pause_value <= 0; - end - else if (FC_TRANS_PAUSEVAL) begin - store_transmit_pause_value <= FC_TRANS_PAUSEDATA; - TXD_PAUSE_DEL1 <= {DEST_ADDR, SOURCE_ADDR[47:32]}; - TXD_PAUSE_DEL2 <= {SOURCE_ADDR[31:0], PAUSE_FRAME_LENGTH, PAUSE_OPCODE, FC_TRANS_PAUSEDATA}; - - TXC_PAUSE_DEL1 <= 8'hff; - TXC_PAUSE_DEL2 <= 8'hff; - - end -end - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - pause_frame_counter <= 0; - end - else if (transmit_pause_frame & !FRAME_START) begin - pause_frame_counter <= pause_frame_counter + 1; - end -end - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - shift_pause_data <= 0; - shift_pause_valid_del <= 0; - shift_pause_valid <= 0; - end - else if (transmit_pause_frame & !FRAME_START) begin - if (pause_frame_counter == 0) begin - shift_pause_data <= TXD_PAUSE_DEL1; - end - else if (pause_frame_counter == 1) begin - shift_pause_data <= TXD_PAUSE_DEL2; - end - else begin - shift_pause_data <= 0; - end - - - if (pause_frame_counter == 7) begin - shift_pause_valid <= 8'h0f; - end - else if (pause_frame_counter < 7) begin - shift_pause_valid <= 8'hff; - end - else begin - shift_pause_valid <= 0; - end - - shift_pause_valid_del <= shift_pause_valid; - end - else begin - shift_pause_data <= 0; - shift_pause_valid <= 0; - shift_pause_valid_del <= shift_pause_valid; - end -end - - - - -always @(posedge reset_int or posedge TX_CLK) -begin - if (reset_int) begin - FRAME_START <= 0; - end - else if (TX_ACK) begin - FRAME_START <= 1; - end - else if ((TX_DATA_VALID_REG != 8'hff) & (BYTE_COUNTER != 0)) begin - FRAME_START <= 0; - end -end - - - - -assign reset_int = RESET; - - -//TXSTATREGPLUS[24:0] -//24 pause_frame transmitted - count when pause flag is set -//23 to 20 bytes valid -//19 vlan frame - asserted if previous frame was a VLAN - just check if VLAN been set -//18 to 5 last frame length count in bytes stick to 16383 when jumbo frame is greater than value - just load the byte count -//4 if last frame has control type code 88-08 in the length type field - pause frame - check if pause flag is set -//3 underrun frame - check if underrun is set -//2 multicast frame - 01-80-C2-00-00-01 use for pause frame -//1 broadcast frame - al ones -//0 sucessful frame - check if error occurred -use insert error flag - - -//TX_STATS_VALID - need to be driving after a frame transmission - use load_overflow signal - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - txstatplus_int <= 0; - end - else if (load_final_CRC) begin - if (insert_error) begin - txstatplus_int[3] <= 1; - end - if (set_pause_stats) begin - txstatplus_int[24] <= 1; - txstatplus_int[4] <= 1; - txstatplus_int[2] <= 1; - txstatplus_int[1] <= 1; - txstatplus_int[18:5] <= 512; - end - if (vlan_enabled_int) begin - txstatplus_int[19] <= 1; - end - else begin - if (final_byte_count[15] == 1) begin - txstatplus_int[18:5] <= 16383; - end - else begin - txstatplus_int[18:5] <= byte_count_stat; - end - end - end - else begin - txstatplus_int <= 0; - end - - TXSTATREGPLUS <= txstatplus_int; - TX_STATS_VALID <= append_end_frame; -end - - - - -//input [31:0] TX_CFG_REG_VALUE; -//24:0 reserved -//25 default to 0 - min frame - 1 adjust frame delay by reading inter-frame gap delay reg - DELAY_ACK signal -//26 WAN - not used -//27 VLAN enable default to 0, 1 enabled -//28 default to 1 - transmitter enbaled, 0 - transmitter disabled - possibly used to reset -//29 default to 0 FCS enabled, 1 FCS disabled -//30 default to 0, 1 - Jumbo frame enabled -//31 deafult to 0, 1 - reset transmitter - -//input TX_CFG_REG_VALID; - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - vlan_enabled_int <= 0; - jumbo_enabled_int <= 0; - tx_enabled_int <= 0; - fcs_enabled_int <= 1; - reset_tx_int <= 0; - read_ifg_int <= 0; - end - else if (TX_CFG_REG_VALID) begin - vlan_enabled_int <= TX_CFG_REG_VALUE[27]; - jumbo_enabled_int <= TX_CFG_REG_VALUE[30]; - tx_enabled_int <= TX_CFG_REG_VALUE[28]; // Stop ack from generated, hold reset - fcs_enabled_int <= TX_CFG_REG_VALUE[29]; - reset_tx_int <= TX_CFG_REG_VALUE[31]; - read_ifg_int <= TX_CFG_REG_VALUE[25]; - end -end - - -//Load the delay value for the acknowledge signal -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - DELAY_ACK <= 16'h0001; - end - else if (apply_pause_delay) begin - DELAY_ACK <= store_pause_frame; - end - else if (read_ifg_int) begin - DELAY_ACK <= TX_IFG_DELAY; - end - end - - -//Need to expand to be setup by the config register -//1514 with out FCS added, 1518 when FCS is added -//1518 without FCS added, 1522 when FCS is added -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - MAX_FRAME_SIZE <= 1514; - end - else begin - if (vlan_enabled_int) begin - if (fcs_enabled_int) begin - MAX_FRAME_SIZE <= 1522; - end - else begin - MAX_FRAME_SIZE <= 1518; - end - end - else if (jumbo_enabled_int) begin - if (fcs_enabled_int) begin - MAX_FRAME_SIZE <= 1518; - end - else begin - MAX_FRAME_SIZE <= 1514; - end - end - else begin - if (fcs_enabled_int) begin - MAX_FRAME_SIZE <= 1518; - end - else begin - MAX_FRAME_SIZE <= 1514; - end - end - end -end - - - - -always @(posedge TX_CLK) -begin - if (reset_int) begin - tx_undderrun_int <= 0; - end - else if (append_end_frame) - tx_undderrun_int <= 0; - end - else if (TX_UNDERRUN == 1) begin - tx_undderrun_int <= 1; - end -end - -//Indicate an error -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - insert_error <= 0; - end - else if (append_end_frame | reset_err_pause) begin - insert_error <= 0; - end - else if (load_CRC8) begin - if (tx_undderrun_int == 1) begin - insert_error <= 1; - end - else begin - if (length_register == final_byte_count) begin - if (final_byte_count <= MAX_FRAME_SIZE) begin - insert_error <= 0; - end - else begin - insert_error <= 1; - end - end - else if (length_register < MIN_FRAME_SIZE) begin - if (final_byte_count == 64) begin - insert_error <= 0; - end - else begin - insert_error <= 1; - end - end - else begin - insert_error <= 1; - end - end - end -end - - -//use for delaying the ack signal when pause is required -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - apply_pause_delay <= 0; - store_pause_frame <= 0; - end - else if (TX_ACK) begin - apply_pause_delay <= 0; - store_pause_frame <= 0; - end - else if (FC_TX_PAUSEVALID) begin - apply_pause_delay <= 1; - store_pause_frame <= FC_TX_PAUSEDATA; - end -end - - - - -always @(posedge TX_CLK) -begin - if (TX_START) begin - TX_DATA_VALID_DELAY <= IDLE_FRAME_8BYTES; - end - else begin - TX_DATA_VALID_DELAY <= TX_DATA; - end -end - - - -//Shift valid into the system and also ensuring min frame is achieved -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - TX_DATA_VALID_REG <= 0; - end - else if (FRAME_START) begin - if (BYTE_COUNTER < 48) begin - TX_DATA_VALID_REG <= 8'b11111111; - end - else if (BYTE_COUNTER == 48) begin - if (TX_START) begin - TX_DATA_VALID_REG <= 8'b00001111; - end - else begin - TX_DATA_VALID_REG <= 8'b00001111 | TX_DATA_VALID; - end - end - else begin - if (TX_START) begin - TX_DATA_VALID_REG <= 0; - end - else begin - TX_DATA_VALID_REG <= TX_DATA_VALID; - end - end - end - else if (transmit_pause_frame_del) begin - shift_pause_valid_del <= shift_pause_valid; - TX_DATA_VALID_REG <= shift_pause_valid_del; - end - else begin - TX_DATA_VALID_REG <= 0; - end -end - - -//Shifting data to the system. Also ensuring min frame is achieved -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - TX_DATA_REG <= IDLE_FRAME_8BYTES; - end - else if (FRAME_START) begin - if (BYTE_COUNTER < 56) begin - case (TX_DATA_VALID_REG) - 8'b00000000 : begin - TX_DATA_REG <= TX_DATA_VALID_DELAY; - end - 8'b00000001 : begin - TX_DATA_REG <= {56'h00000000000000, TX_DATA_VALID_DELAY[7:0]}; - end - 8'b00000011 : begin - TX_DATA_REG <= {48'h000000000000, TX_DATA_VALID_DELAY[15:0]}; - end - 8'b00000111 : begin - TX_DATA_REG <= {40'h0000000000, TX_DATA_VALID_DELAY[23:0]}; - end - 8'b00001111 : begin - TX_DATA_REG <= {32'h00000000, TX_DATA_VALID_DELAY[31:0]}; - end - 8'b00011111 : begin - TX_DATA_REG <= {24'h000000, TX_DATA_VALID_DELAY[39:0]}; - end - 8'b00111111 : begin - TX_DATA_REG <= {16'h0000, TX_DATA_VALID_DELAY[47:0]}; - end - 8'b01111111 : begin - TX_DATA_REG <= {8'h00, TX_DATA_VALID_DELAY[55:0]}; - end - 8'b11111111 : begin - TX_DATA_REG <= TX_DATA_VALID_DELAY; - end - endcase - end - else begin - TX_DATA_REG <= TX_DATA_VALID_DELAY; - end - end - else if (transmit_pause_frame_valid) begin - TX_DATA_REG <= shift_pause_data; - end - else begin - if (TX_ACK | append_start_pause) begin - TX_DATA_REG <= START_SEQ; - end - else begin - TX_DATA_REG <= IDLE_FRAME_8BYTES; - end - end - -end - - - - - - - -//Use for shifting data to CRC and loading start value for CRC -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - frame_start_del <= 0; - transmit_pause_frame_del <= 0; - transmit_pause_frame_del2 <= 0; - transmit_pause_frame_del3 <= 0; - append_start_pause <= 0; - append_start_pause_del <= 0; - transmit_pause_frame_valid <= 0; - reset_err_pause <= 0; - load_CRC8 <= 0; - end - else begin - frame_start_del <= FRAME_START; - transmit_pause_frame_del <= transmit_pause_frame; - transmit_pause_frame_del2 <= transmit_pause_frame_del; - transmit_pause_frame_del3 <= transmit_pause_frame_del2; - append_start_pause <= (!transmit_pause_frame_del & transmit_pause_frame); - append_start_pause_del <= append_start_pause; - transmit_pause_frame_valid <= (transmit_pause_frame_del & transmit_pause_frame); - reset_err_pause <= (transmit_pause_frame_del & !transmit_pause_frame); - load_CRC8 <= (frame_start_del & !FRAME_START) | (transmit_pause_frame_del3 & !transmit_pause_frame_del2); - end -end - - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - TX_DATA_VALID_DEL1 <= 0; - TX_DATA_VALID_DEL2 <= 0; - TX_DATA_VALID_DEL3 <= 0; - TX_DATA_VALID_DEL4 <= 0; - TX_DATA_VALID_DEL5 <= 0; - TX_DATA_VALID_DEL6 <= 0; - TX_DATA_VALID_DEL7 <= 0; - TX_DATA_VALID_DEL8 <= 0; - TX_DATA_VALID_DEL9 <= 0; - TX_DATA_VALID_DEL10 <= 0; - TX_DATA_VALID_DEL11 <= 0; - TX_DATA_VALID_DEL12 <= 0; - TX_DATA_VALID_DEL13 <= 0; - TX_DATA_VALID_DEL14 <= 0; - TX_DATA_VALID_DEL15 <= 0; - OVERFLOW_VALID <= 0; - end - else begin - TX_DATA_VALID_DEL1 <= TX_DATA_VALID_REG; - TX_DATA_VALID_DEL2 <= TX_DATA_VALID_DEL1; - TX_DATA_VALID_DEL3 <= TX_DATA_VALID_DEL2; - TX_DATA_VALID_DEL4 <= TX_DATA_VALID_DEL3; - TX_DATA_VALID_DEL5 <= TX_DATA_VALID_DEL4; - TX_DATA_VALID_DEL6 <= TX_DATA_VALID_DEL5; - TX_DATA_VALID_DEL7 <= TX_DATA_VALID_DEL6; - TX_DATA_VALID_DEL8 <= TX_DATA_VALID_DEL7; - TX_DATA_VALID_DEL9 <= TX_DATA_VALID_DEL8; - TX_DATA_VALID_DEL10 <= TX_DATA_VALID_DEL9; - TX_DATA_VALID_DEL11 <= TX_DATA_VALID_DEL10; - TX_DATA_VALID_DEL12 <= TX_DATA_VALID_DEL11; - TX_DATA_VALID_DEL13 <= TX_DATA_VALID_DEL12; - TX_DATA_VALID_DEL14 <= TX_DATA_VALID_DEL13; - - if (load_final_CRC) begin - case (TX_DATA_VALID_DEL13) - 8'b00000000 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b00001111; - end - else begin - TX_DATA_VALID_DEL14 <= 8'b00001111; - end - OVERFLOW_VALID <= 8'b00000000; - end - 8'b00000001 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b00011111; - end - - OVERFLOW_VALID <= 8'b00000000; - end - 8'b00000011 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b00111111; - end - OVERFLOW_VALID <= 8'b00000000; - end - 8'b00000111 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b01111111; - end - - OVERFLOW_VALID <= 8'b00000000; - - end - 8'b00001111 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b11111111; - end - - OVERFLOW_VALID <= 8'b00000000; - - end - 8'b00011111 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b11111111; - OVERFLOW_VALID <= 8'b00000001; - end - else begin - OVERFLOW_VALID <= 8'b00000000; - end - - end - 8'b00111111 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b11111111; - OVERFLOW_VALID <= 8'b00000011; - end - else begin - OVERFLOW_VALID <= 8'b00000000; - end - end - 8'b01111111 : begin - if (fcs_enabled_int) begin - TX_DATA_VALID_DEL14 <= 8'b11111111; - OVERFLOW_VALID <= 8'b00000111; - end - else begin - OVERFLOW_VALID <= 8'b00000000; - end - end - endcase - - end - - else if (append_end_frame) begin - TX_DATA_VALID_DEL14 <= OVERFLOW_VALID; - end - - TX_DATA_VALID_DEL15 <= TX_DATA_VALID_DEL14; - TXC <= TX_DATA_VALID_DEL15; - end -end - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - TX_DATA_DEL1 <= 0; - TX_DATA_DEL2 <= 0; - TX_DATA_DEL3 <= 0; - TX_DATA_DEL4 <= 0; - TX_DATA_DEL5 <= 0; - TX_DATA_DEL6 <= 0; - TX_DATA_DEL7 <= 0; - TX_DATA_DEL8 <= 0; - TX_DATA_DEL9 <= 0; - TX_DATA_DEL10 <= 0; - TX_DATA_DEL11 <= 0; - TX_DATA_DEL12 <= 0; - TX_DATA_DEL13 <= 0; - TX_DATA_DEL14 <= 0; - TX_DATA_DEL15 <= 0; - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - end - else begin - TX_DATA_DEL1 <= TX_DATA_REG; - TX_DATA_DEL2 <= TX_DATA_DEL1; - TX_DATA_DEL3 <= TX_DATA_DEL2; - TX_DATA_DEL4 <= TX_DATA_DEL3; - TX_DATA_DEL5 <= TX_DATA_DEL4; - TX_DATA_DEL6 <= TX_DATA_DEL5; - TX_DATA_DEL7 <= TX_DATA_DEL6; - TX_DATA_DEL8 <= TX_DATA_DEL7; - TX_DATA_DEL9 <= TX_DATA_DEL8; - TX_DATA_DEL10 <= TX_DATA_DEL9; - TX_DATA_DEL11 <= TX_DATA_DEL10; - TX_DATA_DEL12 <= TX_DATA_DEL11; - TX_DATA_DEL13 <= TX_DATA_DEL12; - TX_DATA_DEL14 <= TX_DATA_DEL13; - - if (load_final_CRC) begin - case (TX_DATA_VALID_DEL13) - 8'b00000000 : begin - if (fcs_enabled_int) begin - - TX_DATA_DEL14[31:0] <= CRC_OUT[31:0]; - if (insert_error) begin - TX_DATA_DEL14[39:32] <= ERROR_FRAME; - TX_DATA_DEL14[47:40] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[39:32] <= TERMINATE_FRAME; - TX_DATA_DEL14[47:40] <= IDLE_FRAME; - end - - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - else begin - if (insert_error) begin - TX_DATA_DEL14[7:0] <= ERROR_FRAME; - TX_DATA_DEL14[15:8] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[7:0] <= TERMINATE_FRAME; - TX_DATA_DEL14[15:8] <= IDLE_FRAME; - end - - TX_DATA_DEL14[23:16] <= IDLE_FRAME; - TX_DATA_DEL14[31:24] <= IDLE_FRAME; - TX_DATA_DEL14[39:32] <= IDLE_FRAME; - TX_DATA_DEL14[47:40] <= IDLE_FRAME; - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - end - 8'b00000001 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0]; - TX_DATA_DEL14[39:8] <= CRC_OUT[31:0]; - if (insert_error) begin - TX_DATA_DEL14[47:40] <= ERROR_FRAME; - TX_DATA_DEL14[55:48] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[47:40] <= TERMINATE_FRAME; - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - end - - - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - TX_DATA_DEL14 <= TX_DATA_DEL13; - - end - else begin - TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0]; - - if (insert_error) begin - TX_DATA_DEL14[15:8] <= ERROR_FRAME; - TX_DATA_DEL14[23:16] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[15:8] <= TERMINATE_FRAME; - TX_DATA_DEL14[23:16] <= IDLE_FRAME; - end - TX_DATA_DEL14[31:24] <= IDLE_FRAME; - TX_DATA_DEL14[39:32] <= IDLE_FRAME; - TX_DATA_DEL14[47:40] <= IDLE_FRAME; - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - TX_DATA_DEL14 <= TX_DATA_DEL13; - - end - - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - end - 8'b00000011 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0]; - TX_DATA_DEL14[47:16] <= CRC_OUT[31:0]; - if (insert_error) begin - TX_DATA_DEL14[55:48] <= ERROR_FRAME; - TX_DATA_DEL14[63:56] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[55:48] <= TERMINATE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - end - else begin - TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0]; - - if (insert_error) begin - TX_DATA_DEL14[23:16] <= ERROR_FRAME; - TX_DATA_DEL14[31:24] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[23:16] <= TERMINATE_FRAME; - TX_DATA_DEL14[31:24] <= IDLE_FRAME; - - end - TX_DATA_DEL14[39:32] <= IDLE_FRAME; - TX_DATA_DEL14[47:40] <= IDLE_FRAME; - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - end - 8'b00000111 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0]; - TX_DATA_DEL14[55:24] <= CRC_OUT[31:0]; - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - if (insert_error) begin - TX_DATA_DEL14[63:56] <= ERROR_FRAME; - OVERFLOW_DATA[7:0] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[63:56] <= TERMINATE_FRAME; - end - end - else begin - TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0]; - TX_DATA_DEL14[55:24] <= CRC_OUT[31:0]; - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - if (insert_error) begin - TX_DATA_DEL14[31:24] <= ERROR_FRAME; - TX_DATA_DEL14[39:32] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14[31:24] <= TERMINATE_FRAME; - TX_DATA_DEL14[39:32] <= IDLE_FRAME; - end - TX_DATA_DEL14[47:40] <= IDLE_FRAME; - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - - end - 8'b00001111 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0]; - TX_DATA_DEL14[63:32]<= CRC_OUT[31:0]; - - if (insert_error) begin - OVERFLOW_DATA [7:0] <= ERROR_FRAME; - OVERFLOW_DATA[15:8] <= TERMINATE_FRAME; - end - else begin - OVERFLOW_DATA [7:0]<= TERMINATE_FRAME; - OVERFLOW_DATA [15:8]<= IDLE_FRAME; - end - OVERFLOW_DATA [23:16]<= IDLE_FRAME; - OVERFLOW_DATA [31:24]<= IDLE_FRAME; - OVERFLOW_DATA [39:32]<= IDLE_FRAME; - OVERFLOW_DATA [47:40]<= IDLE_FRAME; - OVERFLOW_DATA [55:48]<= IDLE_FRAME; - OVERFLOW_DATA [63:56]<= IDLE_FRAME; - end - else begin - TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0]; - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - if (insert_error) begin - TX_DATA_DEL14 [39:32] <= ERROR_FRAME; - TX_DATA_DEL14[47:40] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14 [39:32]<= TERMINATE_FRAME; - TX_DATA_DEL14 [47:40]<= IDLE_FRAME; - end - TX_DATA_DEL14[55:48] <= IDLE_FRAME; - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - end - 8'b00011111 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0]; - TX_DATA_DEL14[63:40] <= CRC_OUT[23:0]; - OVERFLOW_DATA [7:0]<= CRC_OUT[31:24]; - if (insert_error) begin - OVERFLOW_DATA [15:8]<= ERROR_FRAME; - OVERFLOW_DATA [23:16]<= TERMINATE_FRAME; - end - else begin - OVERFLOW_DATA [15:8]<= TERMINATE_FRAME; - OVERFLOW_DATA [23:16]<= IDLE_FRAME; - end - OVERFLOW_DATA [31:24]<= IDLE_FRAME; - OVERFLOW_DATA [39:32]<= IDLE_FRAME; - OVERFLOW_DATA [47:40]<= IDLE_FRAME; - OVERFLOW_DATA [55:48]<= IDLE_FRAME; - OVERFLOW_DATA [63:56]<= IDLE_FRAME; - end - else begin - TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0]; - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - if (insert_error) begin - TX_DATA_DEL14 [47:40] <= ERROR_FRAME; - TX_DATA_DEL14[55:48] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14 [47:40]<= TERMINATE_FRAME; - TX_DATA_DEL14 [55:48]<= IDLE_FRAME; - end - TX_DATA_DEL14[63:56] <= IDLE_FRAME; - end - - end - 8'b00111111 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0]; - TX_DATA_DEL14[63:48] <= CRC_OUT[15:0]; - OVERFLOW_DATA [15:0]<= CRC_OUT[31:16]; - if (insert_error) begin - OVERFLOW_DATA [23:16]<= ERROR_FRAME; - OVERFLOW_DATA [31:24]<= TERMINATE_FRAME; - end - else begin - OVERFLOW_DATA [23:16]<= TERMINATE_FRAME; - OVERFLOW_DATA [31:24]<= IDLE_FRAME; - end - OVERFLOW_DATA [39:32]<= IDLE_FRAME; - OVERFLOW_DATA [47:40]<= IDLE_FRAME; - OVERFLOW_DATA [55:48]<= IDLE_FRAME; - OVERFLOW_DATA [63:56]<= IDLE_FRAME; - end - else begin - TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0]; - if (insert_error) begin - TX_DATA_DEL14 [55:48] <= ERROR_FRAME; - TX_DATA_DEL14[63:56] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14 [55:48]<= TERMINATE_FRAME; - TX_DATA_DEL14 [63:56]<= IDLE_FRAME; - end - - end - end - 8'b01111111 : begin - if (fcs_enabled_int) begin - TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0]; - TX_DATA_DEL14[63:56] <= CRC_OUT[7:0]; - OVERFLOW_DATA [23:0]<= CRC_OUT[31:8]; - if (insert_error) begin - OVERFLOW_DATA [31:24]<= ERROR_FRAME; - OVERFLOW_DATA [39:32]<= TERMINATE_FRAME; - end - else begin - OVERFLOW_DATA [31:24]<= TERMINATE_FRAME; - OVERFLOW_DATA [39:32]<= IDLE_FRAME; - end - OVERFLOW_DATA [47:40]<= IDLE_FRAME; - OVERFLOW_DATA [55:48]<= IDLE_FRAME; - OVERFLOW_DATA [63:56]<= IDLE_FRAME; - end - else begin - TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0]; - OVERFLOW_DATA <= IDLE_FRAME_8BYTES; - if (insert_error) begin - TX_DATA_DEL14 [63:56] <= ERROR_FRAME; - OVERFLOW_DATA[7:0] <= TERMINATE_FRAME; - end - else begin - TX_DATA_DEL14 [63:56]<= TERMINATE_FRAME; - OVERFLOW_DATA [7:0]<= IDLE_FRAME; - end - end - - end - - endcase - end - else if (append_end_frame) begin - TX_DATA_DEL14 <= OVERFLOW_DATA; - end - - TX_DATA_DEL15 <= TX_DATA_DEL14; - - TXD <= TX_DATA_DEL15; - end -end - - - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - store_tx_data_valid <= 0; - store_tx_data <= 0; - store_CRC64 <= 0; - tx_data_int <= 0; - end - else if (load_CRC8) begin - store_tx_data_valid <= TX_DATA_VALID_DEL2; - store_tx_data <= TX_DATA_DEL2; - store_CRC64 <= CRC_32_64; - end - else begin - store_tx_data_valid[6:0] <= store_tx_data_valid[7:1]; - tx_data_int <= store_tx_data[7:0]; - store_tx_data[55:0] <= store_tx_data[63:8]; - end -end - -//Start CRC8 and load CRC8 -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - start_CRC8 <= 0; - START_CRC8_DEL <= 0; - end - else begin - start_CRC8 <= store_tx_data_valid[0]; - START_CRC8_DEL <= start_CRC8; - end -end - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - byte_count_reg <= 0; - end - else begin - byte_count_reg <= BYTE_COUNTER; - end -end - -//Use for determining the number of bytes in the data -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - final_byte_count <= 0; - end - else if (load_CRC8) begin - if (BYTE_COUNTER == 64) begin - final_byte_count <= 60; - end - else begin - final_byte_count <= byte_count_reg; - end - end - else if (start_CRC8) begin - final_byte_count <= final_byte_count + 1; - end - - if (transmit_pause_frame) begin - byte_count_stat = 512; - end - else begin - byte_count_stat = final_byte_count; - end -end - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - append_reg <= 0; - load_final_CRC <= 0; - append_end_frame <= 0; - end - else begin - append_reg[0] <= load_CRC8; - append_reg[9:1] <= append_reg[8:0]; - load_final_CRC <= append_reg[9]; - append_end_frame <= load_final_CRC; - end -end - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - vlan_enabled_int <= 0; - end -end - -// VLAN field - 8100 at second 64 bit data at 32:47 and V1 V2 is at 48:63 -// length field at third 64 bit data at 0:15 - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - length_register <= 0; - end - if (vlan_enabled_int) begin - if (BYTE_COUNTER == 16) begin - length_register <= TX_DATA_REG[15:0]; - end - end - else begin - if (BYTE_COUNTER == 8) begin - length_register <= TX_DATA_REG[47:32]; - end - end - -end - - -always @(posedge TX_CLK or posedge reset_int) -begin - if (reset_int) begin - set_pause_stats <= 0; - end - else if (PAUSEVAL_DEL2) begin - set_pause_stats <= 1; - end - else if (append_end_frame) begin - set_pause_stats <= 0; - end -end - - -endmodule - Index: trunk/tx_engine/TransmitTop_min_frame_tb.v =================================================================== --- trunk/tx_engine/TransmitTop_min_frame_tb.v (revision 42) +++ trunk/tx_engine/TransmitTop_min_frame_tb.v (nonexistent) @@ -1,157 +0,0 @@ -`include "TransmitTop.v" -module TransmitTop_min_frame_tb(); - -//Input from user logic -reg [63:0] TX_DATA; -reg [63:0] TX_DATA_int; -reg [7:0] TX_DATA_VALID; // To accept the data valid to be available -reg Append_last_bit; -reg TX_CLK; -reg RESET; -reg TX_START; // This signify the first frame of data -reg TX_UNDERRUN; // this will cause an error to be injected into the data -reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal - -//input to transmit fault signals -reg RXTXLINKFAULT; -reg LOCALLINKFAULT; -reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data -reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent - -//apply pause timing -reg [15:0] FC_TX_PAUSEDATA; -reg FC_TX_PAUSEVALID; - -//apply configuration value -reg [31:0] TX_CFG_REG_VALUE; -reg TX_CFG_REG_VALID; - -//output to stat register -wire TX_STATS_VALID; -wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats -wire [63:0] TXD; -wire [7:0] TXC; -wire TX_ACK; -reg D_START; - -reg START_TX_BITS; - -// Initialize all variables -initial begin - - Append_last_bit = 0; - TX_CLK = 1; // initial value of clock - RESET <= 0; // initial value of reset - TX_START <= 0; // initial value of enable - TX_DATA_VALID <= 8'h00; - D_START = 0; - FC_TX_PAUSEVALID <= 0; - FC_TX_PAUSEDATA <= 0; - FC_TRANS_PAUSEDATA <= 0; - FC_TRANS_PAUSEVAL <= 0; - TX_UNDERRUN = 0; - #5 RESET= 1; // Assert the reset - #10 RESET= 0; // De-assert the reset - #15 TX_START = 1; - // TX_DATA = 64'h0000560000000000; - TX_DATA_VALID = 8'hFF; - D_START = 1; - #20 TX_START = 0; - //#1800 TX_DATA_VALID = 8'h07; - #60 TX_DATA_VALID = 8'h07; -// #1960 TX_DATA_VALID = 8'h07; - // TX_DATA = 64'h0000000000000011; - #10 TX_DATA_VALID = 8'h00; - D_START = 0; -//next frame - #20 TX_START <= 1; - TX_DATA_VALID <= 8'hFF; - D_START = 1; - #20 TX_START <= 0; - #400 TX_DATA_VALID <= 8'h00; - #10 TX_DATA_VALID <= 8'h00; - D_START = 0; - - #1000 $finish; // Terminate simulation -end - -always @(posedge D_START or posedge TX_CLK) -begin - if (D_START == 0) begin - TX_DATA = 64'h0000000000000000; - end - //else if (TX_DATA_VALID == 8'h07) begin - // TX_DATA = 64'h000000000077FFCC; - //end - else if (Append_last_bit == 1) begin -// TX_DATA = 64'h202020202077FFCC; - TX_DATA = 64'h000000000077FFCC; - end - else if (START_TX_BITS == 1) begin - TX_DATA = TX_DATA + 1; - end - else begin - TX_DATA = 64'h0000000000000001; - end -end - - - -always @(TX_DATA) -begin - if (TX_DATA == 2) begin - TX_DATA_int[31:0] <= TX_DATA[31:0]; - TX_DATA_int[47:32] <= 300; - TX_DATA_int[63:48] <= TX_DATA[63:48]; - end - else begin - TX_DATA_int <= TX_DATA; - end - -end - - -always @(TX_ACK | TX_START) -begin - if (TX_ACK) begin - START_TX_BITS = 1; - end - else if (TX_START) begin - START_TX_BITS = 0; - end -end - - -// Clock generator -always begin - #5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks -end - -// Connect DUT to test bench -TRANSMIT_TOP U_top_module ( -TX_DATA_int, -TX_DATA_VALID, -TX_CLK, -RESET, -TX_START, -TX_ACK, -TX_UNDERRUN, -TX_IFG_DELAY, -RXTXLINKFAULT, -LOCALLINKFAULT, -TX_STATS_VALID, -TXSTATREGPLUS, -TXD, -TXC, -FC_TRANS_PAUSEDATA, -FC_TRANS_PAUSEVAL, -FC_TX_PAUSEDATA, -FC_TX_PAUSEVALID, -TX_CFG_REG_VALUE, -TX_CFG_REG_VALID -); - - - - -endmodule \ No newline at end of file Index: trunk/tx_engine/TransmitTop_pause_tb.v =================================================================== --- trunk/tx_engine/TransmitTop_pause_tb.v (revision 42) +++ trunk/tx_engine/TransmitTop_pause_tb.v (nonexistent) @@ -1,161 +0,0 @@ -`include "TransmitTop.v" -module TransmitTopPause_tb(); - -//Input from user logic -reg [63:0] TX_DATA; -reg [63:0] TX_DATA_int; -reg [7:0] TX_DATA_VALID; // To accept the data valid to be available -reg Append_last_bit; -reg TX_CLK; -reg RESET; -reg TX_START; // This signify the first frame of data -reg TX_UNDERRUN; // this will cause an error to be injected into the data -reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal - -//input to transmit fault signals -reg RXTXLINKFAULT; -reg LOCALLINKFAULT; -reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data -reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent - -//apply pause timing -reg [15:0] FC_TX_PAUSEDATA; -reg FC_TX_PAUSEVALID; - -//apply configuration value -reg [31:0] TX_CFG_REG_VALUE; -reg TX_CFG_REG_VALID; - -//output to stat register -wire TX_STATS_VALID; -wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats -wire [63:0] TXD; -wire [7:0] TXC; -wire TX_ACK; -reg D_START; - -reg START_TX_BITS; - -// Initialize all variables -initial begin - Append_last_bit = 0; - TX_CLK = 1; // initial value of clock - RESET <= 0; // initial value of reset - TX_START <= 0; // initial value of enable - TX_DATA_VALID <= 8'h00; - D_START = 0; - FC_TX_PAUSEVALID <= 0; - FC_TX_PAUSEDATA <= 0; - FC_TRANS_PAUSEDATA <= 0; - FC_TRANS_PAUSEVAL <= 0; - TX_UNDERRUN = 0; - #5 RESET <= 1; // Assert the reset - #10 RESET <= 0; // De-assert the reset - - #15 //TX_START <= 1; - //TX_DATA_VALID <= 8'hFF; - //D_START <= 1; - #20 TX_START <= 0; - #400 //TX_DATA_VALID <= 8'h00; - //FC_TX_PAUSEVALID <= 1; - //FC_TX_PAUSEDATA <= 30; - FC_TRANS_PAUSEDATA <= 30; - FC_TRANS_PAUSEVAL <= 1; - //TX_DATA_VALID <= 8'h7f; - #10 TX_DATA_VALID <= 8'h00; - D_START = 0; - //FC_TX_PAUSEVALID <= 0; - //FC_TX_PAUSEDATA <= 0; - FC_TRANS_PAUSEDATA <= 0; - FC_TRANS_PAUSEVAL <= 0; - #20 //TX_START <= 1; - //TX_DATA_VALID <= 8'hFF; - //D_START = 1; - #20 TX_START <= 0; - #400 TX_DATA_VALID <= 8'h00; - #10 TX_DATA_VALID <= 8'h00; - D_START = 0; - #1300 $finish; // Terminate simulation -end - -always @(posedge D_START or posedge TX_CLK) -begin - if (D_START == 0) begin - TX_DATA = 64'h0000000000000000; - end - //else if (TX_DATA_VALID == 8'h07) begin - // TX_DATA = 64'h000000000077FFCC; - //end - else if (Append_last_bit == 1) begin -// TX_DATA = 64'h202020202077FFCC; - TX_DATA = 64'h000000000077FFCC; - end - else if (START_TX_BITS == 1) begin - TX_DATA = TX_DATA + 1; - end - else begin - TX_DATA = 64'h0000000000000001; - end -end - - - -always @(TX_DATA) -begin - if (TX_DATA == 2) begin - TX_DATA_int[31:0] <= TX_DATA[31:0]; - TX_DATA_int[47:32] <= 300; - TX_DATA_int[63:48] <= TX_DATA[63:48]; - end - else begin - TX_DATA_int <= TX_DATA; - end - -end - - -always @(TX_ACK | TX_START) -begin - if (TX_ACK) begin - START_TX_BITS = 1; - end - else if (TX_START) begin - START_TX_BITS = 0; - end -end - - -// Clock generator -always begin - #5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks -end - -// Connect DUT to test bench -TRANSMIT_TOP U_top_module ( -TX_DATA_int, -TX_DATA_VALID, -TX_CLK, -RESET, -TX_START, -TX_ACK, -TX_UNDERRUN, -TX_IFG_DELAY, -RXTXLINKFAULT, -LOCALLINKFAULT, -TX_STATS_VALID, -TXSTATREGPLUS, -TXD, -TXC, -FC_TRANS_PAUSEDATA, -FC_TRANS_PAUSEVAL, -FC_TX_PAUSEDATA, -FC_TX_PAUSEVALID, -TX_CFG_REG_VALUE, -TX_CFG_REG_VALID -); - - - - -endmodule - Index: trunk/tx_engine/CRC32_D8.v =================================================================== --- trunk/tx_engine/CRC32_D8.v (revision 42) +++ trunk/tx_engine/CRC32_D8.v (nonexistent) @@ -1,135 +0,0 @@ -module CRC32_D8(DATA_IN, CLK, RESET, START, LOAD, CRC_IN, CRC_OUT); - - input [7:0] DATA_IN; - input CLK; - input RESET; - input START; - input LOAD; - input [31:0] CRC_IN; - output [31:0] CRC_OUT; - - reg [31:0] CRC_OUT; - reg start_int; - reg [7:0] data_int; - -always @(posedge CLK) -begin - start_int <= START; - data_int <= DATA_IN; -end - -always @(posedge CLK or posedge RESET) - begin - if (RESET) begin - CRC_OUT = 0; - end - else if (start_int == 1) begin - CRC_OUT = nextCRC32_D8(data_int, CRC_OUT); - end - else if (LOAD == 1) begin - CRC_OUT = CRC_IN; - end - - - - end - - -/////////////////////////////////////////////////////////////////////// -// File: CRC32_D64.v -// Date: Sun Nov 27 19:32:12 2005 -// -// Copyright (C) 1999-2003 Easics NV. -// This source file may be used and distributed without restriction -// provided that this copyright statement is not removed from the file -// and that any derivative work contains the original copyright notice -// and the associated disclaimer. -// -// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS -// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -// Purpose: Verilog module containing a synthesizable CRC function -// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) -// * data width: 64 -// -// Info: tools@easics.be -// http://www.easics.com -/////////////////////////////////////////////////////////////////////// - - // polynomial: (0 1 2 3 4 5 7 8 10 11 12 16 22 23 26 32) - // data width: 8 - // convention: the first serial data bit is D[7] - function [31:0] nextCRC32_D8; - - input [7:0] Data; - input [31:0] CRC; - - reg [7:0] D; - reg [31:0] C; - reg [31:0] NewCRC; - - begin - - D = Data; - C = CRC; - - NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30]; - NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ - C[31]; - NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ - C[26] ^ C[30] ^ C[31]; - NewCRC[3] = D[7] ^ D[6] ^ D[3] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ - C[26] ^ C[27] ^ C[30] ^ C[31]; - NewCRC[4] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ - C[25] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31]; - NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[2] ^ D[1] ^ D[0] ^ - C[24] ^ C[25] ^ C[26] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ - C[31]; - NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ - C[26] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; - NewCRC[7] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ - C[27] ^ C[28] ^ C[29] ^ C[31]; - NewCRC[8] = D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ - C[27] ^ C[28] ^ C[29]; - NewCRC[9] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ - C[28] ^ C[29] ^ C[30]; - NewCRC[10] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ - C[27] ^ C[29] ^ C[31]; - NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ - C[27] ^ C[28]; - NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ - C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30]; - NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ - C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31]; - NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ - C[28] ^ C[30] ^ C[31]; - NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ - C[29] ^ C[31]; - NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29]; - NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30]; - NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31]; - NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31]; - NewCRC[20] = D[4] ^ C[12] ^ C[28]; - NewCRC[21] = D[5] ^ C[13] ^ C[29]; - NewCRC[22] = D[0] ^ C[14] ^ C[24]; - NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30]; - NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31]; - NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27]; - NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ - C[28] ^ C[30]; - NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ - C[29] ^ C[31]; - NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30]; - NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31]; - NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31]; - NewCRC[31] = D[5] ^ C[23] ^ C[29]; - - nextCRC32_D8 = NewCRC; - - end - - endfunction - -endmodule - Index: trunk/tx_engine/CRC32_D64.v =================================================================== --- trunk/tx_engine/CRC32_D64.v (revision 42) +++ trunk/tx_engine/CRC32_D64.v (nonexistent) @@ -1,310 +0,0 @@ -module CRC32_D64(DATA_IN, CLK, RESET, START, CRC_OUT); - - input [63:0] DATA_IN; - input CLK; - input RESET; - input START; - output [31:0] CRC_OUT; - -// reg [31:0] CRC_FB; - reg [31:0] CRC_OUT; - reg [31:0] CRC_REG; - -reg start_int; -reg startCRC; -wire [63:0] data_del; - - -assign data_del = {DATA_IN[0],DATA_IN[1],DATA_IN[2],DATA_IN[3],DATA_IN[4],DATA_IN[5],DATA_IN[6],DATA_IN[7], - DATA_IN[8],DATA_IN[9],DATA_IN[10],DATA_IN[11],DATA_IN[12],DATA_IN[13],DATA_IN[14],DATA_IN[15], - DATA_IN[16],DATA_IN[17],DATA_IN[18],DATA_IN[19],DATA_IN[20],DATA_IN[21],DATA_IN[22],DATA_IN[23], - DATA_IN[24],DATA_IN[25],DATA_IN[26],DATA_IN[27],DATA_IN[28],DATA_IN[29],DATA_IN[30],DATA_IN[31], - DATA_IN[32],DATA_IN[33],DATA_IN[34],DATA_IN[35],DATA_IN[36],DATA_IN[37],DATA_IN[38],DATA_IN[39], - DATA_IN[40],DATA_IN[41],DATA_IN[42],DATA_IN[43],DATA_IN[44],DATA_IN[45],DATA_IN[46],DATA_IN[47], - DATA_IN[48],DATA_IN[49],DATA_IN[50],DATA_IN[51],DATA_IN[52],DATA_IN[53],DATA_IN[54],DATA_IN[55], - DATA_IN[56],DATA_IN[57],DATA_IN[58],DATA_IN[59],DATA_IN[60],DATA_IN[61],DATA_IN[62],DATA_IN[63]}; - -//assign data_del = 64'h1000000000000000; - -always @(START) -begin - startCRC <= START; -end - -always @(posedge CLK or posedge RESET) - begin - if (RESET) begin - CRC_OUT <= 0; - CRC_REG <= 0; - end - - else if (startCRC == 1) begin - CRC_OUT <= nextCRC32_D64(data_del, CRC_OUT); - end - - end - - -/////////////////////////////////////////////////////////////////////// -// File: CRC32_D64.v -// Date: Sun Nov 27 19:32:12 2005 -// -// Copyright (C) 1999-2003 Easics NV. -// This source file may be used and distributed without restriction -// provided that this copyright statement is not removed from the file -// and that any derivative work contains the original copyright notice -// and the associated disclaimer. -// -// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS -// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -// Purpose: Verilog module containing a synthesizable CRC function -// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) -// * data width: 64 -// -// Info: tools@easics.be -// http://www.easics.com -/////////////////////////////////////////////////////////////////////// - - // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) - // data width: 64 - // convention: the first serial data bit is D[63] - function [31:0] nextCRC32_D64; - - input [63:0] Data; - input [31:0] CRC; - - reg [63:0] D; - reg [31:0] C; - reg [31:0] NewCRC; - - begin - - D = Data; - C = CRC; - - NewCRC[0] = D[63] ^ D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[54] ^ D[53] ^ - D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[37] ^ D[34] ^ - D[32] ^ D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ - D[24] ^ D[16] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[0] ^ - C[0] ^ C[2] ^ C[5] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ - C[18] ^ C[21] ^ C[22] ^ C[23] ^ C[26] ^ C[28] ^ C[29] ^ - C[31]; - NewCRC[1] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ - D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[38] ^ - D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[28] ^ D[27] ^ D[24] ^ - D[17] ^ D[16] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[7] ^ - D[6] ^ D[1] ^ D[0] ^ C[1] ^ C[2] ^ C[3] ^ C[5] ^ C[6] ^ - C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ - C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31]; - NewCRC[2] = D[59] ^ D[58] ^ D[57] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ - D[44] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^ D[32] ^ - D[31] ^ D[30] ^ D[26] ^ D[24] ^ D[18] ^ D[17] ^ D[16] ^ - D[14] ^ D[13] ^ D[9] ^ D[8] ^ D[7] ^ D[6] ^ D[2] ^ - D[1] ^ D[0] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ - C[12] ^ C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[25] ^ C[26] ^ - C[27]; - NewCRC[3] = D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[54] ^ D[53] ^ D[52] ^ - D[45] ^ D[40] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[33] ^ - D[32] ^ D[31] ^ D[27] ^ D[25] ^ D[19] ^ D[18] ^ D[17] ^ - D[15] ^ D[14] ^ D[10] ^ D[9] ^ D[8] ^ D[7] ^ D[3] ^ - D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ - C[8] ^ C[13] ^ C[20] ^ C[21] ^ C[22] ^ C[24] ^ C[26] ^ - C[27] ^ C[28]; - NewCRC[4] = D[63] ^ D[59] ^ D[58] ^ D[57] ^ D[50] ^ D[48] ^ D[47] ^ - D[46] ^ D[45] ^ D[44] ^ D[41] ^ D[40] ^ D[39] ^ D[38] ^ - D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[25] ^ D[24] ^ D[20] ^ - D[19] ^ D[18] ^ D[15] ^ D[12] ^ D[11] ^ D[8] ^ D[6] ^ - D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[1] ^ C[6] ^ C[7] ^ C[8] ^ - C[9] ^ C[12] ^ C[13] ^ C[14] ^ C[15] ^ C[16] ^ C[18] ^ - C[25] ^ C[26] ^ C[27] ^ C[31]; - NewCRC[5] = D[63] ^ D[61] ^ D[59] ^ D[55] ^ D[54] ^ D[53] ^ D[51] ^ - D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[42] ^ D[41] ^ D[40] ^ - D[39] ^ D[37] ^ D[29] ^ D[28] ^ D[24] ^ D[21] ^ D[20] ^ - D[19] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ - D[3] ^ D[1] ^ D[0] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ - C[12] ^ C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ C[22] ^ - C[23] ^ C[27] ^ C[29] ^ C[31]; - NewCRC[6] = D[62] ^ D[60] ^ D[56] ^ D[55] ^ D[54] ^ D[52] ^ D[51] ^ - D[50] ^ D[47] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ D[40] ^ - D[38] ^ D[30] ^ D[29] ^ D[25] ^ D[22] ^ D[21] ^ D[20] ^ - D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^ - D[2] ^ D[1] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ - C[13] ^ C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[23] ^ - C[24] ^ C[28] ^ C[30]; - NewCRC[7] = D[60] ^ D[58] ^ D[57] ^ D[56] ^ D[54] ^ D[52] ^ D[51] ^ - D[50] ^ D[47] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ - D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[29] ^ D[28] ^ D[25] ^ - D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[16] ^ D[15] ^ D[10] ^ - D[8] ^ D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[0] ^ C[2] ^ - C[5] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ - C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[24] ^ C[25] ^ - C[26] ^ C[28]; - NewCRC[8] = D[63] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[52] ^ D[51] ^ - D[50] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[40] ^ D[38] ^ - D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[31] ^ D[28] ^ - D[23] ^ D[22] ^ D[17] ^ D[12] ^ D[11] ^ D[10] ^ D[8] ^ - D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ - C[5] ^ C[6] ^ C[8] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ - C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ - C[31]; - NewCRC[9] = D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^ - D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ D[39] ^ D[38] ^ - D[36] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[29] ^ D[24] ^ - D[23] ^ D[18] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[5] ^ - D[4] ^ D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ - C[6] ^ C[7] ^ C[9] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ - C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[26] ^ C[28] ^ C[29]; - NewCRC[10] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ - D[52] ^ D[50] ^ D[42] ^ D[40] ^ D[39] ^ D[36] ^ D[35] ^ - D[33] ^ D[32] ^ D[31] ^ D[29] ^ D[28] ^ D[26] ^ D[19] ^ - D[16] ^ D[14] ^ D[13] ^ D[9] ^ D[5] ^ D[3] ^ D[2] ^ - D[0] ^ C[0] ^ C[1] ^ C[3] ^ C[4] ^ C[7] ^ C[8] ^ C[10] ^ - C[18] ^ C[20] ^ C[23] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^ - C[30] ^ C[31]; - NewCRC[11] = D[59] ^ D[58] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ D[51] ^ - D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ - D[40] ^ D[36] ^ D[33] ^ D[31] ^ D[28] ^ D[27] ^ D[26] ^ - D[25] ^ D[24] ^ D[20] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ - D[12] ^ D[9] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[1] ^ C[4] ^ - C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^ - C[18] ^ C[19] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ C[26] ^ - C[27]; - NewCRC[12] = D[63] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ D[53] ^ - D[52] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[42] ^ - D[41] ^ D[31] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[18] ^ - D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[5] ^ - D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[9] ^ C[10] ^ C[14] ^ - C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ - C[24] ^ C[25] ^ C[27] ^ C[29] ^ C[31]; - NewCRC[13] = D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[54] ^ D[53] ^ - D[52] ^ D[51] ^ D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[42] ^ - D[32] ^ D[31] ^ D[28] ^ D[25] ^ D[22] ^ D[19] ^ D[18] ^ - D[16] ^ D[14] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ - D[3] ^ D[2] ^ D[1] ^ C[0] ^ C[10] ^ C[11] ^ C[15] ^ - C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ - C[25] ^ C[26] ^ C[28] ^ C[30]; - NewCRC[14] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ D[54] ^ - D[53] ^ D[52] ^ D[51] ^ D[49] ^ D[48] ^ D[44] ^ D[43] ^ - D[33] ^ D[32] ^ D[29] ^ D[26] ^ D[23] ^ D[20] ^ D[19] ^ - D[17] ^ D[15] ^ D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ - D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[1] ^ C[11] ^ C[12] ^ - C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ - C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31]; - NewCRC[15] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ - D[53] ^ D[52] ^ D[50] ^ D[49] ^ D[45] ^ D[44] ^ D[34] ^ - D[33] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[20] ^ D[18] ^ - D[16] ^ D[15] ^ D[12] ^ D[9] ^ D[8] ^ D[7] ^ D[5] ^ - D[4] ^ D[3] ^ C[1] ^ C[2] ^ C[12] ^ C[13] ^ C[17] ^ - C[18] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ - C[27] ^ C[28] ^ C[30]; - NewCRC[16] = D[57] ^ D[56] ^ D[51] ^ D[48] ^ D[47] ^ D[46] ^ D[44] ^ - D[37] ^ D[35] ^ D[32] ^ D[30] ^ D[29] ^ D[26] ^ D[24] ^ - D[22] ^ D[21] ^ D[19] ^ D[17] ^ D[13] ^ D[12] ^ D[8] ^ - D[5] ^ D[4] ^ D[0] ^ C[0] ^ C[3] ^ C[5] ^ C[12] ^ C[14] ^ - C[15] ^ C[16] ^ C[19] ^ C[24] ^ C[25]; - NewCRC[17] = D[58] ^ D[57] ^ D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[45] ^ - D[38] ^ D[36] ^ D[33] ^ D[31] ^ D[30] ^ D[27] ^ D[25] ^ - D[23] ^ D[22] ^ D[20] ^ D[18] ^ D[14] ^ D[13] ^ D[9] ^ - D[6] ^ D[5] ^ D[1] ^ C[1] ^ C[4] ^ C[6] ^ C[13] ^ C[15] ^ - C[16] ^ C[17] ^ C[20] ^ C[25] ^ C[26]; - NewCRC[18] = D[59] ^ D[58] ^ D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[46] ^ - D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[31] ^ D[28] ^ D[26] ^ - D[24] ^ D[23] ^ D[21] ^ D[19] ^ D[15] ^ D[14] ^ D[10] ^ - D[7] ^ D[6] ^ D[2] ^ C[0] ^ C[2] ^ C[5] ^ C[7] ^ C[14] ^ - C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[26] ^ C[27]; - NewCRC[19] = D[60] ^ D[59] ^ D[54] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ - D[40] ^ D[38] ^ D[35] ^ D[33] ^ D[32] ^ D[29] ^ D[27] ^ - D[25] ^ D[24] ^ D[22] ^ D[20] ^ D[16] ^ D[15] ^ D[11] ^ - D[8] ^ D[7] ^ D[3] ^ C[0] ^ C[1] ^ C[3] ^ C[6] ^ C[8] ^ - C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[27] ^ C[28]; - NewCRC[20] = D[61] ^ D[60] ^ D[55] ^ D[52] ^ D[51] ^ D[50] ^ D[48] ^ - D[41] ^ D[39] ^ D[36] ^ D[34] ^ D[33] ^ D[30] ^ D[28] ^ - D[26] ^ D[25] ^ D[23] ^ D[21] ^ D[17] ^ D[16] ^ D[12] ^ - D[9] ^ D[8] ^ D[4] ^ C[1] ^ C[2] ^ C[4] ^ C[7] ^ C[9] ^ - C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[28] ^ C[29]; - NewCRC[21] = D[62] ^ D[61] ^ D[56] ^ D[53] ^ D[52] ^ D[51] ^ D[49] ^ - D[42] ^ D[40] ^ D[37] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ - D[27] ^ D[26] ^ D[24] ^ D[22] ^ D[18] ^ D[17] ^ D[13] ^ - D[10] ^ D[9] ^ D[5] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10] ^ - C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[29] ^ C[30]; - NewCRC[22] = D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ - D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ - D[37] ^ D[36] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ - D[26] ^ D[24] ^ D[23] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^ - D[12] ^ D[11] ^ D[9] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ - C[5] ^ C[6] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ - C[16] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^ - C[30]; - NewCRC[23] = D[62] ^ D[60] ^ D[59] ^ D[56] ^ D[55] ^ D[54] ^ D[50] ^ - D[49] ^ D[47] ^ D[46] ^ D[42] ^ D[39] ^ D[38] ^ D[36] ^ - D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ D[26] ^ D[20] ^ - D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[13] ^ D[9] ^ D[6] ^ - D[1] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ C[6] ^ C[7] ^ C[10] ^ - C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[22] ^ C[23] ^ C[24] ^ - C[27] ^ C[28] ^ C[30]; - NewCRC[24] = D[63] ^ D[61] ^ D[60] ^ D[57] ^ D[56] ^ D[55] ^ D[51] ^ - D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[40] ^ D[39] ^ D[37] ^ - D[36] ^ D[35] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[21] ^ - D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[14] ^ D[10] ^ D[7] ^ - D[2] ^ D[1] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[7] ^ C[8] ^ - C[11] ^ C[15] ^ C[16] ^ C[18] ^ C[19] ^ C[23] ^ C[24] ^ - C[25] ^ C[28] ^ C[29] ^ C[31]; - NewCRC[25] = D[62] ^ D[61] ^ D[58] ^ D[57] ^ D[56] ^ D[52] ^ D[51] ^ - D[49] ^ D[48] ^ D[44] ^ D[41] ^ D[40] ^ D[38] ^ D[37] ^ - D[36] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[22] ^ D[21] ^ - D[19] ^ D[18] ^ D[17] ^ D[15] ^ D[11] ^ D[8] ^ D[3] ^ - D[2] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[12] ^ - C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[24] ^ C[25] ^ C[26] ^ - C[29] ^ C[30]; - NewCRC[26] = D[62] ^ D[61] ^ D[60] ^ D[59] ^ D[57] ^ D[55] ^ D[54] ^ - D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[44] ^ D[42] ^ D[41] ^ - D[39] ^ D[38] ^ D[31] ^ D[28] ^ D[26] ^ D[25] ^ D[24] ^ - D[23] ^ D[22] ^ D[20] ^ D[19] ^ D[18] ^ D[10] ^ D[6] ^ - D[4] ^ D[3] ^ D[0] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[12] ^ - C[15] ^ C[16] ^ C[17] ^ C[20] ^ C[22] ^ C[23] ^ C[25] ^ - C[27] ^ C[28] ^ C[29] ^ C[30]; - NewCRC[27] = D[63] ^ D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[56] ^ D[55] ^ - D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[45] ^ D[43] ^ D[42] ^ - D[40] ^ D[39] ^ D[32] ^ D[29] ^ D[27] ^ D[26] ^ D[25] ^ - D[24] ^ D[23] ^ D[21] ^ D[20] ^ D[19] ^ D[11] ^ D[7] ^ - D[5] ^ D[4] ^ D[1] ^ C[0] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ - C[13] ^ C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[23] ^ C[24] ^ - C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; - NewCRC[28] = D[63] ^ D[62] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ - D[51] ^ D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ - D[40] ^ D[33] ^ D[30] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ - D[24] ^ D[22] ^ D[21] ^ D[20] ^ D[12] ^ D[8] ^ D[6] ^ - D[5] ^ D[2] ^ C[1] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ - C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[24] ^ C[25] ^ - C[27] ^ C[29] ^ C[30] ^ C[31]; - NewCRC[29] = D[63] ^ D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^ - D[51] ^ D[50] ^ D[47] ^ D[45] ^ D[44] ^ D[42] ^ D[41] ^ - D[34] ^ D[31] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^ - D[23] ^ D[22] ^ D[21] ^ D[13] ^ D[9] ^ D[7] ^ D[6] ^ - D[3] ^ C[2] ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15] ^ - C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ - C[30] ^ C[31]; - NewCRC[30] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ D[52] ^ - D[51] ^ D[48] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[35] ^ - D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[24] ^ - D[23] ^ D[22] ^ D[14] ^ D[10] ^ D[8] ^ D[7] ^ D[4] ^ - C[0] ^ C[3] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ C[16] ^ - C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^ - C[31]; - NewCRC[31] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[53] ^ D[52] ^ - D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[36] ^ D[33] ^ - D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[25] ^ D[24] ^ - D[23] ^ D[15] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ C[1] ^ - C[4] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[20] ^ - C[21] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ C[30]; - - nextCRC32_D64 = NewCRC; - - end - - endfunction - -endmodule - Index: trunk/tx_engine/TransmitTop_tb.v =================================================================== --- trunk/tx_engine/TransmitTop_tb.v (revision 42) +++ trunk/tx_engine/TransmitTop_tb.v (nonexistent) @@ -1,161 +0,0 @@ -`include "TransmitTop.v" -module TransmitTop_tb(); - -//Input from user logic -reg [63:0] TX_DATA; -reg [63:0] TX_DATA_int; -reg [7:0] TX_DATA_VALID; // To accept the data valid to be available -reg Append_last_bit; -reg TX_CLK; -reg RESET; -reg TX_START; // This signify the first frame of data -reg TX_UNDERRUN; // this will cause an error to be injected into the data -reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal - -//input to transmit fault signals -reg RXTXLINKFAULT; -reg LOCALLINKFAULT; -reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data -reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent - -//apply pause timing -reg [15:0] FC_TX_PAUSEDATA; -reg FC_TX_PAUSEVALID; - -//apply configuration value -reg [31:0] TX_CFG_REG_VALUE; -reg TX_CFG_REG_VALID; - -//output to stat register -wire TX_STATS_VALID; -wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats -wire [63:0] TXD; -wire [7:0] TXC; -wire TX_ACK; -reg D_START; - -reg START_TX_BITS; - -// Initialize all variables -initial begin - Append_last_bit = 0; - TX_CLK = 1; // initial value of clock - RESET <= 0; // initial value of reset - TX_START <= 0; // initial value of enable - TX_DATA_VALID <= 8'h00; - D_START = 0; - FC_TX_PAUSEVALID <= 0; - FC_TX_PAUSEDATA <= 0; - FC_TRANS_PAUSEDATA <= 0; - FC_TRANS_PAUSEVAL <= 0; - TX_UNDERRUN = 0; - #5 RESET <= 1; // Assert the reset - #10 RESET <= 0; // De-assert the reset - - #15 TX_START <= 1; - TX_DATA_VALID <= 8'hFF; - D_START <= 1; - #20 TX_START <= 0; - #400 //TX_DATA_VALID <= 8'h00; - //FC_TX_PAUSEVALID <= 1; - //FC_TX_PAUSEDATA <= 30; - // FC_TRANS_PAUSEDATA <= 30; - // FC_TRANS_PAUSEVAL <= 1; - TX_DATA_VALID <= 8'h7f; - #10 TX_DATA_VALID <= 8'h00; - D_START = 0; - //FC_TX_PAUSEVALID <= 0; - //FC_TX_PAUSEDATA <= 0; - // FC_TRANS_PAUSEDATA <= 0; - // FC_TRANS_PAUSEVAL <= 0; - #20 TX_START <= 1; - TX_DATA_VALID <= 8'hFF; - D_START = 1; - #20 TX_START <= 0; - #400 TX_DATA_VALID <= 8'h00; - #10 TX_DATA_VALID <= 8'h00; - D_START = 0; - #1300 $finish; // Terminate simulation -end - -always @(posedge D_START or posedge TX_CLK) -begin - if (D_START == 0) begin - TX_DATA = 64'h0000000000000000; - end - //else if (TX_DATA_VALID == 8'h07) begin - // TX_DATA = 64'h000000000077FFCC; - //end - else if (Append_last_bit == 1) begin -// TX_DATA = 64'h202020202077FFCC; - TX_DATA = 64'h000000000077FFCC; - end - else if (START_TX_BITS == 1) begin - TX_DATA = TX_DATA + 1; - end - else begin - TX_DATA = 64'h0000000000000001; - end -end - - - -always @(TX_DATA) -begin - if (TX_DATA == 2) begin - TX_DATA_int[31:0] <= TX_DATA[31:0]; - TX_DATA_int[47:32] <= 300; - TX_DATA_int[63:48] <= TX_DATA[63:48]; - end - else begin - TX_DATA_int <= TX_DATA; - end - -end - - -always @(TX_ACK | TX_START) -begin - if (TX_ACK) begin - START_TX_BITS = 1; - end - else if (TX_START) begin - START_TX_BITS = 0; - end -end - - -// Clock generator -always begin - #5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks -end - -// Connect DUT to test bench -TRANSMIT_TOP U_top_module ( -TX_DATA_int, -TX_DATA_VALID, -TX_CLK, -RESET, -TX_START, -TX_ACK, -TX_UNDERRUN, -TX_IFG_DELAY, -RXTXLINKFAULT, -LOCALLINKFAULT, -TX_STATS_VALID, -TXSTATREGPLUS, -TXD, -TXC, -FC_TRANS_PAUSEDATA, -FC_TRANS_PAUSEVAL, -FC_TX_PAUSEDATA, -FC_TX_PAUSEVALID, -TX_CFG_REG_VALUE, -TX_CFG_REG_VALID -); - - - - -endmodule - Index: trunk/tx_engine/ack_counter.v =================================================================== --- trunk/tx_engine/ack_counter.v (revision 42) +++ trunk/tx_engine/ack_counter.v (nonexistent) @@ -1,89 +0,0 @@ -module ack_counter ( -clock , // 156 MHz clock -reset , // active high, asynchronous Reset input -ready, -tx_start , // Active high tx_start signal for counter -max_count, //16 bit reg for the maximum count to generate the ack signal -tx_ack // Active high signal -); - -// Ports declaration -input clock; -input reset; -input ready; -input tx_start; -input [15:0] max_count; - -output tx_ack; - -// Wire connections -//Input -wire clock; -wire reset; -wire ready; -wire tx_start; -wire [15:0] max_count; - -//Output -reg tx_ack; - - - -//Internal wires -reg start_count; -reg start_count_del; -reg [15:0] counter; - - -always @ (reset or tx_start or counter or max_count) -begin - - if (reset) begin - start_count <= 0; - end - - else if (tx_start) begin - start_count <= 1; - end - - else if ((counter == max_count) & !ready) begin //& !ready - start_count <= 0; - end - -end - - -always @ (posedge clock or posedge reset) -begin - - if (reset) begin - counter <= 0; - end - - else if (counter == max_count) begin - counter <= 0; - end - - else if (start_count) begin - counter <= counter + 1; - end - -end - - -always @ (posedge clock or posedge reset) -begin - - if (reset) begin - start_count_del <= 0; - tx_ack <= 0; - end - else begin - start_count_del <= start_count; - tx_ack <= ~start_count & start_count_del; - end - -end - -endmodule // End of Module - Index: trunk/tx_engine/debug_large.do =================================================================== --- trunk/tx_engine/debug_large.do (revision 42) +++ trunk/tx_engine/debug_large.do (nonexistent) @@ -1,119 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_CLK -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/RESET -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_START -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_UNDERRUN -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_ACK -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_tb/U_top_module/TXD -add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_tb/U_top_module/TXC -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/FC_TRANS_PAUSEDATA -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/FC_TRANS_PAUSEVAL -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/FC_TX_PAUSEDATA -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/FC_TX_PAUSEVALID -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/FRAME_START -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/reset_int -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/DELAY_ACK -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_REG -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL1 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL2 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL3 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL4 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL5 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL6 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL7 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL8 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL9 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL10 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL11 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL12 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL13 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL14 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL15 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL1 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL2 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL3 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL4 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL5 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL6 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL7 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL8 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL9 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL10 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL11 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL12 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL13 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL14 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL15 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/OVERFLOW_VALID -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/OVERFLOW_DATA -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_REG -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DELAY -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/CRC_32_64 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/BYTE_COUNTER -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/frame_start_del -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/transmit_pause_frame_del -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/transmit_pause_frame -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/append_start_pause -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/append_start_pause_del -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/transmit_pause_frame_valid -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/reset_err_pause -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/load_CRC8 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/tx_data_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/start_CRC8 -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/START_CRC8_DEL -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/append_end_frame -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/insert_error -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_tx_data_valid -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_tx_data -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_CRC64 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_valid -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/load_final_CRC -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/final_byte_count -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/byte_count_reg -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/CRC_OUT -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/append_reg -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/length_register -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/tx_undderrun_int -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/MAX_FRAME_SIZE -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/vlan_enabled_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/jumbo_enabled_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/tx_enabled_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/fcs_enabled_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/reset_tx_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/read_ifg_int -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/apply_pause_delay -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_pause_frame -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXD_PAUSE_DEL0 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXD_PAUSE_DEL1 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXD_PAUSE_DEL2 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXC_PAUSE_DEL0 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXC_PAUSE_DEL1 -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXC_PAUSE_DEL2 -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/PAUSEVAL_DEL -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/PAUSEVAL_DEL1 -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/PAUSEVAL_DEL2 -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/RESET_ERR_PAUSE -add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/set_pause_stats -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_transmit_pause_value -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/pause_frame_counter -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/shift_pause_data -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/shift_pause_valid -add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/shift_pause_valid_del -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {480 ns} 0} -WaveRestoreZoom {225 ns} {617 ns} -configure wave -namecolwidth 403 -configure wave -valuecolwidth 182 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0