URL
https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk
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Rev 42 → Rev 43
/trunk/rtl/verilog/generic_spram.v
67,8 → 67,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
|
76,7 → 74,7
|
//`define VENDOR_XILINX |
//`define VENDOR_ALTERA |
//`define VENDOR_FPGA |
`define VENDOR_FPGA |
|
module generic_spram( |
// Generic synchronous single-port RAM interface |
112,21 → 110,25
// This code has been tested using LeonardoSpectrum and Synplicity. |
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs. |
// |
reg [dw-1 :0] mem [(1<<aw) -1:0]; |
reg [aw-1:0] raddr; |
|
always@(posedge clk) |
begin |
// read operation |
raddr <= #1 addr; // read address needs to be registered to read clock |
// NOTE: |
// 'synthesis syn_ramstyle="block_ram"' is a Synplify attribute. |
// It instructs Synplify to map to BlockRAMs instead of the default SelectRAMs |
|
// write operation |
if (we && ce) |
mem[addr] <= #1 di; |
end |
reg [dw-1:0] mem [(1<<aw) -1:0] /* synthesis syn_ramstyle="block_ram" */; |
reg [aw-1:0] ra; |
|
assign #1 do = mem[raddr]; |
// read operation |
always @(posedge clk) |
if (ce) |
ra <= #1 addr; // read address needs to be registered to read clock |
|
assign #1 do = mem[ra]; |
|
// write operation |
always @(posedge clk) |
if (we && ce) |
mem[addr] <= #1 di; |
`else |
|
`ifdef VENDOR_XILINX |
/trunk/rtl/verilog/vga_wb_master.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: vga_wb_master.v,v 1.11 2002-04-20 10:02:39 rherveille Exp $ |
// $Id: vga_wb_master.v,v 1.12 2003-03-18 21:45:48 rherveille Exp $ |
// |
// $Date: 2002-04-20 10:02:39 $ |
// $Revision: 1.11 $ |
// $Date: 2003-03-18 21:45:48 $ |
// $Revision: 1.12 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2002/04/20 10:02:39 rherveille |
// Changed video timing generator. |
// Changed wishbone master vertical gate count code. |
// Fixed a potential bug in the wishbone slave (cursor color register readout). |
// |
// Revision 1.10 2002/03/28 04:59:25 rherveille |
// Fixed two small bugs that only showed up when the hardware cursors were disabled |
// |
72,7 → 77,8
`include "timescale.v" |
`include "vga_defines.v" |
|
module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint, |
module vga_wb_master (clk_i, rst_i, nrst_i, |
cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint, |
ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw, |
cursor0_en, cursor0_res, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_o, cc0_dat_i, |
cursor1_en, cursor1_res, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_o, cc1_dat_i, |
90,8 → 96,10
reg cyc_o; |
output stb_o; // strobe ouput |
reg stb_o; |
output cab_o; // consecutive address burst output |
reg cab_o; |
output [ 3:0] cti_o; // cycle type id |
reg [3:0] cti_o; |
output [ 1:0] bte_o; // burst type extension |
reg [1:0] bte_o; |
output we_o; // write enable output |
reg we_o; |
output [31:0] adr_o; // address output |
155,7 → 163,7
// |
|
reg vmem_acc; // video memory access |
wire nvmem_req, vmem_ack; // NOT video memory access request // video memory access acknowledge |
wire vmem_req_n, vmem_ack; // NOT video memory access request // video memory access acknowledge |
|
wire ImDone; // Done reading image from video mem |
reg dImDone; // delayed ImDone |
191,8 → 199,8
// |
|
// generate synchronous clear |
always@(posedge clk_i) |
sclr <= #1 ~ctrl_ven; |
always @(posedge clk_i) |
sclr <= #1 ~ctrl_ven; |
|
// |
// WISHBONE block |
200,24 → 208,24
reg [ 2:0] burst_cnt; // video memory burst access counter |
wire burst_done; // completed burst access to video mem |
reg sel_VBA; // select video memory base address |
reg [31:2] vmemA; // video memory address |
reg [31:2] vmemA; // video memory address |
|
// wishbone access controller, video memory access request has highest priority (try to keep fifo full) |
always@(posedge clk_i) |
if (sclr) |
vmem_acc <= #1 1'b0; // video memory access request |
else |
vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc; |
always @(posedge clk_i) |
if (sclr) |
vmem_acc <= #1 1'b0; // video memory access request |
else |
vmem_acc <= #1 (!vmem_req_n | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc; |
|
always@(posedge clk_i) |
if (sclr) |
cur_acc <= #1 1'b0; // cursor processor memory access request |
else |
cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done; |
always @(posedge clk_i) |
if (sclr) |
cur_acc <= #1 1'b0; // cursor processor memory access request |
else |
cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done; |
|
|
assign vmem_ack = ack_i & vmem_acc; |
assign cur_ack = ack_i & cur_acc; |
assign vmem_ack = ack_i & stb_o & vmem_acc; |
assign cur_ack = ack_i & stb_o & cur_acc; |
assign sint = err_i; // Non recoverable error, interrupt host system |
|
|
224,11 → 232,11
// select active memory page |
assign vmem_switch = ImDoneStrb; |
|
always@(posedge clk_i) |
if (sclr) |
sel_VBA <= #1 1'b0; |
else if (ctrl_vbsw) |
sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled) |
always @(posedge clk_i) |
if (sclr) |
sel_VBA <= #1 1'b0; |
else if (ctrl_vbsw) |
sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled) |
|
assign stat_avmp = sel_VBA; // assign output |
|
249,25 → 257,25
|
// |
// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay |
always@(posedge clk_i) |
if (sclr) |
dImDoneFifoQ <= #1 1'b0; |
else if (data_fifo_rreq) |
dImDoneFifoQ <= #1 ImDoneFifoQ; |
always @(posedge clk_i) |
if (sclr) |
dImDoneFifoQ <= #1 1'b0; |
else if (data_fifo_rreq) |
dImDoneFifoQ <= #1 ImDoneFifoQ; |
|
always@(posedge clk_i) |
if (sclr) |
ddImDoneFifoQ <= #1 1'b0; |
else |
ddImDoneFifoQ <= #1 dImDoneFifoQ; |
always @(posedge clk_i) |
if (sclr) |
ddImDoneFifoQ <= #1 1'b0; |
else |
ddImDoneFifoQ <= #1 dImDoneFifoQ; |
|
assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ; |
|
always@(posedge clk_i) |
if (sclr) |
stat_acmp <= #1 1'b0; |
else if (ctrl_cbsw) |
stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled) |
always @(posedge clk_i) |
if (sclr) |
stat_acmp <= #1 1'b0; |
else if (ctrl_cbsw) |
stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled) |
|
// |
// generate clut-address |
279,16 → 287,16
assign burst_cnt_val = {1'b0, burst_cnt} -4'h1; |
assign burst_done = burst_cnt_val[3]; |
|
always@(posedge clk_i) |
if ( (burst_done & vmem_ack) | !vmem_acc) |
case (ctrl_vbl) // synopsis full_case parallel_case |
2'b00: burst_cnt <= #1 3'b000; // burst length 1 |
2'b01: burst_cnt <= #1 3'b001; // burst length 2 |
2'b10: burst_cnt <= #1 3'b011; // burst length 4 |
2'b11: burst_cnt <= #1 3'b111; // burst length 8 |
endcase |
else if(vmem_ack) |
burst_cnt <= #1 burst_cnt_val[2:0]; |
always @(posedge clk_i) |
if ( (burst_done & vmem_ack) | !vmem_acc) |
case (ctrl_vbl) // synopsis full_case parallel_case |
2'b00: burst_cnt <= #1 3'b000; // burst length 1 |
2'b01: burst_cnt <= #1 3'b001; // burst length 2 |
2'b10: burst_cnt <= #1 3'b011; // burst length 4 |
2'b11: burst_cnt <= #1 3'b111; // burst length 8 |
endcase |
else if(vmem_ack) |
burst_cnt <= #1 burst_cnt_val[2:0]; |
|
// |
// generate image counters |
302,78 → 310,71
|
wire hdone = hgate_cnt_val[16] & vmem_ack; // ???? |
|
always@(hgate_cnt or hgate_div_cnt or ctrl_cd) |
begin |
hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1; |
|
if (ctrl_cd != 2'b10) |
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1; |
else if ( hgate_div_val[2] ) |
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1; |
else |
hgate_cnt_val = {1'b0, hgate_cnt}; |
end |
always @(hgate_cnt or hgate_div_cnt or ctrl_cd) |
begin |
hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1; |
|
always@(posedge clk_i) |
if (sclr) |
begin |
case(ctrl_cd) // synopsys full_case parallel_case |
2'b00: // 8bpp |
hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle |
2'b01: //16bpp |
hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle |
2'b10: //24bpp |
hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle |
2'b11: //32bpp |
hgate_cnt <= #1 Thgate; // 1 pixel per cycle |
endcase |
if (ctrl_cd != 2'b10) |
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1; |
else if ( hgate_div_val[2] ) |
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1; |
else |
hgate_cnt_val = {1'b0, hgate_cnt}; |
end |
|
hgate_div_cnt <= 2'b10; |
end |
else if (vmem_ack) |
if (hdone) |
begin |
case(ctrl_cd) // synopsys full_case parallel_case |
2'b00: // 8bpp |
hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle |
2'b01: //16bpp |
hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle |
2'b10: //24bpp |
hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle |
2'b11: //32bpp |
hgate_cnt <= #1 Thgate; // 1 pixel per cycle |
endcase |
hgate_div_cnt <= #1 2'b10; |
end |
else //if (vmem_ack) |
begin |
hgate_cnt <= #1 hgate_cnt_val[15:0]; |
always @(posedge clk_i) |
if (sclr) |
begin |
case(ctrl_cd) // synopsys full_case parallel_case |
2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle |
2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle |
2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle |
2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle |
endcase |
|
if ( hgate_div_val[2] ) |
hgate_div_cnt <= #1 2'b10; |
else |
hgate_div_cnt <= #1 hgate_div_val[1:0]; |
end |
hgate_div_cnt <= 2'b10; |
end |
else if (vmem_ack) |
if (hdone) |
begin |
case(ctrl_cd) // synopsys full_case parallel_case |
2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle |
2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle |
2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle |
2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle |
endcase |
|
hgate_div_cnt <= 2'b10; |
end |
else //if (vmem_ack) |
begin |
hgate_cnt <= #1 hgate_cnt_val[15:0]; |
|
if ( hgate_div_val[2] ) |
hgate_div_cnt <= #1 2'b10; |
else |
hgate_div_cnt <= #1 hgate_div_val[1:0]; |
end |
|
// vgate counter |
reg [15:0] vgate_cnt; |
wire vdone = ~|vgate_cnt[15:1] & vgate_cnt[0]; |
|
always@(posedge clk_i) |
if (sclr || ImDoneStrb) |
vgate_cnt <= #1 Tvgate; |
else if (hdone) |
vgate_cnt <= #1 vgate_cnt -16'h1; |
always @(posedge clk_i) |
if (sclr || ImDoneStrb) |
vgate_cnt <= #1 Tvgate; |
else if (hdone) |
vgate_cnt <= #1 vgate_cnt -16'h1; |
|
assign ImDone = hdone & vdone; |
|
assign ImDoneStrb = ImDone & !dImDone; |
|
always@(posedge clk_i) |
begin |
dImDone <= #1 ImDone; |
dImDoneStrb <= #1 ImDoneStrb; |
end |
always @(posedge clk_i) |
begin |
dImDone <= #1 ImDone; |
dImDoneStrb <= #1 ImDoneStrb; |
end |
|
// |
// generate addresses |
380,49 → 381,49
// |
|
// select video memory base address |
always@(posedge clk_i) |
if (dImDoneStrb | sclr) |
if (!sel_VBA) |
vmemA <= #1 VBAa; |
else |
vmemA <= #1 VBAb; |
else if (vmem_ack) |
vmemA <= #1 vmemA +30'h1; |
always @(posedge clk_i) |
if (dImDoneStrb | sclr) |
if (!sel_VBA) |
vmemA <= #1 VBAa; |
else |
vmemA <= #1 VBAb; |
else if (vmem_ack) |
vmemA <= #1 vmemA +30'h1; |
|
|
//////////////////////////////////// |
// hardware cursor signals section |
// |
always@(posedge clk_i) |
if (ImDone) |
cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority |
always @(posedge clk_i) |
if (ImDone) |
cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority |
|
always@(posedge clk_i) |
always @(posedge clk_i) |
if (sclr) |
begin |
ld_cursor0 <= #1 1'b0; |
ld_cursor1 <= #1 1'b0; |
end |
begin |
ld_cursor0 <= #1 1'b0; |
ld_cursor1 <= #1 1'b0; |
end |
else |
begin |
ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel)); |
ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel)); |
end |
begin |
ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel)); |
ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel)); |
end |
|
// select cursor base address |
always@(posedge clk_i) |
if (!cur_acc) |
cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba; |
always @(posedge clk_i) |
if (!cur_acc) |
cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba; |
|
// generate pattern offset |
wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1; |
assign cur_done = next_cursor_adr[9]; |
assign cur_done = next_cursor_adr[9] & cur_ack; |
|
always@(posedge clk_i) |
if (!cur_acc) |
cursor_adr <= #1 9'h0; |
else if (cur_ack) |
cursor_adr <= #1 next_cursor_adr; |
always @(posedge clk_i) |
if (!cur_acc) |
cursor_adr <= #1 9'h0; |
else if (cur_ack) |
cursor_adr <= #1 next_cursor_adr; |
|
// generate cursor buffers write enable signals |
assign cursor1_we = cur_ack & !cur_acc_sel; |
433,36 → 434,52
// generate wishbone signals |
// |
assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00}; |
wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone || |
wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & vmem_req_n) & !ImDone || |
cur_acc & !cur_done; |
|
always@(posedge clk_i or negedge nrst_i) |
if (!nrst_i) |
begin |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
sel_o <= #1 4'b1111; |
cab_o <= #1 1'b0; |
we_o <= #1 1'b0; |
end |
else |
if (rst_i) |
begin |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
sel_o <= #1 4'b1111; |
cab_o <= #1 1'b0; |
we_o <= #1 1'b0; |
end |
else |
begin |
cyc_o <= #1 wb_cycle; |
stb_o <= #1 wb_cycle; |
sel_o <= #1 4'b1111; // only 32bit accesses are supported |
cab_o <= #1 wb_cycle; |
we_o <= #1 1'b0; // read only |
end |
wire [2:0] cti_vid = (burst_cnt == 3'h1) ? 3'b111 : 3'b010; |
wire [2:0] cti_cur = &next_cursor_adr[8:0] ? 3'b111 : 3'b010; |
reg [2:0] cti; |
always @(ctrl_vbl or cur_acc or cti_cur or cti_vid) |
case (ctrl_vbl) |
3'b000: cti <= #1 3'b000; // wishbone classic cycle |
|
default: cti <= #1 cur_acc ? cti_cur : cti_vid; |
endcase |
|
always @(posedge clk_i or negedge nrst_i) |
if (!nrst_i) |
begin |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
sel_o <= #1 4'b1111; |
cti_o <= #1 3'b000; |
bte_o <= #1 2'b00; |
we_o <= #1 1'b0; |
end |
else |
if (rst_i) |
begin |
cyc_o <= #1 1'b0; |
stb_o <= #1 1'b0; |
sel_o <= #1 4'b1111; |
cti_o <= #1 3'b000; |
bte_o <= #1 2'b00; |
we_o <= #1 1'b0; |
end |
else |
begin |
cyc_o <= #1 wb_cycle; |
stb_o <= #1 wb_cycle; |
sel_o <= #1 4'b1111; // only 32bit accesses are supported |
we_o <= #1 1'b0; // read only |
|
if (vmem_ack | cur_ack) |
cti_o <= #1 cti; // cycle type |
|
bte_o <= #1 2'b00; // linear burst |
end |
|
// |
// video-data buffer (temporary store data read from video memory) |
vga_fifo #(4, 32) data_fifo ( |
478,7 → 495,7
.full() |
); |
|
assign nvmem_req = data_fifo_hfull; |
assign vmem_req_n = data_fifo_hfull; |
|
// |
// hookup color processor |
511,19 → 528,19
|
assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ; |
|
always@(posedge clk_i) |
if (sclr) |
scursor1_en <= #1 1'b0; |
else if (cursor1_ld_strb) |
scursor1_en <= #1 cursor1_en; |
always @(posedge clk_i) |
if (sclr) |
scursor1_en <= #1 1'b0; |
else if (cursor1_ld_strb) |
scursor1_en <= #1 cursor1_en; |
|
always@(posedge clk_i) |
if (cursor1_ld_strb) |
scursor1_xy <= #1 cursor1_xy; |
always @(posedge clk_i) |
if (cursor1_ld_strb) |
scursor1_xy <= #1 cursor1_xy; |
|
always@(posedge clk_i) |
if (cursor1_ld_strb) |
scursor1_res <= #1 cursor1_res; |
always @(posedge clk_i) |
if (cursor1_ld_strb) |
scursor1_res <= #1 cursor1_res; |
|
vga_curproc hw_cursor1 ( |
.clk(clk_i), |
547,15 → 564,15
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled) |
reg sddImDoneFifoQ, sdImDoneFifoQ; |
|
always@(posedge clk_i) |
if (ssel1_wreq) |
begin |
sdImDoneFifoQ <= #1 dImDoneFifoQ; |
sddImDoneFifoQ <= #1 sdImDoneFifoQ; |
end |
always @(posedge clk_i) |
if (ssel1_wreq) |
begin |
sdImDoneFifoQ <= #1 dImDoneFifoQ; |
sddImDoneFifoQ <= #1 sdImDoneFifoQ; |
end |
`endif |
|
`else // Hardware Cursor1 disabled, generate pass-through signals |
`else // Hardware Cursor1 disabled, generate pass-through signals |
assign ssel1_wreq = color_proc_wreq; |
assign ssel1_q = color_proc_q; |
|
579,19 → 596,19
|
assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ; |
|
always@(posedge clk_i) |
if (sclr) |
scursor0_en <= #1 1'b0; |
else if (cursor0_ld_strb) |
scursor0_en <= #1 cursor0_en; |
always @(posedge clk_i) |
if (sclr) |
scursor0_en <= #1 1'b0; |
else if (cursor0_ld_strb) |
scursor0_en <= #1 cursor0_en; |
|
always@(posedge clk_i) |
if (cursor0_ld_strb) |
scursor0_xy <= #1 cursor0_xy; |
always @(posedge clk_i) |
if (cursor0_ld_strb) |
scursor0_xy <= #1 cursor0_xy; |
|
always@(posedge clk_i) |
if (cursor0_ld_strb) |
scursor0_res <= #1 cursor0_res; |
always @(posedge clk_i) |
if (cursor0_ld_strb) |
scursor0_res <= #1 cursor0_res; |
|
vga_curproc hw_cursor0 ( |
.clk(clk_i), |
619,7 → 636,7
`endif |
|
// |
// hookup RGB buffer (temporary station between WISHBONE-clock-domain |
// hookup RGB buffer (temporary station between WISHBONE-clock-domain |
// and pixel-clock-domain) |
// The cursor_processor pipelines introduce a delay between the color |
// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate |
641,8 → 658,3
assign line_fifo_wreq = rgb_fifo_rreq; |
|
endmodule |
|
|
|
|
|
/trunk/rtl/verilog/vga_enh_top.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: vga_enh_top.v,v 1.2 2002-03-04 11:01:59 rherveille Exp $ |
// $Id: vga_enh_top.v,v 1.3 2003-03-18 21:45:48 rherveille Exp $ |
// |
// $Date: 2002-03-04 11:01:59 $ |
// $Revision: 1.2 $ |
// $Date: 2003-03-18 21:45:48 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/04 11:01:59 rherveille |
// Added 64x64pixels 4bpp hardware cursor support. |
// |
// Revision 1.1 2002/02/07 05:42:10 rherveille |
// Fixed some bugs discovered by modified testbench |
// Removed / Changed some strange logic constructions |
58,9 → 61,10
`include "vga_defines.v" |
|
module vga_enh_top (wb_clk_i, wb_rst_i, rst_i, wb_inta_o, |
wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o, |
wbm_adr_o, wbm_dat_i, wbm_cab_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i, |
clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o); |
wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o, |
wbm_adr_o, wbm_dat_i, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i, |
clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o |
); |
|
// |
// parameters |
96,7 → 100,8
output wbm_we_o; // write enable output |
output wbm_stb_o; // strobe output |
output wbm_cyc_o; // valid bus cycle output |
output wbm_cab_o; // continuos address burst output |
output [ 3:0] wbm_cti_o; // cycle type identifier |
output [ 1:0] wbm_bte_o; // burst type extensions |
input wbm_ack_i; // bus cycle acknowledge input |
input wbm_err_i; // bus cycle error input |
|
142,7 → 147,7
wire ihsync, ivsync, icsync, iblank; // intermediate horizontal/vertical/composite sync, intermediate blank |
|
// line fifo connections |
wire line_fifo_dpm_wreq; |
wire line_fifo_dpm_wreq, line_fifo_empty_rd; |
wire [23:0] line_fifo_dpm_d, line_fifo_dpm_q; |
|
// clut connections |
157,7 → 162,7
// |
|
// hookup wishbone slave |
vga_wb_slave u1 ( |
vga_wb_slave wbs ( |
// wishbone interface |
.clk_i(wb_clk_i), |
.rst_i(wb_rst_i), |
205,7 → 210,7
.hint_in(hint), // horizontal interrupt |
.vint_in(vint), // vertical interrupt |
.luint_in(luint), // line fifo underrun interrupt |
.sint_in(sint), // system-error interrupt |
.sint_in(sint), // system-error interrupt |
.Thsync(Thsync), |
.Thgdel(Thgdel), |
.Thgate(Thgate), |
222,7 → 227,7
); |
|
// hookup wishbone master |
vga_wb_master u2 ( |
vga_wb_master wbm ( |
// wishbone interface |
.clk_i(wb_clk_i), |
.rst_i(wb_rst_i), |
229,7 → 234,8
.nrst_i(arst), |
.cyc_o(wbm_cyc_o), |
.stb_o(wbm_stb_o), |
.cab_o(wbm_cab_o), |
.cti_o(wbm_cti_o), |
.bte_o(wbm_bte_o), |
.we_o(wbm_we_o), |
.adr_o(wbm_adr_o), |
.sel_o(wbm_sel_o), |
302,7 → 308,7
); |
|
// hookup pixel and video timing generator |
vga_pgen u3 ( |
vga_pgen pixel_generator ( |
.mclk(wb_clk_i), |
.pclk(clk_p_i), |
.ctrl_ven(ctrl_ven), |
329,16 → 335,16
|
|
// delay video control signals 1 clock cycle (dual clock fifo synchronizes output) |
always@(posedge clk_p_i) |
always @(posedge clk_p_i) |
begin |
hsync_pad_o <= #1 ihsync; |
vsync_pad_o <= #1 ivsync; |
csync_pad_o <= #1 icsync; |
blank_pad_o <= #1 iblank; |
hsync_pad_o <= #1 ihsync; |
vsync_pad_o <= #1 ivsync; |
csync_pad_o <= #1 icsync; |
blank_pad_o <= #1 iblank; |
end |
|
// hookup line-fifo |
vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) u4 ( |
vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) line_fifo ( |
.rclk(clk_p_i), |
.wclk(wb_clk_i), |
.aclr(ctrl_ven), |
359,30 → 365,30
// generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt) |
reg luint_pclk, sluint; |
|
always@(posedge clk_p_i) |
luint_pclk <= #1 cgate & line_fifo_empty_rd; |
always @(posedge clk_p_i) |
luint_pclk <= #1 cgate & line_fifo_empty_rd; |
|
always@(posedge wb_clk_i or negedge arst) |
if (!arst) |
begin |
sluint <= #1 1'b0; |
luint <= #1 1'b0; |
end |
else if (wb_rst_i) |
begin |
sluint <= #1 1'b0; |
luint <= #1 1'b0; |
end |
else if (!ctrl_ven) |
begin |
sluint <= #1 1'b0; |
luint <= #1 1'b0; |
end |
else |
begin |
sluint <= #1 luint_pclk; // resample at wb_clk_i clock |
luint <= #1 sluint; // sample again, reduce metastability risk |
end |
always @(posedge wb_clk_i or negedge arst) |
if (!arst) |
begin |
sluint <= #1 1'b0; |
luint <= #1 1'b0; |
end |
else if (wb_rst_i) |
begin |
sluint <= #1 1'b0; |
luint <= #1 1'b0; |
end |
else if (!ctrl_ven) |
begin |
sluint <= #1 1'b0; |
luint <= #1 1'b0; |
end |
else |
begin |
sluint <= #1 luint_pclk; // resample at wb_clk_i clock |
luint <= #1 sluint; // sample again, reduce metastability risk |
end |
|
endmodule |
|
/trunk/rtl/verilog/generic_dpram.v
66,6 → 66,23
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/09/28 08:18:52 rherveille |
// Changed synthesizeable FPGA memory implementation. |
// Fixed some issues with Xilinx BlockRAM |
// |
// Revision 1.3 2001/11/09 00:34:18 samg |
// minor changes: unified with all common rams |
// |
// Revision 1.2 2001/11/08 19:11:31 samg |
// added valid checks to behvioral model |
// |
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille |
// Major cleanup. |
// Files are now compliant to Altera & Xilinx memories. |
// Memories are now compatible, i.e. drop-in replacements. |
// Added synthesizeable generic FPGA description. |
// Created "generic_memories" cvs entry. |
// |
// Revision 1.1.1.2 2001/08/21 13:09:27 damjan |
// *** empty log message *** |
// |
80,9 → 97,11
// |
// |
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
//`define VENDOR_FPGA |
`define VENDOR_FPGA |
//`define VENDOR_XILINX |
//`define VENDOR_ALTERA |
|
129,22 → 148,22
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs. |
// |
|
reg [dw-1 :0] mem [(1<<aw) -1:0]; // instantiate memory |
reg [dw-1:0] do; // data output registers |
// NOTE: |
// 'synthesis syn_ramstyle="block_ram"' is a Synplify attribute. |
// It instructs Synplify to map to BlockRAMs instead of the default SelectRAMs |
|
reg [dw-1:0] mem [(1<<aw) -1:0] /* synthesis syn_ramstyle="block_ram" */; |
reg [aw-1:0] ra; // register read address |
|
// read operation |
always @(posedge rclk) |
if (rce) |
ra <= #1 raddr; |
|
/* |
always@(posedge rclk) |
if (rce) // clock enable instructs Xilinx tools to use SelectRAM (LUTS) instead of BlockRAM |
do <= #1 mem[raddr]; |
*/ |
assign do = mem[ra]; |
|
always@(posedge rclk) |
do <= #1 mem[raddr]; |
|
// write operation |
always@(posedge wclk) |
always @(posedge wclk) |
if (we && wce) |
mem[waddr] <= #1 di; |
|
295,18 → 314,18
// |
// Generic RAM's registers and wires |
// |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content |
reg [dw-1:0] do_reg; // RAM data output register |
|
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'bz}}; |
assign do = (oe & rce) ? do_reg : {dw{1'bz}}; |
|
// read operation |
always @(posedge rclk) |
if (rce) |
do_reg <= #1 mem[raddr]; |
do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr]; |
|
// write operation |
always @(posedge wclk) |
313,6 → 332,19
if (wce && we) |
mem[waddr] <= #1 di; |
|
|
// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
task print_ram; |
input [aw-1:0] start; |
input [aw-1:0] finish; |
integer rnum; |
begin |
for (rnum=start;rnum<=finish;rnum=rnum+1) |
$display("Addr %h = %h",rnum,mem[rnum]); |
end |
endtask |
|
`endif // !VENDOR_VIRAGE |
`endif // !VENDOR_AVANT |
`endif // !VENDOR_ARTISAN |