URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 422 to Rev 423
- ↔ Reverse comparison
Rev 422 → Rev 423
/trunk/or1ksim/testbench/defaultmem.cfg
1,3 → 1,3
>00000000 00040000 flash |
>40000000 00010000 RAM |
>00000000 00200000 flash |
>40000000 00200000 RAM |
|
/trunk/or1ksim/testbench/acv_uart.c
41,7 → 41,7
#define LSR_TXE (0x40) |
#define LSR_ERR (0x80) |
|
#define UART_INT_LINE 4 /* To which interrupt is uart connected */ |
#define UART_INT_LINE 15 /* To which interrupt is uart connected */ |
|
/* fails if x is false */ |
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__)) |
350,8 → 350,8
MARK(); |
while (!((x = getreg (UART_LSR)) & LSR_DR)); |
/* we should receive zero character with broken frame and break bit should be set */ |
printf("[%x]\n", (LSR_DR | LSR_FE | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE)); |
ASSERT (x == (LSR_DR | LSR_FE | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE)); |
printf("[%x]\n", (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE)); |
ASSERT (x == (LSR_DR | LSR_BREAK | LSR_ERR | LSR_TXFE | LSR_TXE)); |
ASSERT (getreg (UART_RBR) == 0); |
MARK(); |
|
383,8 → 383,8
while (!((x = getreg (UART_LSR)) & LSR_DR)); |
/* we should receive zero character with broken frame and break bit |
should not be set, because we cleared it */ |
printf("[%x:%x]\n", x, (LSR_DR | LSR_FE | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE)); |
ASSERT (x == (LSR_DR | LSR_FE | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE)); |
printf("[%x:%x]\n", x, (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE)); |
ASSERT (x == (LSR_DR | LSR_BREAK |LSR_ERR | LSR_TXFE | LSR_TXE)); |
ASSERT (getreg (UART_RBR) == 0); |
MARK(); |
send_char ('?'); |
466,6 → 466,9
setreg (UART_DLL, 2 & 0xff); |
setreg (UART_LCR, 0x03); /* 8N1 @ 2 */ |
MARK(); |
while (!(getreg (UART_LSR) & 1)); /* Receive 'x' char */ |
getreg (UART_RBR); |
MARK(); |
|
send_char ('T'); |
while (getreg (UART_LSR) != 0x60); /* Wait for THR to be empty */ |
486,11 → 489,19
setreg (UART_DLL, 6 & 0xff); |
setreg (UART_LCR, 0x03); /* 8N1 @ 6 */ |
|
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */ |
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */ |
setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */ |
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */ |
MARK(); |
|
|
#if 0 |
while (!int_cnt); /* Clear previous THR interrupt */ |
ASSERT (--int_cnt == 0); |
ASSERT (int_iir == 0xc2); |
ASSERT ((int_lsr & 0xbe) == 0x20); |
MARK(); |
#endif |
|
/* I am configured - start interrupt test */ |
send_char ('I'); |
while (!int_cnt); /* Wait for THR to be empty */ |
607,7 → 618,7
while (!int_cnt); /* Wait for break interrupt */ |
ASSERT (--int_cnt == 0); |
ASSERT (int_iir == 0xc6); |
ASSERT (int_lsr == 0xf9); /* BE flag should be set */ |
ASSERT (int_lsr == 0xf1); /* BE flag should be set */ |
ASSERT (getreg (UART_LSR) == 0x61); /* BE flag should be cleared by previous read */ |
MARK(); |
recv_char (0); |
769,9 → 780,9
init_8n1 (); |
// send_recv_test (); |
// break_test (); |
// different_modes_test (); |
// interrupt_test (); |
// control_register_test (); |
different_modes_test (); |
interrupt_test (); |
control_register_test (); |
line_error_test (); |
|
/* loopback_test (); |
/trunk/or1ksim/testbench/acv_uart.cfg
37,7 → 37,7
baseaddr = 0x9c000000 |
jitter = -1 /* async behaviour */ |
16550 = 1 |
irq = 4 |
irq = 15 |
vapi_id = 0x100 |
enddevice |
end |
/trunk/or1ksim/peripheral/16450.c
100,7 → 100,6
uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value; |
|
uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE); |
|
uarts[chipsel].istat.thre_int = 0; |
break; |
case UART_FCR: |
122,7 → 121,9
break; |
case UART_IER: |
uarts[chipsel].regs.ier = value & UART_VALID_IER; |
uarts[chipsel].istat.thre_int = 0; |
#if 0 |
uarts[chipsel].istat.thre_int = 1; |
#endif |
break; |
case UART_LCR: |
uarts[chipsel].regs.lcr = value & UART_VALID_LCR; |
378,7 → 379,8
|
uarts[i].istat.break_set = 0; |
uarts[i].istat.timeout_count = 0; |
|
uarts[i].istat.thre_int = 0; |
|
uarts[i].regs.lcr = UART_LCR_RESET; |
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0; |
uarts[i].vapi.next_break_cnt = -1; |
449,8 → 451,7
if (!uarts[i].istat.break_set) { |
unsigned lsr; |
uarts[i].istat.break_set = 1; |
lsr = UART_LSR_BREAK | UART_LSR_FRAME | UART_LSR_RXERR | UART_LSR_RDRDY; |
if (uarts[i].regs.lcr & UART_LCR_PARITY) lsr |= UART_LSR_PARITY; |
lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY; |
printf ("[%x]\n", uarts[i].regs.lsr); |
uarts[i].istat.rxser_full = 0; |
uarts[i].istat.rxser_clks = 0; |
/trunk/or1ksim/peripheral/16450.h
173,10 → 173,10
#define UART_FCR_RRXFI 0x02 /* Reset rx FIFO */ |
#define UART_FCR_RTXFI 0x04 /* Reset tx FIFO */ |
#define UART_FIFO_TRIGGER(x) /* Trigger values for indexes 0..3 */\ |
((x)==0?1\ |
:(x)==1?4\ |
:(x)==2?8\ |
:(x)==3?14:0) |
((x) == 0 ? 1\ |
:(x) == 1 ? 4\ |
:(x) == 2 ? 8\ |
:(x) == 3 ? 14 : 0) |
|
/* |
* Bit definitions for the Interrupt Enable Register |
210,5 → 210,5
/* |
* Various definitions |
*/ |
#define UART_BREAK_COUNT (4) /* # of chars to count when performing break */ |
#define UART_BREAK_COUNT (1) /* # of chars to count when performing break */ |
#define UART_CHAR_TIMEOUT (4) /* # of chars to count when performing timeout int. */ |