URL
https://opencores.org/ocsvn/t51/t51/trunk
Subversion Repositories t51
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 43 to Rev 44
- ↔ Reverse comparison
Rev 43 → Rev 44
/trunk/rtl/vhdl/T51_UART.vhd
4,7 → 4,7
-- Version : 0300 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
44,7 → 44,7
-- Limitations : |
-- |
-- File history : |
-- |
-- 15-Jan-06 : Bugfix for writing SCON Register in mode 0 |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
194,8 → 194,11
if SC_Wr = '1' then |
SCON(0) <= Data_In(0); |
SCON(2) <= Data_In(2); |
RX_Shifting <= '0'; |
-- RX_Shifting <= '0'; |
end if; |
if SCON(7 downto 6) /= "00" then |
RX_Shifting <= '0'; |
end if; |
if SCON(7 downto 6) = "00" and Tick6 = '1' and (TXD_i = '0' or RX_Bit_Cnt = 0) then |
if SCON(4) = '1' and SCON(0) = '0' and RX_Bit_Cnt = 0 then |
RX_Shifting <= '1'; |
287,12 → 290,15
elsif Clk'event and Clk = '1' then |
if SC_Wr = '1' then |
SCON(1) <= Data_In(1); |
TX_Shifting <= '0'; |
-- TX_Shifting <= '0'; |
end if; |
if SB_Wr = '1' then |
TX_Data <= Data_In; |
TX_Start <= '1'; |
end if; |
if SCON(7 downto 6) /= "00" then |
TX_Shifting <= '0'; |
end if; |
if Tick6 = '1' and (RX_Shifting = '1' or TX_Shifting = '1') then |
TXD_i <= not TXD_i; |
end if; |
/trunk/rtl/vhdl/T51_Pack.vhd
4,7 → 4,7
-- Version : 0300 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
220,14 → 220,7
TH2_Wr : out std_logic; |
SCON_Wr : out std_logic; |
SBUF_Wr : out std_logic; |
Int_Trig : out std_logic_vector(6 downto 0); |
-- SevenSeg Controller |
SevSeg_Con_Sel : out std_logic; |
SevSeg_Con_Wr : out std_logic; |
SevSeg_DataL_Sel : out std_logic; |
SevSeg_DataL_Wr : out std_logic; |
SevSeg_DataH_Sel : out std_logic; |
SevSeg_DataH_Wr : out std_logic |
Int_Trig : out std_logic_vector(6 downto 0) |
); |
end component; |
|
/trunk/rtl/vhdl/T51.vhd
4,7 → 4,7
-- Version : 0300 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
/trunk/rtl/vhdl/T51_Port.vhd
4,7 → 4,7
-- Version : 0300 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
69,20 → 69,7
); |
end T51_Port; |
|
architecture rtl of T51_Port is |
-- component InputSync |
-- port ( |
-- Input : in std_ulogic; |
-- clk : in std_ulogic; |
-- clr_n : in std_ulogic; |
-- q : out std_ulogic); |
-- end component; |
-- component PULLUP |
-- port ( |
-- O : out std_logic |
-- ); |
-- end component; |
|
architecture rtl of T51_Port is |
signal Port_Output : std_logic_vector(7 downto 0); |
signal Port_Input : std_logic_vector(7 downto 0); |
-- signal P_trans : std_logic_vector(7 downto 0); |
101,19 → 88,9
end generate; |
|
iop: for i in 0 to 7 generate |
-- IOPort(i) <= '0' when Port_Output(i) = '0' else 'Z'; |
-- P_PULLUP: PULLUP port map(O =>IOPort(i)); |
-- IOPort(i) <= 'H'; |
|
IOPort_out(i) <= Port_Output(i); |
Port_Input(i)<=To_X01Z(IOPort_in(i)); |
|
|
-- ISP : InputSync |
-- port map ( |
-- Input => P_trans(i), |
-- clk => clk, |
-- clr_n => Rst_n, |
-- q => Port_Input(i)); |
Port_Input(i) <= To_X01Z(IOPort_in(i)); |
end generate; |
|
process (Rst_n, Clk) |
/trunk/rtl/vhdl/T8032.vhd
4,7 → 4,7
-- Version : 0222 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
/trunk/rtl/vhdl/T8052.vhd
4,7 → 4,7
-- Version : 0300 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
77,12 → 77,14
RXD_IsO : out std_logic; |
RXD_O : out std_logic; |
TXD : out std_logic; |
ExSel : out std_logic; |
ExRd : out std_logic; |
ExWr : out std_logic; |
ExAddr : out std_logic_vector(15 downto 0); |
ExDI : in std_logic_vector(7 downto 0); |
ExDO : out std_logic_vector(7 downto 0) |
-- External XRAM Wishbone: |
XRAM_WE_O : out std_logic; |
XRAM_STB_O : out std_logic; |
XRAM_CYC_O : out std_logic; |
XRAM_ACK_I : in std_logic; |
XRAM_DAT_O : out std_logic_vector(7 downto 0); |
XRAM_ADR_O : out std_logic_vector(15 downto 0); |
XRAM_DAT_I : in std_logic_vector(7 downto 0) |
); |
end T8052; |
|
126,9 → 128,12
signal RAM_Rd : std_logic; |
signal RAM_Wr : std_logic; |
signal RAM_WE_n : std_logic; |
signal RAM_Sel_Addr : std_logic_vector(15 downto XRAMAddressWidth); |
signal RAM_Sel_n : std_logic; |
signal Ex_Sel_i : std_logic; |
signal zeros : std_logic_vector(15 downto XRAMAddressWidth); |
signal ram_access : std_logic; |
signal mux_sel : std_logic; |
signal mux_sel_r : std_logic; |
signal ext_ram_en : std_logic; |
signal int_xram_sel_n : std_logic; |
signal IO_Rd : std_logic; |
signal IO_Wr : std_logic; |
signal IO_Addr : std_logic_vector(6 downto 0); |
190,43 → 195,63
|
begin |
|
Ready <= '1'; |
Ready <= '0' when (XRAM_ACK_I='0' and (ext_ram_en and ram_access)='1') else |
'1'; |
|
ExSel <= Ex_Sel_i; |
ExRd <= RAM_Rd; |
ExWr <= RAM_Wr; |
ExDO <= RAM_WData; |
XRAM_ADR_O <= XRAM_Addr(15 downto 0); -- Registered address |
XRAM_DAT_O <= RAM_WData; |
XRAM_CYC_O <= ext_ram_en and ram_access; |
XRAM_STB_O <= ext_ram_en and ram_access; |
XRAM_WE_O <= RAM_Wr; |
|
process (Clk) |
begin |
if Clk'event and Clk = '1' then |
IO_Addr_r <= IO_Addr; |
Ex_Sel_i <= RAM_Sel_n; |
RAM_Addr_r <= RAM_Addr; |
end if; |
end process; |
process (Rst_n,clk) |
begin |
if Rst_n='0' then |
IO_Addr_r <= (others =>'0'); |
RAM_Addr_r <= (others =>'0'); |
mux_sel_r <= '0'; |
elsif clk'event and clk = '1' then |
IO_Addr_r <= IO_Addr; |
if Ready = '1' then |
RAM_Addr_r <= RAM_Addr; |
end if; |
mux_sel_r <= mux_sel; |
end if; |
end process; |
|
XRAM_Addr <= RAM_Addr_r; |
|
ExAddr <= XRAM_Addr; |
|
rom : ROM52 port map( |
Clk => Clk, |
A => ROM_Addr(ROMAddressWidth - 1 downto 0), |
D => ROM_Data); |
|
zeros <= (others => '0'); |
g_rams0 : if XRAMAddressWidth > 15 generate |
RAM_Sel_n <= '0'; |
ext_ram_en <= '0'; -- no external XRAM |
end generate; |
|
g_rams1 : if XRAMAddressWidth < 16 and XRAMAddressWidth > 0 generate |
RAM_Sel_n <= '0' when RAM_Addr(15 downto XRAMAddressWidth) = RAM_Sel_Addr else '1'; |
ext_ram_en <= '1' when XRAM_Addr(15 downto XRAMAddressWidth) /= zeros else |
'0'; |
end generate; |
|
RAM_Sel_Addr <= (others => '0'); |
RAM_WE_n <= not RAM_Wr; |
RAM_RData <= ExDI when Ex_Sel_i = '1' else RAM_DO; |
ram_access <= '1' when (RAM_Rd or RAM_Wr)='1' else |
'0'; |
|
-- xram bus access is pipelined. |
-- so use registered signal for selecting read data |
RAM_RData <= RAM_DO when mux_sel_r = '0' else |
XRAM_DAT_I; |
|
-- select data mux |
mux_sel <= ext_ram_en; |
|
-- internal XRAM select signal is active low. |
-- so internal xram is selected when external XRAM is not selected (ext_ram_en = '0') |
int_xram_sel_n <= ext_ram_en; |
RAM_WE_n <= not RAM_Wr; |
|
g_ram : if XRAMAddressWidth > 0 generate |
ram : SSRAM |
generic map( |
233,7 → 258,7
AddrWidth => XRAMAddressWidth) |
port map( |
Clk => Clk, |
CE_n => Ex_Sel_i, |
CE_n => int_xram_sel_n, |
WE_n => RAM_WE_n, |
A => XRAM_Addr(XRAMAddressWidth - 1 downto 0), |
DIn => RAM_WData, |
/trunk/rtl/vhdl/T51_Glue.vhd
4,7 → 4,7
-- Version : 0300 |
-- |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.ac.at) |
-- (c) 2004-2005 Andreas Voggeneder (andreas.voggeneder@fh-hagenberg.at) |
-- |
-- All rights reserved |
-- |
106,15 → 106,7
TH2_Wr : out std_logic; |
SCON_Wr : out std_logic; |
SBUF_Wr : out std_logic; |
Int_Trig : out std_logic_vector(6 downto 0); |
-- SevenSeg Controller |
SevSeg_Con_Sel : out std_logic; |
SevSeg_Con_Wr : out std_logic; |
SevSeg_DataL_Sel : out std_logic; |
SevSeg_DataL_Wr : out std_logic; |
SevSeg_DataH_Sel : out std_logic; |
SevSeg_DataH_Wr : out std_logic |
|
Int_Trig : out std_logic_vector(6 downto 0) |
); |
end T51_Glue; |
|
259,12 → 251,4
SCON_Wr <= '1' when IO_Addr_r = "0011000" and IO_Wr = '1' else '0'; |
SBUF_Sel <= '1' when IO_Addr = "0011001" else '0'; |
SBUF_Wr <= '1' when IO_Addr_r = "0011001" and IO_Wr = '1' else '0'; |
|
-- SevenSeg Controller |
SevSeg_Con_Sel <= '1' when IO_Addr = "0010001" else '0'; -- 0x91 |
SevSeg_Con_Wr <= '1' when IO_Addr_r = "0010001" and IO_Wr = '1' else '0'; |
SevSeg_DataL_Sel <= '1' when IO_Addr = "0010010" else '0'; -- 0x92 |
SevSeg_DataL_Wr <= '1' when IO_Addr_r = "0010010" and IO_Wr = '1' else '0'; |
SevSeg_DataH_Sel <= '1' when IO_Addr = "0010011" else '0'; -- 0x93 |
SevSeg_DataH_Wr <= '1' when IO_Addr_r = "0010011" and IO_Wr = '1' else '0'; |
end; |